WO2016090725A1 - 一种ltps阵列基板 - Google Patents

一种ltps阵列基板 Download PDF

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WO2016090725A1
WO2016090725A1 PCT/CN2015/070629 CN2015070629W WO2016090725A1 WO 2016090725 A1 WO2016090725 A1 WO 2016090725A1 CN 2015070629 W CN2015070629 W CN 2015070629W WO 2016090725 A1 WO2016090725 A1 WO 2016090725A1
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layer
storage capacitor
transparent conductive
array substrate
electrode line
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French (fr)
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王聪
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/420,901 priority Critical patent/US9711540B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an LTPS array substrate.
  • Low temperature poly-silicon (LTPS) thin film transistor liquid crystal display is different from traditional amorphous silicon thin film transistor liquid crystal display, and its electron mobility can reach 200cm2/V-sec or more, which can effectively reduce thin film transistor device.
  • the area is increased to achieve an increase in aperture ratio, and the overall brightness can be reduced while increasing the brightness of the display.
  • the higher electron mobility can integrate part of the driving circuit on the glass substrate, which reduces the driving IC, and can also greatly improve the reliability of the liquid crystal display panel, thereby greatly reducing the manufacturing cost of the panel. Therefore, LTPS thin film transistor liquid crystal displays have gradually become a research hotspot.
  • the LTPS thin film transistor liquid crystal display mainly includes an array substrate and a color filter substrate disposed opposite thereto.
  • the array substrate of the LTPS has a capacitance composed of a bottom common electrode and a pixel electrode separated by an insulating layer as a storage capacitor of a pixel corresponding thereto, but the storage capacitance of such a structure is small, and the power of the array substrate cannot be satisfied. Capacitance requirements after saturation.
  • the present invention provides an LTPS array substrate which increases the storage capacitance without lowering the aperture ratio.
  • the present invention provides an LTPS array substrate including a plurality of low temperature polysilicon thin film transistors, each of which includes a substrate;
  • a gate insulating layer formed on the patterned polysilicon layer and the buffer layer;
  • first metal layer Forming a first metal layer on the gate insulating layer, patterning the first metal layer to form a gate electrode line and a common electrode line, the common electrode line, the polysilicon corresponding to the common electrode line a second portion of the layer and a gate insulating layer sandwiched between the common electrode line and the second portion to form a first storage capacitor;
  • a second metal layer formed on the insulating layer is patterned to form a drain electrode and a source electrode, the drain electrode extends with an extension, and the extension is projected onto the common An electrode line, and an extension of the drain electrode and the common electrode line and an insulating layer between the extension and the common electrode line form a second storage capacitor; the second storage capacitor and the first Storage capacitors are placed in parallel, and
  • the LTPS array substrate further includes a patterned underlying transparent conductive layer formed on the planar layer, an extension of the underlying transparent conductive layer and the drain electrode, and a transparent conductive layer at the extension and the bottom transparent conductive layer.
  • the flat layer forms a third storage capacitor, and the third storage capacitor is disposed in parallel with the second storage capacitor and the first storage capacitor.
  • the LTPS array substrate further includes a protective layer formed on the patterned underlying transparent conductive layer; and a top transparent conductive layer formed on the protective layer, the top transparent conductive layer and the bottom transparent conductive layer And a protective layer between the top transparent conductive layer and the bottom transparent conductive to form a fourth storage capacitor, the fourth storage capacitor and the third storage capacitor, the second storage capacitor, and the first storage capacitor Parallel settings.
  • the second metal layer is formed on the insulating layer and electrically connected to the polysilicon layer through via holes.
  • the top transparent conductive layer is formed on the protective layer and electrically connected to the drain electrode through a via.
  • the thickness of the flat layer on the extension of the drain electrode is less than the thickness of other locations of the flat layer.
  • the gate insulating layer is made of one of silicon oxide, silicon nitride and silicon oxynitride.
  • the material of the first metal layer and the second metal layer is a conductive material such as molybdenum aluminum alloy or chrome metal.
  • the flat layer material is an organic film.
  • the flat layer is formed by a photomask process.
  • An LTPS array substrate of the present invention adds a second portion through the patterned polysilicon layer, and forms an extension portion of the drain electrode over the second portion, thereby forming four parallel storage capacitors without reducing the aperture ratio. Next, increase the storage capacitance of the array substrate.
  • FIG. 1 is a cross-sectional view of a LTPS array substrate in accordance with a preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a LTPS array substrate according to another preferred embodiment of the present invention.
  • the LTPS array substrate is different from that of FIG. 1 in the thickness of a portion of the planar layer.
  • FIG. 1 is a schematic structural diagram of a LTPS array substrate including a plurality of low temperature polysilicon thin film transistors, a bottom transparent conductive layer 32, a protective layer 34, and a top transparent layer according to a preferred embodiment of the present invention.
  • Conductive layer 36 In this embodiment, a low temperature polysilicon thin film transistor is taken as an example for description.
  • Each of the low temperature polysilicon thin film transistors includes a substrate 10, a patterned light shielding layer 12, a buffer layer 14, an imaged polysilicon layer 16, a gate insulating layer 18, a gate electrode line 20, and a common electrode. Line 22, insulating layer 24, drain electrode 26 and source electrode and flat layer 30.
  • the imaged polysilicon layer 16 includes a first portion 161 and a second portion 162.
  • the drain electrode 26 extends with an extension 262.
  • the extension portion 262 is disposed corresponding to the second portion 162. details as follows:
  • the substrate 10 is typically a transparent glass sheet.
  • the patterned light shielding layer 12 is formed on the substrate 10, wherein the patterning refers to a process of performing exposure etching on the light shielding layer material coated on the entire substrate 10, and finally forming the patterning.
  • the material of the light shielding layer 12 is, for example, molybdenum aluminum alloy, chrome metal, molybdenum metal or other materials having both light shielding function and conductive property.
  • the buffer layer 14 is formed on the substrate 10 and the patterned light shielding layer 12.
  • the patterned polysilicon layer 16 is formed on the buffer layer 14.
  • the patterning refers to processing by performing exposure etching on polysilicon coated on the buffer layer 14.
  • the patterned polysilicon layer 16 includes a first portion 161 that is projected onto the light shielding layer 12 and a second portion 162 that extends away from the light shielding layer 12.
  • the plane in which the second portion 162 is located is in the same plane as the buffer layer 14 that is projected on the portion of the light shielding layer 12.
  • the gate insulating layer 18 is formed on the patterned polysilicon layer 16 and on the buffer layer 14.
  • the gate insulating layer 18 is made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • a first metal layer (not labeled) is formed on the gate insulating layer 18, and the gate electrode line 20 and the common electrode line 22 are formed by patterning the first metal layer, the common electrode line 22, and the The second portion 162 of the polysilicon layer 16 corresponding to the common electrode line 22 and the gate insulating layer 18 sandwiched between the common electrode line 22 and the second portion 162 of the polysilicon layer 16 constitute the first A storage capacitor C 1 .
  • the common electrode line 22 is located directly above the second portion 162.
  • the insulating layer 24 is formed on the gate insulating layer 18 and the gate electrode line 20 and the common electrode line 22.
  • a first via (not labeled) penetrating through the insulating layer 24 and the gate insulating layer 18 is formed by etching, and the first via exposes a portion of the patterned polysilicon layer 16.
  • a second metal layer (not labeled) is formed on the insulating layer 24, and the drain electrode 26 and the source electrode are formed by patterning the second metal layer.
  • the drain electrode 26 extends with an extension 262 that is projected above the common electrode line 22.
  • the extension portion 262 of the drain electrode 26 and the common electrode line 22 and the insulating layer 24 between the extension portion 262 and the common electrode line 22 form a second storage capacitor C 2 .
  • the second storage capacitor C 2 is disposed in parallel with the first storage capacitor C 1 .
  • the second metal layer is formed on the insulating layer 24 and electrically connected to the patterned polysilicon layer 16 through the first via, that is, the drain electrode 26 and the source electrode pass through The first via is electrically connected to the patterned polysilicon layer 16.
  • the material of the first metal layer and the second metal layer is a conductive material such as molybdenum aluminum alloy or chrome metal.
  • the flat layer 30 is formed on the insulating layer 24 and the patterned second metal layer.
  • the material of the flat layer 30 is an organic film.
  • the flat layer 30 is formed using a photomask process.
  • the LTPS array substrate further includes a patterned underlying transparent conductive layer 32 formed on the planar layer 30.
  • the bottom transparent conductive layer 32 and the extension portion 262 of the drain electrode 26 and the flat layer 30 of the extension portion 262 and the bottom transparent conductive layer 32 form a third storage capacitor C 3 , and the third storage capacitor C 3 and The second storage capacitor C 2 and the first storage capacitor C 1 are arranged in parallel.
  • the LTPS array substrate further includes a protective layer 34 formed on the patterned underlying transparent conductive layer 32; and a top transparent conductive layer 36 formed on the protective layer 34, the top transparent conductive layer A fourth storage capacitor C 4 is formed between the underlying transparent conductive layer 32 and the protective layer 34 between the top transparent conductive layer 36 and the underlying transparent conductive layer 32.
  • the fourth storage capacitor C 4 is disposed in parallel with the third storage capacitor C3, the second storage capacitor C 2, and the first storage capacitor C 1 .
  • the top transparent conductive layer 36 and the bottom transparent conductive layer 32 are respectively a pixel electrode layer and a common electrode layer of the array substrate.
  • the top transparent conductive layer 36 is formed on the protective layer 34 and electrically connected to the drain electrode 26 through a second via hole penetrating through the bottom transparent conductive layer 32, the protective layer 34 and the flat layer 30.
  • the LTPS array substrate of the present invention has a second portion 162 added through the patterned polysilicon layer 16, and an extension portion 262 of the drain electrode 26 is formed over the second portion 162, and the common electrode line 22 and the common electrode
  • the second portion 162 of the polysilicon layer 16 corresponding to the line 22 and the gate insulating layer 18 sandwiched between the common electrode line 22 and the second portion 162 of the polysilicon layer 16 constitute a first storage capacitor C 1
  • the drain electrode 26, extension portions 262 and the common electrode line 22 and the extending portion 262 is located and the insulating layer 22 between the common electrode line 24 is formed a second storage capacitor C 2; a first storage capacitor a second storage capacitor C 1 and C 2 are provided in parallel, at the same time, the LTPS array substrate further provided with a fourth storage capacitor C 4 and the third storage capacitor C3 and the second storage capacitor C 2 and the first
  • the storage capacitor C 1 is connected in parallel, and the storage capacitor is increased to reduce the capacitance requirement after the array substrate is saturated without reducing
  • the thickness of the flat layer 30 on the extension portion 262 of the drain electrode 26 is smaller than the thickness of other positions of the flat layer 30, so that the bottom layer can be reduced. the distance 262 between the transparent conductive layer 32 and the drain electrode extension portion 26, thereby increasing the third storage capacitor C 3.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种LTPS阵列基板，其包括多个低温多晶硅薄膜晶体管及底层透明导电层(32)、保护层(34)以及顶层透明导电层(36)。所述每一低温多晶硅薄膜晶体管包括依次叠加形成的基板(10)，图形化的遮光层(12)、缓冲层(14)、图像化的多晶硅层(16)、栅极绝缘层(18)、栅电极线(20)和公共电极线(22)、绝缘层(24)、漏极电极(26)和源极电极、平坦层(30)。所述底层透明导电层(32)、保护层(34)以及顶层透明导电层(36)依次叠加形成在平坦层(30)上。所述图像化的多晶硅层(16)包括第一部分(161)及第二部分(162)。所述漏极电极(26)延伸有与所述第二部分(162)相对的延伸部(262)。

Description

一种LTPS阵列基板
本发明要求2014年12月11日递交的发明名称为“一种LTPS阵列基板”的申请号201410764302.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示屏技术领域，尤其涉及一种LTPS阵列基板。
背景技术
低温多晶硅(low temperature poly-silicon，简称为LTPS)薄膜晶体管液晶显示器有别于传统的非晶硅薄膜晶体管液晶显示器，其电子迁移率可以达到200cm2/V-sec以上，可有效减小薄膜晶体管器件的面积，从而达到提高开口率，并且在增进显示器亮度的同时还可以降低整体的功耗。另外，较高的电子迁移率可以将部分驱动电路集成在玻璃基板上，减少了驱动IC，还可以大幅提升液晶显示面板的可靠度，从而使得面板的制造成本大幅降低。因此，LTPS薄膜晶体管液晶显示器逐步成为研究的热点。LTPS薄膜晶体管液晶显示器主要包括阵列基板和与其相对设置的彩膜基板。
而现有技术中的LTPS的阵列基板，通过由绝缘层隔开的底部公共电极与像素电极组成的电容作为与其对应的像素的存储电容，但是这样的结构存储电容较小，无法满足阵列基板电量饱和后的电容需求。
发明内容
本发明提供一种LTPS阵列基板，在不降低开口率的情况下，增加存储电容。
本发明提供一种LTPS阵列基板，其包括多个低温多晶硅薄膜晶体管，所述每一低温多晶硅薄膜晶体管包括一个基板；
形成于所述基板上的图形化的遮光层；
形成于所述基板和所述图形化的遮光层上的缓冲层；
形成于所述缓冲层上的图像化的多晶硅层，其中，图像化的多晶硅层包括正投影于遮光层的第一部分和远离所述遮光层延伸的第二部分；
形成于所述图形化的多晶硅层和所述缓冲层上的栅极绝缘层；
形成于所述栅极绝缘层上的第一金属层，图形化所述第一金属层形成栅电极线和公共电极线，所述公共电极线、与所述公共电极线相对应的所述多晶硅层的第二部分以及夹持在形成所述公共电极线与所述第二部分之间的栅极绝缘层构成第一存储电容；
形成于所述栅极绝缘层和栅电极线和公共电极线的绝缘层；
形成于所述绝缘层上的第二金属层，图案化所述第二金属层形成漏极电极和源极电极，所述漏极电极延伸有延伸部，所述延伸部正投影于所述公共电极线，并且所述漏极电极的延伸部与所述公共电极线以及位于所述延伸部与公共电极线之间的绝缘层形成第二存储电容；所述第二存储电容与所述第一存储电容并联设置，以及
形成于所述绝缘层和图案化后的第二金属层上的平坦层。
其中，所述LTPS阵列基板还包括形成于所述平坦层上的图形化的底层透明导电层，所述底层透明导电层与漏极电极的延伸部以及位于所述延伸部及底层透明导电层的平坦层形成第三存储电容，所述第三存储电容与所述第二存储电容及所述第一存储电容并联设置。
其中，所述LTPS阵列基板还包括形成于图案化的底层透明导电层上的保护层；以及形成于所述保护层上的顶层透明导电层，所述顶层透明导电层与所述底层透明导电层以及位于所述所述顶层透明导电层与所述底层透明导电之间的保护层形成第四存储电容，所述第四存储电容与所述第三存储电容、第二存储电容及第一存储电容并联设置。
其中，所述第二金属层形成于所述绝缘层上且通过过孔与所述多晶硅层电连接。
其中，所述顶层透明导电层形成于所述保护层上且通过过孔与所述漏极电极电连接。
其中，位于所述漏极电极的延伸部上的平坦层的厚度小于所述平坦层其它位置的厚度。
其中，所述栅极绝缘层采用氧化硅、氮化硅与氮氧化硅中的一种制成。
其中，所述第一金属层与第二金属层的材料为钼铝合金、铬金属等导电材料。
其中，所述平坦层材料为有机膜。
其中，所述平坦层采用光罩工艺形成。
本发明的一种LTPS阵列基板通过图形化的多晶硅层上增加第二部分，并在第二部分上方形成漏极电极的延伸部，进而形成四个并联的存储电容，在不降低开口率的情况下，增加阵列基板的存储电容。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的LTPS阵列基板剖面示意图。
图2为本发明另一较佳实施方式的LTPS阵列基板剖面示意图，该LTPS阵列基板与图1所述不同之处在于部分所述平坦层的厚度。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的一种LTPS阵列基板的结构示意图，所述LTPS阵列基板包括多个低温多晶硅薄膜晶体管及底层透明导电层32、保护层34以及顶层透明导电层36。而本实施例以一个低温多晶硅薄膜晶体管为例进行说明。
所述每一低温多晶硅薄膜晶体管包括一个基板10，图形化的遮光层12、缓冲层14、图像化的多晶硅层16、栅极绝缘层18、栅电极线20和公共电极 线22、绝缘层24、漏极电极26和源极电极及平坦层30。其中，所述图像化的多晶硅层16包括第一部分161及第二部分162。所述漏极电极26延伸有延伸部262。所述延伸部262与第二部分162对应设置。具体如下：
所述基板10通常为透明玻璃板。
所述基板10上形成有所述图形化的遮光层12，其中图案化是指通过对涂于整个基板10上的遮光层材料进行曝光刻蚀等工艺加工而成，最终形成所述的图案化的遮光层12。所述遮光层12的材质例如为钼铝合金、铬金属、钼金属或是其它同时具有遮光功能与导电性质的材质。
所述基板10和所述图形化的遮光层12上形成所述缓冲层14。
所述缓冲层14上形成所述图像化的多晶硅层16。其中图案化是指通过对涂于缓冲层14上的多晶硅进行曝光刻蚀等工艺加工而成。本实施例中，所述图像化的多晶硅层16包括正投影于遮光层12的第一部分161和远离所述遮光层12延伸的第二部分162。所述第二部分162所在平面与正投影于所述遮光层12部分的缓冲层14位于同一平面。
所述图形化的多晶硅层16上和所述缓冲层14上形成所述的栅极绝缘层18。所述栅极绝缘层18采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
所述栅极绝缘层18上形成有第一金属层(图未标)，并通过图形化所述第一金属层形成栅电极线20和公共电极线22，所述公共电极线22、与所述公共电极线22相对应的所述多晶硅层16的第二部分162以及夹持在形成所述公共电极线22与所述多晶硅层16的第二部分162之间的栅极绝缘层18构成第一存储电容C1。所述公共电极线22位于所述第二部分162的正上方。
所述绝缘层24形成于所述栅极绝缘层18和栅电极线20和公共电极线22上。通过刻蚀方式形成贯穿所述绝缘层24和栅极绝缘层18的第一过孔(图未标)，所述第一过孔暴露出部分所述图形化的多晶硅层16。
所述绝缘层24上形成有第二金属层(图未标)，通过图案化所述第二金属层形成所述的漏极电极26和源极电极。所述漏极电极26延伸有延伸部262，所述延伸部262正投影于所述公共电极线22上方。并且所述漏极电极26的延伸部262与所述公共电极线22以及位于所述延伸部262与公共电极线22之间 的绝缘层24形成第二存储电容C2。所述第二存储电容C2与所述第一存储电容C1并联设置。本实施例中，所述第二金属层形成于所述绝缘层24上且通过所述第一过孔与所述图形化的多晶硅层16电连接，即漏极电极26和源极电极通过所述第一过孔与所述图形化的多晶硅层16电连接。所述第一金属层与第二金属层的材料为钼铝合金、铬金属等导电材料。
所述平坦层30形成于所述绝缘层24和图案化后的第二金属层上。所述平坦层30材料为有机膜。并且所述平坦层30采用光罩工艺形成。
本实施例中，所述LTPS阵列基板还包括形成于所述平坦层30上的图形化的底层透明导电层32。所述底层透明导电层32与漏极电极26的延伸部262以及位于所述延伸部262及底层透明导电层32的平坦层30形成第三存储电容C3，所述第三存储电容C3与所述第二存储电容C2及所述第一存储电容C1并联设置。
本实施例中，所述LTPS阵列基板还包括形成于图案化的底层透明导电层32上的保护层34；以及形成于所述保护层34上的顶层透明导电层36，所述顶层透明导电层36与所述底层透明导电层32以及位于所述所述顶层透明导电层36与所述底层透明导电32之间的保护层34形成第四存储电容C4。所述第四存储电容C4与所述第三存储电容C3、第二存储电容C2及第一存储电容C1并联设置。所述顶层透明导电层36与所述底层透明导电层32分别为像素电极层及阵列基板的公共电极层。所述顶层透明导电层36形成于所述保护层34上且通过贯穿所述底层透明导电层32、保护层34及平坦层30的第二过孔与所述漏极电极26电连接。
本发明的LTPS阵列基板通过图形化的多晶硅层16上增加第二部分162，并在第二部分162上方形成漏极电极26的延伸部262，进而所述公共电极线22、与所述公共电极线22相对应的所述多晶硅层16的第二部分162以及夹持在形成所述公共电极线22与所述多晶硅层16的第二部分162之间的栅极绝缘层18构成第一存储电容C1，所述漏极电极26的延伸部262与所述公共电极线22以及位于所述延伸部262与公共电极线22之间的绝缘层24形成第二存储电容C2；第一存储电容C1与第二存储电容C2并联设置，同时，所述LTPS阵列基板还设有所述第四存储电容C4与所述第三存储电容C3与所述第二存储 电容C2及第一存储电容C1并联，在不降低开口率的情况下，增加存储电容，以满足阵列基板电量饱和后的电容需求。
请参阅图2，在本发明的其他实施方式中，位于所述漏极电极26的延伸部262上的平坦层30的厚度小于所述平坦层30其它位置的厚度，如此可以减小所述底层透明导电层32与漏极电极26的延伸部262之间的距离，进而增大所述第三存储电容C3。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种LTPS阵列基板，其包括多个低温多晶硅薄膜晶体管，其中，所述每一低温多晶硅薄膜晶体管包括一个基板；
    形成于所述基板上的图形化的遮光层；
    形成于所述基板和所述图形化的遮光层上的缓冲层；
    形成于所述缓冲层上的图像化的多晶硅层，其中，图像化的多晶硅层包括正投影于遮光层的第一部分和远离所述遮光层延伸的第二部分；
    形成于所述图形化的多晶硅层和所述缓冲层上的栅极绝缘层；
    形成于所述栅极绝缘层上的第一金属层，图形化所述第一金属层形成栅电极线和公共电极线，所述公共电极线、与所述公共电极线相对应的所述多晶硅层的第二部分以及夹持在形成所述公共电极线与所述第二部分之间的栅极绝缘层构成第一存储电容；
    形成于所述栅极绝缘层和栅电极线和公共电极线的绝缘层；
    形成于所述绝缘层上的第二金属层，图案化所述第二金属层形成漏极电极和源极电极，所述漏极电极延伸有延伸部，所述延伸部正投影于所述公共电极线，并且所述漏极电极的延伸部与所述公共电极线以及位于所述延伸部与公共电极线之间的绝缘层形成第二存储电容；所述第二存储电容与所述第一存储电容并联设置，以及
    形成于所述绝缘层和图案化后的第二金属层上的平坦层。
  2. 如权利要求1所述的一种LTPS阵列基板，其中，所述LTPS阵列基板还包括形成于所述平坦层上的图形化的底层透明导电层，所述底层透明导电层与漏极电极的延伸部以及位于所述延伸部及底层透明导电层的平坦层形成第三存储电容，所述第三存储电容与所述第二存储电容及所述第一存储电容并联设置。
  3. 如权利要求2所述的一种LTPS阵列基板，其中，所述LTPS阵列基板还包括形成于图案化的底层透明导电层上的保护层；以及形成于所述保护层上的顶层透明导电层，所述顶层透明导电层与所述底层透明导电层以及位于所述所述顶层透明导电层与所述底层透明导电之间的保护层形成第四存储电容，所 述第四存储电容与所述第三存储电容、第二存储电容及第一存储电容并联设置。
  4. 如权利要求1所述的一种LTPS阵列基板，其中，所述第二金属层形成于所述绝缘层上且通过过孔与所述多晶硅层电连接。
  5. 如权利要求1所述的一种LTPS阵列基板，其中，所述顶层透明导电层形成于所述保护层上且通过过孔与所述漏极电极电连接。
  6. 如权利要求1所述的一种LTPS阵列基板，其中，位于所述漏极电极的延伸部上的平坦层的厚度小于所述平坦层其它位置的厚度。
  7. 如权利要求1所述的一种LTPS阵列基板，其中，所述栅极绝缘层采用氧化硅、氮化硅与氮氧化硅中的一种制成。
  8. 如权利要求1所述的一种LTPS阵列基板，其中，所述第一金属层与第二金属层的材料为钼铝合金、铬金属等导电材料。
  9. 如权利要求1所述的一种LTPS阵列基板，其中，所述平坦层材料为有机膜。
  10. 如权利要求1所述的一种LTPS阵列基板，其中，所述平坦层采用光罩工艺形成。
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