WO2016090681A1 - 像素结构、阵列基板及显示装置 - Google Patents

像素结构、阵列基板及显示装置 Download PDF

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WO2016090681A1
WO2016090681A1 PCT/CN2014/094882 CN2014094882W WO2016090681A1 WO 2016090681 A1 WO2016090681 A1 WO 2016090681A1 CN 2014094882 W CN2014094882 W CN 2014094882W WO 2016090681 A1 WO2016090681 A1 WO 2016090681A1
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pixel electrode
region
signal line
sub
pixel
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French (fr)
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高冬子
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a pixel structure, an array substrate having the pixel structure, and a display device having the array substrate.
  • FIG. 1 is a schematic view showing a pixel structure of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) in the prior art, in order to clearly show a pixel structure, pixel electrodes are not shown in the figure (including Main pixel electrode and sub-pixel electrode).
  • Fig. 2 shows a schematic diagram of a pixel structure with pixel electrodes in the prior art.
  • the pixel structure includes a main pixel thin film transistor 8, a sub-pixel thin film transistor 9, an adjustment thin film transistor 10, first and second signal lines 31 and 32, a main pixel electrode 5, and a sub-pixel electrode 11.
  • Each component of the pixel structure is disposed on the substrate 7. Specifically, referring to the broken lines for demarcation in FIGS.
  • the entire area of the substrate 7 can be divided into a first area 71, a second area 72, and a third area 73 which are sequentially arranged from top to bottom.
  • the main pixel thin film transistor 8, the sub-pixel thin film transistor 9 and the adjustment thin film transistor 10 are located in the first region 71, the main pixel electrode 5 is located in the second region 72, and the sub-pixel electrode 11 is located in the third region 73.
  • the first signal line 31 and the second signal line 32 belong to the metal line (signal line) in the signal line metal layer 3.
  • the components of the pixel structure are overlapped layer by layer.
  • FIG. 3 a cross-sectional view of the pixel structure shown in FIG. 2 in the second region 72 is shown.
  • the hierarchical structure of the pixel structure in the second region 72 is: a gate line metal layer 1, a first insulating layer 2, a signal line metal layer 3, a second insulating layer 4, and a main pixel electrode 5 in order from bottom to top.
  • the first insulating layer 2 and the second insulating layer 4 are both silicon nitride (SiNx) insulating protective layers.
  • the main pixel thin film transistor 8 is connected to the main pixel electrode 5 located in the second region 72 through the first signal line 31, and the sub-pixel thin film transistor 9 is connected to the sub-pixel electrode 11 located in the third region 73 through the first signal line 31.
  • the adjustment thin film transistor 10 is electrically connected to the sub-pixel thin film transistor 9 transistor for adjusting the voltage output from the sub-pixel thin film transistor 9 to the sub-pixel electrode 11, so that the voltage received by the main pixel electrode 5 and the voltage received by the sub-pixel electrode 11 Differently, the deflection angles of the liquid crystals disposed in the second region 72 and the third region 73 are different, and this design is called a wide viewing angle technique.
  • the second signal line 32 drawn from the sub-pixel thin film transistor 9 needs to penetrate the entire second region 72 to be adjacent to the sub-pixel electrode. 11 electrical connection.
  • a disadvantage of such a structure is that, referring to FIG. 4, if the signal metal layer 3 where the second signal line 32 is located is deposited with fine solid particles 6 (especially during chemical vapor deposition (CVD) film formation, it cannot be cleaned.
  • the removed minute solid particles fall at a position where the second signal line 32 overlaps the main pixel electrode 5, the second signal line 32 is lifted up by the solid particles 6, and the second insulating layer 4 deposited later cannot cover the topped up
  • the second signal line 32 causes the second signal line 32 to be jacked to be electrically connected to the main pixel electrode 5. This means that the main pixel electrode 5 and the sub-pixel electrode 11 are short-circuited, so that the above-described wide viewing angle technique cannot be realized.
  • the technical problem to be solved by the present invention is that the pixel structure shown in FIG. 1 has a defect of being resistant to poor solid particles, that is, if a small solid particle falls on the second signal before the metal layer of the signal line where the second signal line is deposited Where the line overlaps with the main pixel electrode, the second signal line is lifted up by the solid particles, and the second insulating layer deposited later cannot cover the second signal line that is jacked up, thereby causing the second signal line to be jacked up Electrically connected to the main pixel electrode.
  • the present invention provides a pixel structure, an array substrate, and a display device.
  • a pixel structure capable of resisting solid particles including a main pixel thin film transistor, a sub-pixel thin film transistor, a main pixel electrode, a sub-pixel electrode, a first signal line, and a second Signal line
  • the main pixel thin film transistor is electrically connected to the main pixel electrode through a first signal line;
  • the sub-pixel thin film transistor is electrically connected to the sub-pixel electrode through a second signal line;
  • the main pixel electrode is located on an upper layer of the second signal line, and an opening is disposed on the main pixel electrode, the opening covering a region where the main pixel electrode overlaps with the second signal line.
  • a boundary of the opening coincides with a boundary of a region where the main pixel electrode and the second signal line overlap.
  • the pixel structure is disposed on a substrate, and the substrate includes a first region sequentially arranged from top to bottom, Second area and third area;
  • the main pixel thin film transistor and the sub-pixel thin film transistor are both disposed in the first region;
  • the main pixel electrode is disposed in the second region
  • the sub-pixel electrode is disposed in the third region, and the second signal line is electrically connected to the sub-pixel electrode through the second region.
  • the main pixel electrode and the sub-pixel electrode are each made of indium tin oxide.
  • an array substrate includes a substrate and a plurality of pixel structures disposed on the substrate, the pixel structure including a main pixel thin film transistor, a sub-pixel thin film transistor, a main pixel electrode, a sub-pixel electrode, a first signal line, and a second signal line;
  • the main pixel thin film transistor is electrically connected to the main pixel electrode through a first signal line;
  • the sub-pixel thin film transistor is electrically connected to the sub-pixel electrode through a second signal line;
  • the main pixel electrode is located on an upper layer of the second signal line, and an opening is disposed on the main pixel electrode, the opening covering a region where the main pixel electrode overlaps with the second signal line.
  • a boundary of the opening coincides with a boundary of a region where the main pixel electrode and the second signal line overlap.
  • the pixel structure is disposed on a substrate, and the substrate includes a first region, a second region, and a third region sequentially arranged from top to bottom;
  • the main pixel thin film transistor and the sub-pixel thin film transistor are both disposed in the first region;
  • the main pixel electrode is disposed in the second region
  • the sub-pixel electrode is disposed in the third region, and the second signal line is electrically connected to the sub-pixel electrode through the second region.
  • the main pixel electrode and the sub-pixel electrode are each made of indium tin oxide.
  • the pixel structure is arranged according to a preset rule.
  • a display device having the above array substrate is also provided.
  • an opening is formed in the main pixel electrode, and the opening covers a portion where the main pixel electrode overlaps with the second signal line, so that even if the second signal line is lifted by the lower layer of solid particles, the jacked up Two signal lines also It does not contact with the main pixel electrode, thereby effectively avoiding the electrical connection between the second signal line and the main pixel electrode, improving the ability of the pixel structure to resist solid particles, and ensuring the wide viewing angle function of the display device.
  • FIG. 1 is a schematic view showing a pixel structure in which a pixel electrode is removed in the prior art
  • FIG. 2 is a schematic view showing a pixel structure with a pixel electrode in the prior art
  • Figure 3 is a cross-sectional view showing the pixel structure shown in Figure 2 in a second region
  • Figure 4 is a schematic cross-sectional view showing the pixel structure in the second region in the case where solid particles are introduced;
  • FIG. 5 is a schematic diagram showing a pixel structure of an embodiment of the present invention.
  • Figure 6 is a cross-sectional view showing the pixel structure shown in Figure 5 in a second region
  • Figure 7 shows a schematic cross-sectional view of the pixel structure in the second region with the introduction of solid particles.
  • the technical problem to be solved by the present invention is that the pixel structure shown in FIG. 1 has a defect of being resistant to poor solid particles, that is, if a small solid particle falls on the second signal before the metal layer of the signal line where the second signal line is deposited Where the line overlaps with the main pixel electrode, the second signal line is lifted up by the solid particles, and the second insulating layer deposited later cannot cover the second signal line that is jacked up, thereby causing the second signal line to be jacked up Electrically connected to the main pixel electrode.
  • the present invention provides a pixel structure that is resistant to solid particles.
  • the pixel structure includes a main pixel thin film transistor 8, a sub-pixel thin film transistor 9, a main pixel electrode 5, a sub-pixel electrode 11, a first signal line 31, and a first
  • the second signal line 32 and the thin film transistor 10 for adjusting the output voltage of the source of the sub-pixel thin film transistor 9 are provided.
  • the main pixel thin film transistor 8, the sub-pixel thin film transistor 9 and the adjustment thin film transistor 10 are both disposed in the first region 71 of the substrate 7, and the main pixel electrode 5 is disposed in the second region 72 of the substrate 7, the sub-pixel electrode 11 It is disposed in the third region 73 of the substrate 7.
  • the main pixel thin film transistor 8 is electrically connected to the main pixel electrode 5 through the first signal line 31, and the sub-pixel thin film transistor 9 is electrically connected to the sub-pixel electrode 11 via the second signal line 32.
  • the sub-pixel thin film transistor 9 and the sub-pixel electrode 11 are disposed in the first region 71 and the third region 73 of the substrate 7, respectively, the second signal line 32 drawn from the source of the sub-pixel thin film transistor 9 needs to penetrate through the substrate 7
  • the second region 72 is electrically connected to the sub-pixel electrode 11.
  • the hierarchical structure of the pixel structure in the second region 72 is from bottom to top.
  • the gate line metal layer 1, the first insulating layer 2, the signal line metal layer 3, the second insulating layer 4, and the main pixel electrode 5 are sequentially used.
  • the hierarchical structure of the pixel structure in the third region 73 is: a gate line metal layer 1, a first insulating layer 2, a signal line metal layer 3, a second insulating layer 4, and a sub-pixel electrode 11 in order from bottom to top.
  • the first signal line 31 and the second signal line 32 belong to the metal line (signal line) in the signal line metal layer 3.
  • an opening 51 is provided on the main pixel electrode 5, and the opening 51 is covered. A region where the main pixel electrode 5 overlaps with the second signal line 32. Therefore, referring to FIG. 7, even if the second signal line 32 is lifted up by the solid particles 6, the second signal line 32 that is pushed up does not cross the main pixel electrode 5 after passing through the second insulating layer 4 due to the presence of the opening 51. The contact is made, thereby effectively avoiding the electrical connection between the second signal line 32 and the main pixel electrode 5, thereby ensuring the wide viewing angle function of the display device.
  • the processing of the opening 51 is the same process as the formation process of the main pixel electrode 5, that is, through the film formation-exposure-development-etch-peel process, while forming the main pixel electrode 5 and being disposed thereon. Opening 51.
  • the openings 51 formed in the main pixel electrode 5 may be one or more.
  • the number of openings 51 depends on the number of overlapping portions of the main pixel electrode 5 and the second signal line 32.
  • the shape of each opening 51 depends on the shape of the portion where the main pixel electrode 5 and the second signal line 32 overlap.
  • the boundary of the opening 51 may be slightly larger than the boundary of the corresponding overlapping portion, but in the specific implementation process, it is also ensured that the provided opening 51 does not affect the basic work of the pixel. can.
  • an opening 51 is formed in the main pixel electrode 5, and the opening 51 covers a portion where the main pixel electrode 5 overlaps with the second signal line 32, so that even if the second signal line 32 is underlying When the solid particles 6 are lifted up, the second signal line 32 that is jacked up does not contact the main pixel electrode 5, thereby effectively preventing the second signal line 32 from being electrically connected to the main pixel electrode 5, thereby improving the pixel structure against solid particles.
  • the ability of 6 ensures the wide viewing angle function of the display device.
  • the opening 51 in order to minimize the possibility that the opening 51 provided on the main pixel electrode 5 affects the basic function of the pixel, the opening 51 is set as small as possible.
  • the boundary of the opening 51 coincides with the boundary of the region where the main pixel electrode 5 and the second signal line 32 overlap (referred to as an overlap region), that is, the length of the opening 51 is equal to the length of the overlap region, and the width D of the opening 51 is equal to the overlap The width of the area.
  • main pixel electrode 5 and the sub-pixel electrode 11 are both made of indium tin oxide, that is, the main pixel electrode 5 and the sub-pixel electrode 11 are both ITO (Indium Tin Oxide) pixel electrodes.
  • an embodiment of the present invention further provides an array substrate 7 including a substrate 7 and a plurality of pixel structures disposed on the substrate 7.
  • the pixel structure includes a main pixel thin film transistor 8 and a sub-pixel thin film transistor 9.
  • the main pixel thin film transistor 8 is electrically connected to the main pixel electrode 5 through the first signal line 31; the sub-pixel thin film transistor 9 is electrically connected to the sub-pixel electrode 11 through the second signal line 32.
  • the main pixel electrode 5 is located on the upper layer of the second signal line 32, and an opening 51 is provided on the main pixel electrode 5, the opening 51 covering a region where the main pixel electrode 5 and the second signal line 32 overlap.
  • the boundary of the opening 51 coincides with the boundary of the region where the main pixel electrode 5 and the second signal line 32 overlap, so that the opening 51 provided on the main pixel electrode 5 affects the basic function of the pixel. Sexuality is reduced to a minimum.
  • the pixel structure is disposed on the substrate 7, and the substrate 7 includes a first region 71, a second region 72, and a third region 73 which are sequentially arranged from top to bottom.
  • the main pixel thin film transistor 8 and the sub-pixel thin film transistor 9 are disposed in the first region 71; the main pixel electrode 5 is disposed in the second region 72; and the sub-pixel electrode 11 is disposed in the third region 73.
  • the second signal line 32 is electrically connected to the sub-pixel electrode 11 through the second region 72.
  • main pixel electrode 5 and the sub-pixel electrode 11 are each made of indium tin oxide.
  • all the pixel structures provided on the substrate 7 are arranged in a predetermined pattern.
  • all pixel structures are arranged in a rectangular array.
  • an embodiment of the present invention further provides a display device having the array substrate 7 described above, for example, a liquid crystal display device.

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Abstract

提供了一种像素结构、阵列基板（7）及显示装置，在像素结构中，主像素薄膜晶体管（8）通过第一信号线（31）与主像素电极（5）电连接；子像素薄膜晶体管（9）通过第二信号线（32）与子像素电极（11）电连接；主像素电极（5）位于第二信号线（32）的上层，在主像素电极（5）上设置开口（51），开口（51）覆盖主像素电极（5）与第二信号线（32）重叠的区域。因此，有效避免了第二信号线（32）与主像素电极（5）电连接，提高了像素结构抵抗固体颗粒（6）的能力，保证了显示装置的广视角功能。

Description

像素结构、阵列基板及显示装置
本申请要求享有2014年12月10日提交的名称为“像素结构、阵列基板及显示装置”的中国专利申请CN201410755558.0的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种像素结构、还涉及一种具有该像素结构的阵列基板、以及具有该阵列基板的显示装置。
背景技术
图1示出了现有技术中TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管-液晶显示器)的像素结构的示意图，为清楚地表示像素结构，该图中未示出像素电极(包括主像素电极和子像素电极)。图2示出了现有技术中带有像素电极的像素结构的示意图。参照图1和图2，像素结构包括主像素薄膜晶体管8、子像素薄膜晶体管9、调节薄膜晶体管10、第一信号线31和第二信号线32、主像素电极5和子像素电极11。像素结构的各组成部分均配置在基板7上。具体地，参照图1和图2中用于划界的虚线所示，基板7的整个区域可分为从上至下顺次排列的第一区域71、第二区域72和第三区域73。其中主像素薄膜晶体管8、子像素薄膜晶体管9和调节薄膜晶体管10位于第一区域71内，主像素电极5位于第二区域72内，子像素电极11位于第三区域73内。第一信号线31和第二信号线32均属于信号线金属层3内的金属线(信号线)。
像素结构的各组成部分是逐层重叠在一起的，参照图3，是图2中所示的像素结构在第二区域72的剖面示意图。像素结构在第二区域72的层次结构为：从下至上依次为栅极线金属层1、第一绝缘层2、信号线金属层3、第二绝缘层4和主像素电极5。第一绝缘层2和第二绝缘层4均为氮化硅(SiNx)绝缘保护层。
主像素薄膜晶体管8通过第一信号线31连接位于第二区域72的主像素电极5，而子像素薄膜晶体管9通过第一信号线31连接位于第三区域73的子像素电极11。调节薄膜晶体管10与子像素薄膜晶体管9晶体管电连接，用于调节子像素薄膜晶体管9向子像素电极11输出的电压，从而使得主像素电极5接收到的电压和子像素电极11接收到的电压 不同，进而使得设置在第二区域72和第三区域73的液晶的偏转角度不同，这种设计称为广视角技术。
由于子像素薄膜晶体管9和子像素电极11分别位于第一区域71和第三区域73内，所以从子像素薄膜晶体管9引出的第二信号线32需要先贯穿整个第二区域72才能与子像素电极11电连接。此种结构的缺陷在于：参照图4，如果在第二信号线32所在的信号线金属层3沉积之前有微小固体颗粒6(特别是化学气相沉积(CVD)成膜过程中产生的无法通过清洗去除的微小固体颗粒)落在第二信号线32与主像素电极5重叠的位置，第二信号线32会被固体颗粒6顶起，而后面沉积的第二绝缘层4不能覆盖被顶起的第二信号线32，从而导致被顶起的第二信号线32会与主像素电极5电连接。这样就意味着主像素电极5和子像素电极11短路，从而无法实现上述广视角技术。
发明内容
本发明所要解决的技术问题是图1中所示的像素结构存在抵抗固体颗粒能力差的缺陷，即：如果在第二信号线所在的信号线金属层沉积之前有微小固体颗粒落在第二信号线与主像素电极重叠的位置，第二信号线会被固体颗粒顶起，而后面沉积的第二绝缘层不能覆盖被顶起的第二信号线，从而导致被顶起的第二信号线会与主像素电极电连接。这样就意味着主像素电极和子像素电极短路，从而无法实现上述广视角技术。
为了解决上述技术问题，本发明提供了一种像素结构、阵列基板及显示装置。
根据本发明的一个方面，提供了一种抵抗固体颗粒能力强的像素结构，所述像素结构包括主像素薄膜晶体管、子像素薄膜晶体管、主像素电极、子像素电极、第一信号线和第二信号线；
所述主像素薄膜晶体管通过第一信号线与主像素电极电连接；所述子像素薄膜晶体管通过第二信号线与所述子像素电极电连接；
所述主像素电极位于所述第二信号线的上层，在所述主像素电极上设置开口，所述开口覆盖所述主像素电极与所述第二信号线重叠的区域。
优选的是，所述开口的边界与所述主像素电极和所述第二信号线重叠的区域的边界重合。
优选的是，所述像素结构设置在基板上，所述基板包括由上至下顺次排布的第一区域、 第二区域和第三区域；
所述主像素薄膜晶体管和子像素薄膜晶体管均设置在所述第一区域内；
所述主像素电极设置在所述第二区域内；
所述子像素电极设置在所述第三区域内，所述第二信号线贯穿所述第二区域与子像素电极电连接。
优选的是，所述主像素电极和所述子像素电极均由氧化铟锡制成。
根据本发明的另一个方面，还提供了一种阵列基板，所述阵列基板包括基板以及设置在所述基板上的多个像素结构，所述像素结构包括主像素薄膜晶体管、子像素薄膜晶体管、主像素电极、子像素电极、第一信号线和第二信号线；
所述主像素薄膜晶体管通过第一信号线与主像素电极电连接；所述子像素薄膜晶体管通过第二信号线与所述子像素电极电连接；
所述主像素电极位于所述第二信号线的上层，在所述主像素电极上设置开口，所述开口覆盖所述主像素电极与所述第二信号线重叠的区域。
优选的是，所述开口的边界与所述主像素电极和所述第二信号线重叠的区域的边界重合。
优选的是，所述像素结构设置在基板上，所述基板包括由上至下顺次排布的第一区域、第二区域和第三区域；
所述主像素薄膜晶体管和子像素薄膜晶体管均设置在所述第一区域内；
所述主像素电极设置在所述第二区域内；
所述子像素电极设置在所述第三区域内，所述第二信号线贯穿所述第二区域与子像素电极电连接。
优选的是，所述主像素电极和所述子像素电极均由氧化铟锡制成。
优选的是，所述像素结构按照预设的规律排布。
根据本发明的另一个方面，还提供了一种具有上述阵列基板的显示装置。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
应用本发明所述的像素结构，在主像素电极上开设开口，开口覆盖主像素电极与第二信号线重叠的部位，使得即使第二信号线被下层的固体颗粒顶起，被顶起的第二信号线也 不会与主像素电极相接触，从而有效避免了第二信号线与主像素电极电连接，提高了像素结构抵抗固体颗粒的能力，保证了显示装置的广视角功能。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了现有技术中去除像素电极的像素结构的示意图；
图2示出了现有技术中带有像素电极的像素结构的示意图；
图3示出了图2中所示的像素结构在第二区域的剖面示意图；
图4示出了在引入固体颗粒的情况下像素结构在第二区域的剖面示意图；
图5示出了本发明实施例像素结构的示意图；
图6示出了图5中所示的像素结构在第二区域的剖面示意图；以及
图7示出了在引入固体颗粒的情况下像素结构在第二区域的剖面示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明所要解决的技术问题是图1中所示的像素结构存在抵抗固体颗粒能力差的缺陷，即：如果在第二信号线所在的信号线金属层沉积之前有微小固体颗粒落在第二信号线与主像素电极重叠的位置，第二信号线会被固体颗粒顶起，而后面沉积的第二绝缘层不能覆盖被顶起的第二信号线，从而导致被顶起的第二信号线会与主像素电极电连接。这样就意味着主像素电极和子像素电极短路，从而无法实现上述广视角技术。为解决上述技术问 题，本发明实施例提供了一种抵抗固体颗粒能力强的像素结构。
图5示出了本发明实施例像素结构的示意图，参照图5，像素结构包括主像素薄膜晶体管8、子像素薄膜晶体管9、主像素电极5、子像素电极11、第一信号线31、第二信号线32以及用于调节子像素薄膜晶体管9的源极的输出电压的调节薄膜晶体管10。
具体地，主像素薄膜晶体管8、子像素薄膜晶体管9和调节薄膜晶体管10均设置在基板7的第一区域71内，主像素电极5设置在基板7的第二区域72内，子像素电极11设置在基板7的第三区域73内。主像素薄膜晶体管8通过第一信号线31与主像素电极5电连接，子像素薄膜晶体管9通过第二信号线32与子像素电极11电连接。由于子像素薄膜晶体管9和子像素电极11分别布设在基板7的第一区域71和第三区域73内，所以从子像素薄膜晶体管9的源极引出的第二信号线32需贯穿基板7的第二区域72与子像素电极11电连接。
像素结构的各组成部分是逐层重叠在一起的，参照图6，是图5中所示的像素结构在第二区域的剖面示意图，像素结构在第二区域72的层次结构为：从下至上依次为栅极线金属层1、第一绝缘层2、信号线金属层3、第二绝缘层4和主像素电极5。类似地，像素结构在第三区域73的层次结构为：从下至上依次为栅极线金属层1、第一绝缘层2、信号线金属层3、第二绝缘层4和子像素电极11。其中第一信号线31和第二信号线32均属于信号线金属层3内的金属线(信号线)。
为避免出现图4中所示的由于固体颗粒6的原因，信号线金属层3的第二信号线32与主像素电极5电连接的现象，在主像素电极5上设置开口51，开口51覆盖主像素电极5与第二信号线32重叠的区域。从而，参照图7，即使第二信号线32被固体颗粒6向上顶起，由于开口51的存在，被顶起的第二信号线32贯穿第二绝缘层4后也不会与主像素电极5相接触，从而有效避免了第二信号线32与主像素电极5电连接，保证了显示装置的广视角功能。
这里，需要指出的是，开口51的加工过程与主像素电极5的形成过程为同一过程，即经过成膜-曝光-显影-蚀刻-剥离制程，同时形成主像素电极5以及设置在其上的开口51。
还需指出的是，在主像素电极5上开设的开口51可以为一个或者多个。开口51的数量取决于主像素电极5与第二信号线32重叠部位的数量。另外，各个开口51的形状取决于主像素电极5与第二信号线32重叠部位的形状。这里，开口51的边界可略大于相对应的重叠部位的边界，但在具体实施过程中还要保证设置的开口51不要影响像素的基本功 能。
综上，应用本实施例所述的像素结构，在主像素电极5上开设开口51，开口51覆盖主像素电极5与第二信号线32重叠的部位，使得即使第二信号线32被下层的固体颗粒6顶起，被顶起的第二信号线32也不会与主像素电极5相接触，从而有效避免了第二信号线32与主像素电极5电连接，提高了像素结构抵抗固体颗粒6的能力，保证了显示装置的广视角功能。
在本发明一优选的实施例中，为使主像素电极5上设置的开口51影响像素基本功能的可能性降到最低，尽量把开口51设置得最小。具体地，开口51的边界与主像素电极5和第二信号线32重叠的区域(称为重叠区域)的边界重合，即开口51的长度等于重叠区域的长度，且开口51的宽度D等于重叠区域的宽度。
进一步地，主像素电极5和子像素电极11均由氧化铟锡制成，即主像素电极5和子像素电极11均为ITO(Indium Tin Oxide)像素电极。
相应地，本发明实施例还提供了一种阵列基板7，该阵列基板7包括基板7以及设置在基板7上的多个像素结构，像素结构包括主像素薄膜晶体管8、子像素薄膜晶体管9、主像素电极5、子像素电极11、第一信号线31和第二信号线32。主像素薄膜晶体管8通过第一信号线31与主像素电极5电连接；子像素薄膜晶体管9通过第二信号线32与子像素电极11电连接。主像素电极5位于第二信号线32的上层，在主像素电极5上设置开口51，该开口51覆盖主像素电极5与第二信号线32重叠的区域。
在本发明一优选的实施例中，上述开口51的边界与主像素电极5和第二信号线32重叠的区域的边界重合，以使主像素电极5上设置的开口51影响像素基本功能的可能性降到最低。
进一步地，像素结构设置在基板7上，基板7包括由上至下顺次排布的第一区域71、第二区域72和第三区域73。主像素薄膜晶体管8和子像素薄膜晶体管9设置在第一区域71内；主像素电极5设置在第二区域72内；子像素电极11设置在第三区域73内。第二信号线32贯穿第二区域72与子像素电极11电连接。
进一步地，主像素电极5和子像素电极11均由氧化铟锡制成。
另外，设置在基板7上的所有像素结构按照预设的规律排布。例如，所有像素结构呈矩形阵列排布。
相应地，本发明实施例还提供了一种具有上述阵列基板7的显示装置，例如，液晶显示装置。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种像素结构，其中，包括主像素薄膜晶体管、子像素薄膜晶体管、主像素电极、子像素电极、第一信号线和第二信号线；
    所述主像素薄膜晶体管通过第一信号线与主像素电极电连接；所述子像素薄膜晶体管通过第二信号线与所述子像素电极电连接；
    所述主像素电极位于所述第二信号线的上层，在所述主像素电极上设置开口，所述开口覆盖所述主像素电极与所述第二信号线重叠的区域。
  2. 根据权利要求1所述的像素结构，其中，所述像素结构设置在基板上，所述基板包括由上至下顺次排布的第一区域、第二区域和第三区域；
    所述主像素薄膜晶体管和子像素薄膜晶体管均设置在所述第一区域内；
    所述主像素电极设置在所述第二区域内；
    所述子像素电极设置在所述第三区域内，所述第二信号线贯穿所述第二区域与子像素电极电连接。
  3. 根据权利要求1所述的像素结构，其中，所述主像素电极和所述子像素电极均由氧化铟锡制成。
  4. 根据权利要求1所述的像素结构，其中，所述开口的边界与所述主像素电极和所述第二信号线重叠的区域的边界重合。
  5. 根据权利要求4所述的像素结构，其中，所述像素结构设置在基板上，所述基板包括由上至下顺次排布的第一区域、第二区域和第三区域；
    所述主像素薄膜晶体管和子像素薄膜晶体管均设置在所述第一区域内；
    所述主像素电极设置在所述第二区域内；
    所述子像素电极设置在所述第三区域内，所述第二信号线贯穿所述第二区域与子像素 电极电连接。
  6. 根据权利要求4所述的像素结构，其中，所述主像素电极和所述子像素电极均由氧化铟锡制成。
  7. 一种阵列基板，其中，包括基板以及设置在所述基板上的多个像素结构，所述像素结构包括主像素薄膜晶体管、子像素薄膜晶体管、主像素电极、子像素电极、第一信号线和第二信号线；
    所述主像素薄膜晶体管通过第一信号线与主像素电极电连接；所述子像素薄膜晶体管通过第二信号线与所述子像素电极电连接；
    所述主像素电极位于所述第二信号线的上层，在所述主像素电极上设置开口，所述开口覆盖所述主像素电极与所述第二信号线重叠的区域。
  8. 根据权利要求7所述的阵列基板，其中，所述像素结构设置在基板上，所述基板包括由上至下顺次排布的第一区域、第二区域和第三区域；
    所述主像素薄膜晶体管和子像素薄膜晶体管均设置在所述第一区域内；
    所述主像素电极设置在所述第二区域内；
    所述子像素电极设置在所述第三区域内，所述第二信号线贯穿所述第二区域与子像素电极电连接。
  9. 根据权利要求7所述的阵列基板，其中，所述主像素电极和所述子像素电极均由氧化铟锡制成。
  10. 根据权利要求7所述的阵列基板，其中，所述像素结构按照预设的规律排布。
  11. 根据权利要求7所述的阵列基板，其中，所述开口的边界与所述主像素电极和所述第二信号线重叠的区域的边界重合。
  12. 根据权利要求11所述的阵列基板，其中，所述像素结构设置在基板上，所述基板包括由上至下顺次排布的第一区域、第二区域和第三区域；
    所述主像素薄膜晶体管和子像素薄膜晶体管均设置在所述第一区域内；
    所述主像素电极设置在所述第二区域内；
    所述子像素电极设置在所述第三区域内，所述第二信号线贯穿所述第二区域与子像素电极电连接。
  13. 根据权利要求11所述的阵列基板，其中，所述主像素电极和所述子像素电极均由氧化铟锡制成。
  14. 根据权利要求11所述的阵列基板，其中，所述像素结构按照预设的规律排布。
  15. 一种显示装置，其中，包括阵列基板，所述阵列基板包括基板以及设置在所述基板上的多个像素结构，所述像素结构包括主像素薄膜晶体管、子像素薄膜晶体管、主像素电极、子像素电极、第一信号线和第二信号线；
    所述主像素薄膜晶体管通过第一信号线与主像素电极电连接；所述子像素薄膜晶体管通过第二信号线与所述子像素电极电连接；
    所述主像素电极位于所述第二信号线的上层，在所述主像素电极上设置开口，所述开口覆盖所述主像素电极与所述第二信号线重叠的区域。
  16. 根据权利要求15所述的显示装置，其中，所述开口的边界与所述主像素电极和所述第二信号线重叠的区域的边界重合。
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