WO2016086571A1 - 阵列基板及其制作方法、显示装置 - Google Patents
阵列基板及其制作方法、显示装置 Download PDFInfo
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- WO2016086571A1 WO2016086571A1 PCT/CN2015/076914 CN2015076914W WO2016086571A1 WO 2016086571 A1 WO2016086571 A1 WO 2016086571A1 CN 2015076914 W CN2015076914 W CN 2015076914W WO 2016086571 A1 WO2016086571 A1 WO 2016086571A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
- H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/82—Cathodes
- H10K50/826—Multilayers, e.g. opaque multilayers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
Definitions
- FIG. 4 is a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 7 is a schematic diagram of forming a first electrode on an oxide conductor layer according to an embodiment of the present invention.
- FIG. 8 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention.
- the active matrix OLED display device includes an array substrate 10 and a package substrate 20 which are packaged together, and a plurality of driving thin films arranged in a matrix are arranged on the substrate 11 of the array substrate 10.
- the driving thin film transistor 100 includes a gate electrode 101, a source electrode 103, and a drain electrode 102.
- the drain electrode 102 of the driving thin film transistor 100 is connected to the first electrode 12 to supply an electrical signal to the first electrode 12.
- a light emitting function layer 13 is formed between the second electrode 15 and the first electrode 12, and when the driving thin film transistor 100 supplies an electrical signal to the first electrode 12, and at the same time, the circuit board supplies an electrical signal to the second electrode 15 through the transmission lead. A current is passed between the one electrode 12 and the second electrode 15, and the light-emitting functional layer is excited to emit light for display.
- the first electrode is formed on the upper surface of the organic flat layer, and an oxide conductor layer is formed between the first electrode and the organic flat layer, that is, an oxide conductor layer is further formed between the organic flat layer and the metal or metal alloy electrode. Since the oxide conductor layer has good adhesion to the organic flat layer and the metal or metal alloy electrode, and the thermal expansion coefficient of the oxide conductor layer and the organic flat layer and the first electrode are not much different, the oxide conductor layer is formed in the organic The flat layer is not easy to fall off and is formed in oxidation The metal or metal alloy electrode on the conductor layer is also less likely to fall off.
- the oxide conductor layer has a lattice distortion characteristic, it is advantageous for buffering and releasing the stress of the first electrode and the organic flat layer adjacent thereto. This is because the direct contact of different crystal structures may cause lattice stress to cause a large stress, which may cause contact problems, and the structure may be reduced by a structure in which the structure is in an intermediate state to alleviate the difference in lattice matching. Moreover, this also makes it difficult for the first electrode and the organic flat layer to fall off from the oxide conductor layer.
- an alloy electrode made of aluminum and metal alloy electrode aluminum is taken as an example for detailed description.
- the array substrate 10 includes an organic flat layer 14, and a first electrode 12 formed on the organic flat layer 14.
- the first electrode 12 is an alloy electrode of aluminum or aluminum
- an oxide conductor layer 16 is further formed between the first electrode 12 and the organic flat layer 14.
- the array substrate may further include a passivation layer, a pixel defining layer, and the like.
- the embodiments of the present invention only exemplify structures such as films or layers related to the inventive aspects of the present invention.
- the oxide conductor layer 16 is in direct contact with the organic planar layer 14, and the first electrode 12 is formed on the upper surface of the oxide conductor layer 16.
- an inert metal layer 17 is further formed between the oxide conductor layer 16 and the first electrode 12.
- the material forming the inert metal layer may be any one of molybdenum, titanium, niobium, tantalum or a combination thereof.
- the metal alloy may be an alloy of aluminum bismuth or an alloy of aluminum boron borohydride. The content of aluminum in the alloy of aluminum-boron-nickel accounts for 99.3% of the alloy, the content of boron accounts for 0.2% of the alloy, and the content of nickel accounts for 0.5% of the alloy.
- an alloy electrode such as an active metal such as aluminum or an active metal such as aluminum is easily oxidized, and the display panel is used for a long period of time, the oxygen atoms in the oxide conductor layer partially migrate to oxidize the metal or metal alloy electrode to form an oxide.
- the electric resistance of one electrode becomes large, so an inert metal layer is formed between the oxide conductor layer and the first electrode, and since the inert metal layer has good stability and good adhesion to the oxide conductor layer and the first electrode, Passing an inert metal layer It is advantageous to prevent the problem that the alloy electrode of the active metal or the active metal is oxidized.
- an inert metal layer is formed between the oxide conductor layer and the first electrode, which is equivalent to making the oxide conductor layer, the inert metal layer and the first electrode connected in parallel, which is advantageous for further reducing the resistance of the first electrode and improving the display quality.
- another stable metal may be used between the oxide conductor layer and the first electrode, such as gold, platinum, etc., but it is expensive, and the display panel is expensive.
- the embodiment of the present invention can be oxidized.
- a molybdenum metal layer is used between the object conductor layer and the first electrode.
- the oxide conductor layer may be an indium tin oxide conductor layer (ie, ITO), an indium zinc oxide (IZO) layer, an indium tin zinc oxide (ITZO) layer, or an indium layer.
- ITO indium tin oxide conductor layer
- IZO indium zinc oxide
- ITZO indium tin zinc oxide
- the layer of gallium zinc oxide Indium Gallium Zinc Oxide, IGZO may also be a combined structure of these material layers.
- the active matrix type OLED display panel includes an array substrate and a package substrate.
- a plurality of thin film transistors arranged in a matrix are formed on the array substrate, and a first electrode, an organic light emitting functional layer, and a second electrode formed on the thin film transistor. If the display side of the display panel is a side close to the package substrate, the display panel is a top emission type display panel; the display side of the display panel is a side close to the array substrate, and the display panel is a bottom emission type display panel.
- the array substrate provided by the embodiment of the invention can be applied to an active matrix display panel or a passive matrix display panel.
- the array substrate 10 further includes a thin film transistor 100 under the organic flat layer 14.
- the thin film transistor 100 includes a gate electrode 101, a source electrode 103 and a drain electrode 102, and the organic flat layer 14 is covered.
- the first electrode 12 and the drain 102 are electrically connected
- the display panel is a top emission type display panel
- the second electrode 15 is a transparent conductive electrode.
- the electrical connection of the first electrode to the drain can be achieved by:
- the organic flat layer 14 is formed with a via hole at a position corresponding to the drain 102 of the thin film transistor 100, and the first electrode 12 and the oxide conductor layer 16 pass through the via hole and the thin film transistor 100.
- the drain 102 is electrically connected. That is, the oxide conductor layer is electrically connected to the drain through direct contact with the drain, and the first electrode is in direct contact with the oxide conductor layer and is electrically connected to the drain.
- the organic flat layer 14 and the oxide conductor layer 16 are formed with via holes at positions of the drain electrodes 102 of the corresponding thin film transistors 100, and the first electrodes 12 pass through the via holes and the drain of the thin film transistor 100. 102 is in direct contact with the electrical connection.
- the organic flat layer and the oxide conductor layer are formed with via holes at the drain positions of the corresponding thin film transistors, and the first electrode and the inert metal layer are electrically connected to the drains of the thin film transistors through the via holes. That is, a via hole is formed on the organic flat layer and the oxide conductor layer, and the inert metal layer is electrically connected to the drain of the thin film transistor through the via hole, and the first electrode is in direct contact with the inert metal layer and is electrically connected to the drain.
- An embodiment of the present invention provides a display device, including the array substrate according to any one of the embodiments of the present invention.
- the display device may be a display device such as an OLED display and any product or component having a display function such as a television, a digital camera, a mobile phone, a tablet computer or the like including the display device.
- An embodiment of the present invention provides a method for fabricating an array substrate, as shown in FIG. 4, including:
- Step S102 forming an oxide conductor layer 16 on the organic flat layer 14, as shown in FIG.
- the material forming the oxide conductor layer is any one of indium tin oxide, indium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, or a combination thereof.
- the first electrode may be formed of a metal or a metal alloy.
- the metal is aluminum and the metal alloy is aluminum alloy.
- the aluminum alloy is an alloy of aluminum bismuth or an alloy of aluminum boron borohydride.
- Step S104 forming the light-emitting function layer 13 and the second electrode 15, as shown in FIG.
- the method further includes:
- an inert metal layer 17 is formed on the oxide conductor layer 16, as shown in FIG.
- the material forming the inert metal layer is any one of molybdenum, titanium, niobium, tantalum or a combination thereof.
- the above step 103 may include forming the first electrode 12 on the inert metal layer 17.
- the array substrate after the light-emitting function layer 13 and the second electrode 15 are formed on the first electrode 12 is as shown in FIG.
- the above step 102 includes forming a via at a position corresponding to the drain 102 of the organic flat layer 14, as shown in FIG. 5.
- Forming the via holes on the organic flat layer may be performed after the organic flat layer is formed, or may be formed at the position corresponding to the drain while the organic flat layer is formed.
- the oxide conductor layer 16 formed on the organic flat layer 14 covers the via hole (ie, the drain electrode 102), and the formed first electrode 12 is electrically connected to the drain electrode 102 through the oxide conductor layer 16.
- an inert metal layer 17 is formed on the oxide conductor layer 16, and the inert metal layer 17 covers the region corresponding to the drain electrode 102, and the formed first electrode 12 passes through the oxide conductor layer 16. The inert metal layer 17 is electrically connected to the drain 102.
- the method further includes: forming a via hole in a region of the organic flat layer 14 and the oxide conductor layer 16 corresponding to the drain electrode 102, wherein the first electrode 12 passes the above The holes are electrically connected directly to the drain 102.
- the method further includes: forming a via hole in the organic flat layer 14, the oxide conductor layer 16, and the region of the inert metal layer 17 corresponding to the drain 102.
- the first electrode 12 is directly electrically connected to the drain 102 through the via hole.
- the method before forming the inert metal layer on the oxide conductor layer, the method further includes: forming a via hole at a position where the organic flat layer and the oxide conductor layer correspond to the drain of the thin film transistor, and then the first electrode And an inert metal layer is electrically connected to the drain of the thin film transistor through the via. That is, a via hole is formed on the organic flat layer and the oxide conductor layer, and the inert metal layer is electrically connected to the drain of the thin film transistor through the via hole, and the first electrode is in direct contact with the inert metal layer. Electrically connected to the drain.
Abstract
Description
Claims (18)
- 一种阵列基板,包括:第一电极;第二电极;位于所述第一电极和所述第二电极之间的发光功能层;以及有机平坦层;其中,所述第一电极形成在所述有机平坦层的上面,所述第一电极为金属或金属合金电极;并且所述有机平坦层与所述第一电极之间还形成有氧化物导体层。
- 根据权利要求1所述的阵列基板,其中,在所述氧化物导体层和所述第一电极之间还形成有惰性金属层。
- 根据权利要求2所述的阵列基板,其中,形成所述惰性金属层的材料包括钼、钛、钽、铌中的任意一种或其组合。
- 根据权利要求1-3任一项所述的阵列基板,其中,形成所述氧化物导体层的材料包括铟锡氧化物、铟锌氧化物、铟锡锌氧化物、铟镓锌氧化物中的任意一种或其组合。
- 根据权利要求1-4任一项所述的阵列基板,其中,所述金属包括铝,并且所述金属合金包括铝合金。
- 根据权利要求5所述的阵列基板,其中,所述铝合金包括铝钕的合金或铝硼镍的合金。
- 根据权利要求1或4-6任一项所述的阵列基板,还包括位于所述有机平坦层下方的薄膜晶体管;其中,所述有机平坦层在对应所述薄膜晶体管漏极的位置处形成有过孔,所述第一电极与所述氧化物导体层通过所述过孔与所述薄膜晶体管的漏极电连接;或者,所述有机平坦层和所述氧化物导体层在对应所述薄膜晶体管漏极的位置处形成有过孔,所述第一电极通过位于所述过孔与所述薄膜晶体管的漏极直接接触电连接。
- 根据权利要求2或3所述的阵列基板,还包括位于所述有机平坦层下方的薄膜晶体管;其中所述有机平坦层在对应所述薄膜晶体管漏极的位置处形成有过孔,所述第一电极、所述惰性金属层与所述氧化物导体层通过所述过孔与所述薄膜晶体管的漏极电连接;或者,所述有机平坦层和所述氧化物导体层在对应所述薄膜晶体管漏极的位置处形成有过孔,所述第一电极、所述惰性金属层通过所述过孔与所述薄膜晶体管的漏极电连接;或者,所述有机平坦层、所述氧化物导体层和所述惰性金属层在对应所述薄膜晶体管漏极的位置处形成有过孔,所述第一电极通过所述过孔与所述薄膜晶体管的漏极直接接触电连接。
- 一种显示装置,包括权利要求1-8任一项所述的阵列基板。
- 一种阵列基板的制作方法,包括:形成有机平坦层;在所述有机平坦层上形成氧化物导体层;在所述氧化物导体层上形成第一电极,其中所述第一电极为金属或金属合金电极;以及形成发光功能层以及第二电极。
- 根据权利要求10所述的制作方法,还包括:在所述有机平坦层上形成氧化物导体层之后,且在所述氧化物导体层上形成第一电极之前,在所述氧化物导体层上形成惰性金属层。
- 根据权利要求11所述的制作方法,其中,在所述惰性金属层上形成所述第一电极。
- 根据权利要求10所述的制作方法,还包括:在形成有机平坦层之前,形成薄膜晶体管;所述形成所述有机平坦层包括:在所述有机平坦层对应所述薄膜晶体管漏极的位置处形成过孔,使得所述第一电极与所述氧化物导体层通过所述过孔与所述薄膜晶体管的漏极电连接;或者,在形成第一电极之前,所述方法还包括:在所述有机平坦层、所述氧化物导体层对应所述薄膜晶体管漏极的位置处形成过孔,使得所述第一电极通过位于所述过孔与所述薄膜晶体管的漏极直接接触电连接。
- 根据权利要求11-13任一项所述的制作方法,还包括:在形成有机平坦层之前,形成薄膜晶体管;所述形成所述有机平坦层包括:在有机平坦层对应所述薄膜晶体管漏极的位置处形成过孔,使得所述第一电极、所述惰性金属层与所述氧化物导体层通过所述过孔与所述薄膜晶体管的漏极电连接;或者,所述方法还包括:在所述氧化物导体层上形成惰性金属层之前,在所述有机平坦层和所述氧化物导体层对应所述薄膜晶体管漏极的位置处形成过孔,使得所述第一电极、所述惰性金属层通过所述过孔与所述薄膜晶体管的漏极电连接;或者,所述方法还包括:在形成所述第一电极之前,在所述有机平坦层、所述氧化物导体层和所述惰性金属层对应所述薄膜晶体管漏极的位置处形成过孔,使得所述第一电极通过所述过孔与所述薄膜晶体管的漏极直接接触电连接。
- 根据权利要求11-12和14任一项所述的制作方法,其中,形成所述惰性金属层的材料包括钼、钛、钽、铌中的任意一种或其组合。
- 根据权利要求10-15任一项所述的制作方法,其中,形成所述氧化物导体层的材料包括铟锡氧化物、铟锌氧化物、铟锡锌氧化物、铟镓锌氧化物中的任意一种或其组合。
- 根据权利要求10-16任一项所述的制作方法,其中,所述金属为铝,所述金属合金为铝合金。
- 根据权利要求16所述的制作方法,其中,所述铝合金为铝钕的合金或铝硼镍的合金。
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KR20170036876A (ko) * | 2015-09-18 | 2017-04-03 | 삼성디스플레이 주식회사 | 유기 전계 발광 소자 및 이를 포함하는 표시 장치 |
US10117084B2 (en) | 2016-09-23 | 2018-10-30 | Apple Inc. | Context-dependent allocation of shared resources in a wireless communication interface |
CN115568243B (zh) * | 2022-08-30 | 2023-10-20 | 惠科股份有限公司 | 显示装置、显示面板及其制备方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1717135A (zh) * | 2004-06-18 | 2006-01-04 | 三洋电机株式会社 | 电致发光面板 |
US20080309232A1 (en) * | 2007-06-12 | 2008-12-18 | Casio Computer Co., Ltd. | Display apparatus and method of manufacturing the same |
CN101556991A (zh) * | 2008-01-31 | 2009-10-14 | 三星移动显示器株式会社 | 有机发光二极管显示装置及其制造方法 |
CN103730481A (zh) * | 2012-10-11 | 2014-04-16 | 友达光电股份有限公司 | 有机发光显示器及其制作方法 |
CN104393023A (zh) * | 2014-12-01 | 2015-03-04 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN204271084U (zh) * | 2014-12-01 | 2015-04-15 | 京东方科技集团股份有限公司 | 一种阵列基板及显示装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6210841A (ja) * | 1985-07-05 | 1987-01-19 | Mitsubishi Electric Corp | カラ−陰極線管 |
JPH01165151A (ja) * | 1987-12-22 | 1989-06-29 | Toshiba Components Co Ltd | 半導体整流装置 |
JP2001060495A (ja) * | 1999-08-23 | 2001-03-06 | Tdk Corp | 有機el素子 |
JP3908552B2 (ja) * | 2001-03-29 | 2007-04-25 | Nec液晶テクノロジー株式会社 | 液晶表示装置及びその製造方法 |
US7105200B2 (en) * | 2001-09-10 | 2006-09-12 | Noritake Co., Limited | Method of producing thick-film sheet member |
CN1287639C (zh) * | 2003-07-24 | 2006-11-29 | 复旦大学 | 有机发光器件中的双亲分子缓冲层及其制备方法 |
KR100560792B1 (ko) * | 2004-03-23 | 2006-03-13 | 삼성에스디아이 주식회사 | 전면 발광 구조를 갖는 유기 전계 발광 표시 장치 및 이의제조방법 |
TW200802998A (en) * | 2006-04-11 | 2008-01-01 | Koninkl Philips Electronics Nv | An organic diode and a method for producing the same |
JP2010503166A (ja) * | 2006-09-07 | 2010-01-28 | サン−ゴバン グラス フランス | 有機発光デバイス用基板、基板の使用法およびを製造プロセス、ならびに有機発光デバイス |
KR100787461B1 (ko) * | 2006-11-10 | 2007-12-26 | 삼성에스디아이 주식회사 | 다층 구조의 애노드를 채용한 유기 발광 디스플레이 장치 |
JP5453952B2 (ja) * | 2009-06-23 | 2014-03-26 | ソニー株式会社 | 有機エレクトロルミネッセンス素子およびその製造方法、並びに表示装置およびその製造方法 |
JP4802286B2 (ja) * | 2009-08-28 | 2011-10-26 | 富士フイルム株式会社 | 光電変換素子及び撮像素子 |
JP5662689B2 (ja) * | 2010-02-17 | 2015-02-04 | 株式会社ジャパンディスプレイ | 表示装置およびその製造方法 |
JP5648437B2 (ja) * | 2010-11-15 | 2015-01-07 | セイコーエプソン株式会社 | 電気光学装置および投射型表示装置 |
JP5969216B2 (ja) * | 2011-02-11 | 2016-08-17 | 株式会社半導体エネルギー研究所 | 発光素子、表示装置、照明装置、及びこれらの作製方法 |
JP2015018770A (ja) * | 2013-07-12 | 2015-01-29 | パナソニックIpマネジメント株式会社 | 有機エレクトロルミネッセンス素子及び照明装置 |
KR102059167B1 (ko) * | 2013-07-30 | 2020-02-07 | 엘지디스플레이 주식회사 | 플렉서블 유기전계 발광소자 및 그 제조 방법 |
CN103500752A (zh) * | 2013-09-27 | 2014-01-08 | 京东方科技集团股份有限公司 | 一种oled像素结构和oled显示装置 |
KR102173510B1 (ko) * | 2014-05-20 | 2020-11-04 | 엘지디스플레이 주식회사 | 유기전계발광소자 |
-
2014
- 2014-12-01 CN CN201410720593.9A patent/CN104393023B/zh active Active
-
2015
- 2015-04-17 US US14/893,325 patent/US10381428B2/en active Active
- 2015-04-17 WO PCT/CN2015/076914 patent/WO2016086571A1/zh active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1717135A (zh) * | 2004-06-18 | 2006-01-04 | 三洋电机株式会社 | 电致发光面板 |
US20080309232A1 (en) * | 2007-06-12 | 2008-12-18 | Casio Computer Co., Ltd. | Display apparatus and method of manufacturing the same |
CN101556991A (zh) * | 2008-01-31 | 2009-10-14 | 三星移动显示器株式会社 | 有机发光二极管显示装置及其制造方法 |
CN103730481A (zh) * | 2012-10-11 | 2014-04-16 | 友达光电股份有限公司 | 有机发光显示器及其制作方法 |
CN104393023A (zh) * | 2014-12-01 | 2015-03-04 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN204271084U (zh) * | 2014-12-01 | 2015-04-15 | 京东方科技集团股份有限公司 | 一种阵列基板及显示装置 |
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CN104393023A (zh) | 2015-03-04 |
US20160329395A1 (en) | 2016-11-10 |
US10381428B2 (en) | 2019-08-13 |
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