WO2016086522A1 - 一种阵列基板、显示装置 - Google Patents

一种阵列基板、显示装置 Download PDF

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WO2016086522A1
WO2016086522A1 PCT/CN2015/071058 CN2015071058W WO2016086522A1 WO 2016086522 A1 WO2016086522 A1 WO 2016086522A1 CN 2015071058 W CN2015071058 W CN 2015071058W WO 2016086522 A1 WO2016086522 A1 WO 2016086522A1
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thin film
source
array substrate
sub
film transistor
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PCT/CN2015/071058
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English (en)
French (fr)
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衣志光
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深圳市华星光电技术有限公司
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/139—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent
    • G02F1/1393—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate and a display device.
  • the liquid crystal display Compared with the traditional cathode ray tube (CRT) display, the liquid crystal display has gradually become the mainstream development direction of the display market due to its advantages such as light and ultra-thin, low power consumption, vivid picture and no flicker.
  • the liquid crystal display mainly utilizes the photoelectric effect of the liquid crystal molecules, and controls the deflection of the liquid crystal molecules in the liquid crystal layer by applying a voltage to the liquid crystal layer, thereby controlling the light emitted by the backlight to pass through the liquid crystal layer to achieve selective brightness and darkness, and to achieve the display image. the goal of.
  • liquid crystal displays have color shift problems. Since the liquid crystal display uses liquid crystal to realize display, the effective refractive index of liquid crystal molecules is different under different viewing angles, thereby causing a change in transmitted light intensity, which is manifested by a decrease in light transmission capability at a large viewing angle, a large viewing angle direction and a positive The color of the viewing angle is inconsistent, that is, a normal image is observed under a positive viewing angle but not displayed at a large viewing angle, and a color shift exists.
  • each sub-pixel unit 1 of the VA liquid crystal display is divided into a main region 11 and a slave region 12, and a main film 11 and a slave region 12 are respectively provided with a thin film transistor 2 (TFT).
  • TFT thin film transistor 2
  • the source 21 of the two thin film transistors 2 are connected, and the data signal enters the main region 11 and the slave region 12 via the connected source 31.
  • each sub-pixel unit 1 is further provided with a voltage dividing capacitor 3, which can reduce the potential from the region 12, thereby reducing the slave region. 12 ability to drive liquid crystal molecules.
  • the main region 11 of the prior art and the source 21 of the thin film transistor 2 of the slave region 12 are both arcuate, and the connection points of the two source electrodes 2 are located at the top end of the arc shape.
  • the inventors have found that in the preparation process of the array substrate, the arrangement of the source 21 shown in FIG. 1 tends to cause insufficient exposure of the region between the source 21 and the drain 22, resulting in photoresist. Residual. The residual photoresist causes insufficient etching of the region between the source 21 and the drain 22, thereby causing the source 21 and the drain 22 to be short-circuited, which improves the preparation difficulty of the array substrate and affects the display effect of the liquid crystal display.
  • An object of the present invention is to provide an array substrate and a display device to solve the technical problem that the source and the drain of the TFT in the VA liquid crystal display are easily short-circuited.
  • a first aspect of the present invention provides an array substrate including a plurality of sub-pixel units arranged in an array, each of the sub-pixel units including a main area and a sub-area, each of the main area and the sub-area Provided with a thin film transistor, wherein
  • the sources of the two thin film transistors are connected and the connected sources are linear, and the drains are insulated from each other.
  • the drain of the thin film transistor is arc-shaped, and the drains of the two thin film transistors are mirror-symmetrical and are respectively disposed at both ends of the source.
  • the drain of the thin film transistor is linear, and the drains of the two thin film transistors are respectively disposed on both sides of the source, parallel to the source.
  • the drain of the thin film transistor is linear, and the drains of the two thin film transistors are arranged side by side on the same side of the source.
  • the array substrate further includes vertical and horizontal staggered gate lines and data lines, and two adjacent gate lines and two adjacent data lines define one sub-pixel unit.
  • the thin film transistor further includes a gate electrode, and the gate electrode and the gate line are integrally formed.
  • the array substrate further includes a metal trace connecting the data line and the source, and the metal trace is located in a corresponding area of the gate line and the gate.
  • the array substrate further includes a metal trace connecting the data line and the source, and the metal trace is located in a corresponding area of the gate line.
  • an area ratio of the slave region to the main region is 6:4 or 5:5 or 4:6.
  • the present invention provides the following advantages:
  • the embodiment of the present invention provides an array substrate, wherein the sub-pixel unit in the array substrate includes a main area and a sub-area, and a main film and a sub-area are each provided with a thin film transistor.
  • the sources of the two thin film transistors are connected and the connected sources are linear, and the drains are insulated from each other.
  • the structure of the two thin film transistors on the array substrate provided by the embodiment of the invention is relatively dispersed, so that the areas of the source and the drain are approximately equal, which can effectively prevent the phenomenon of photoresist residue occurring during the patterning process. Further, the poor result of preventing the short circuit between the source and the drain caused by the residual photoresist reduces the difficulty in preparation of the array substrate and ensures the display effect of the display device.
  • a second aspect of the present invention provides a display device including the above array substrate.
  • FIG. 1 is a schematic structural view of a sub-pixel unit of the prior art
  • FIG. 2 is a schematic view showing the shape of a semi-transmissive mask suitable for the thin film transistor of FIG. 1;
  • Figure 3 is a schematic view showing the development effect of the semi-transmissive mask of Figure 2 after exposure;
  • Figure 4 is a cross-sectional view taken along line A-A of Figure 3;
  • 5 to 7 are schematic diagrams of the preparation process based on FIG. 4;
  • FIGS. 8 to 11 are schematic views showing the structure of a thin film transistor provided in an embodiment of the present invention.
  • an array substrate including a plurality of sub-pixel units 1 arranged in an array, each sub-pixel unit 1 including a main area 11 and a sub-area 12, and a main thin film transistor is disposed in each of the main area 11 and the sub-area 12. 2.
  • the source 21 of the two thin film transistors 2 are connected and the connected source 21 is linear, and the drains 22 are insulated from each other.
  • the current array substrate is usually prepared by a four-layer patterning process, wherein the patterns of the active layer 23, the source 21 and the drain 22 of the thin film transistor 2 are formed in the same patterning process, and the It is a semi-transmissive mask 4.
  • the pattern of the active layer 23, the source 21 and the drain 22 of the array substrate in the prior art can be made using a semi-transmissive mask 4 as shown in FIG. 2, which includes a full light transmission.
  • an amorphous silicon layer 231, an N-type doped amorphous silicon layer 232, and a metal layer 6 are sequentially formed over the gate insulating layer 25. Then, a photoresist 7 is formed by coating on the metal layer 6.
  • the above structure is exposed by the semi-transmissive mask 4 shown in FIG. 2.
  • the semi-transmissive mask 4 is placed above the structure to be exposed, and light is emitted from the semi-transmissive mask 4 toward the structure to be exposed, and the shape of the semi-transparent mask 4 is projected onto the structure to be exposed. .
  • the exposed structure to be exposed after exposure is subjected to development processing.
  • the photoresist 7 corresponding to the fully transparent region of the semi-transmissive mask 4 is subjected to a large amount of illumination, and is completely removed after development processing to form a completely removed region 71 of the photoresist 7; the semi-transmissive region 41
  • the corresponding photoresist 7 is partially illuminated, and partially removed after the development process to form a partial retention region 72 having a small thickness; the photoresist 7 corresponding to the opaque region 42 is not exposed to light, and there is no change after development processing.
  • a fully preserved area 73 of greater thickness is provided.
  • the light path of part of the light is affected by the opaque region 42 of the semi-transparent mask 4, and will be transmitted through the semi-transmissive mask 4 in a diffracted manner to illuminate the structure to be exposed, and the diffracted light is on the structure to be exposed.
  • the illuminated area primarily corresponds to the partially retained area 72 formed. Therefore, after the exposure process, since the area of the B region in the opaque region 42 in FIG. 2 is large, the light passing through the C region between the B region and the drain 22 is relatively small, less than semi-transparent. Other areas of area 41. As shown in FIG. 3 and FIG. 4, it is understood that the C region transmits less light than the other semi-transmissive regions 41.
  • the thickness of the residual photoresist which will result in the C1 region in the partial retention region 72 corresponding to the C region after the development process is thicker relative to the remainder of the partial retention region, which is about 0.08 micrometers.
  • FIG. 5 it is a schematic structural view after the first wet etching and the first dry etching of the structure shown in FIG.
  • FIG. 6 after the first ashing process is performed on the structure shown in FIG. 5, it is highly likely that a portion of the photoresist 7 remains in the C1 region of the portion of the remaining region 72.
  • the metal layer 6 between the source 21 and the drain 22 which causes the residual photoresist to be covered is not removed, and finally a structure as shown in FIG. 7 is formed, at which time the source 21 and the drain 22 of the thin film transistor 2 are short-circuited. .
  • the source 21 and the drain 22 of the thin film transistor 2 are short-circuited, so that the thin film transistor 2 is not controlled by the driving signal applied from the gate 24, and receives the data signal from the data line 8 at all times, resulting in the corresponding sub-pixel unit of the thin film transistor 2.
  • the display of 1 is abnormal, usually a bright spot. What is more serious is that the phenomenon that the source 21 and the drain 22 of the thin film transistor 2 are short-circuited by the exposure process is usually in the form of a sheet, that is, a bright spot composed of bright spots of a sheet appears on the liquid crystal display panel, and the bright spot is not Easy to repair. Therefore, the pattern of the source 21 of the two thin film transistors 2 in the prior art is liable to cause the display effect of the liquid crystal display panel to be unsatisfactory, so that the production cost of the array substrate of the prior art is high.
  • the embodiment of the present invention adopts A pattern that is significantly different from the source stage 21 and the drain 22 of the thin film transistor 2 shown in FIG. 1 is as follows:
  • the source 21 of the two thin film transistors 2 are connected and the connected source 21 is linear, and the drain 22 of the thin film transistor 2 is arc-shaped, and the drains of the two thin film transistors 2 are provided. 22 is mirror symmetrical and is disposed outside the ends of the source 1 respectively.
  • the source 21 of the two thin film transistors 2 are connected, and the patterns of the source 21 and the drain 22 on the thin film transistor 2 are similar in size, unlike the area shown in FIG. section.
  • the intensity of light transmitted through the semi-transmissive region 41 is almost equal.
  • the thickness of the photoresist 7 of the partial retention region 72 formed after development is made substantially equal. After the first ashing process is performed, the photoresist 7 corresponding to the semi-transmissive region 41 can be substantially completely removed, and there is no phenomenon in which the photoresist 7 remains as described above. The subsequent second etching process can proceed smoothly, completely separating the source 21 and the drain 22.
  • the array substrate further includes the gate lines 9 and the data lines 8 which are criss-crossed, two adjacent gate lines 9 and two adjacent data lines 8 divide one sub-pixel unit 1. Then, in order to ensure that the active layer 23 of the thin film transistor 2 can be driven by the gate driving signal loaded on the gate 24, the source 21 and the drain 22 are turned on. As shown in FIG. 8, the two thin film transistors 2 are entirely placed over the gate electrode 24, and the gate electrode 24 is integrally formed with the gate line 9.
  • the metal substrate 10 is further disposed on the array substrate.
  • the metal trace 10 includes two portions perpendicular to each other and two portions connecting the data line 8 and the source 21, respectively.
  • a portion connecting the data lines 8 is perpendicular to the data lines 8, parallel to the gate lines 9, and a portion connecting the source electrodes 21 is parallel to the data lines 8 and perpendicular to the gate lines 9.
  • the metal trace 10 is partially outside the corresponding area of the gate line 9 and the gate electrode 21, resulting in a slight decrease in the aperture ratio of the sub-pixel unit 1.
  • the metal trace 10 and the two thin film transistors 2 are narrowed as a whole in the y direction until the metal trace 10 and the two thin film transistors 2 can be located in the corresponding regions of the gate 24 and the gate line 9. Inside. Obviously, the metal trace 10 shown in FIG. 9 does not affect the aperture ratio of the sub-pixel unit 1.
  • the channel length of the thin film transistor 2 is reduced from the original 4.5 micron to 3 micrometers. Accordingly, the resolution of the transflective mask 4 also needs to be reduced, typically 3 microns or less.
  • the decrease in the channel width may result in the occurrence of a channel defect, for example, may cause the partial sub-pixel unit 1 to form a bright spot.
  • these bright spots can be repaired by dark doting or the like, that is, the gate line 9 or the gate electrode 24 is electrically connected to the pixel electrode by a soldering process, and the pixel voltage is forced to rotate the liquid crystal so that the sub-pixel unit 1 is always darkened. status.
  • the embodiment of the present invention also provides another structure which is significantly different from the thin film transistor 2 shown in FIGS. 8 and 9.
  • the drain 22 of the thin film transistor 2 is a linear type, and two thin film transistors are used.
  • the drain electrodes 22 of the two are disposed on both sides of the source 21, respectively, in parallel with the source 21.
  • the metal trace 10 and the source 21 are on the same straight line and are located in the corresponding regions of the gate line 24.
  • the width of the conductive channel of the active layer 23 can be 4.5 micrometers in accordance with the prior art or the structure shown in FIG. 8, which can prevent some disadvantages caused by a decrease in the channel width.
  • the metal trace 10 and the two thin film transistors 2 are located in corresponding regions of the gate line 9, which can ensure the aperture ratio of the sub-pixel unit 1, thereby ensuring the display effect of the display device.
  • the structure shown in Fig. 10 can be simply modified to obtain the structure shown in Fig. 11.
  • the drain 22 of the thin film transistor 2 is linear, and the drains 22 of the two thin film transistors 2 are arranged side by side on the same side of the source 21.
  • the structure shown in FIG. 11 is more compact than the structure shown in FIG. 10, which is advantageous in reducing the area of the gate electrode 24 and increasing the aperture ratio of the sub-pixel unit 1.
  • the metal trace 10 the source 21 and the drain 22 in the same plane should have a pitch of at least 3 micrometers to ensure normal operation of the sub-pixel unit 1.
  • the area ratio of the main area and the sub-area of the sub-pixel unit may be a common ratio such as 6:4 or 5:5 or 4:6, and may also be selected and set according to actual conditions. The embodiment does not limit this.
  • an embodiment of the present invention provides an array substrate, wherein the sub-pixel unit in the array substrate includes a main area and a sub-area, and the main area and the sub-area are each provided with a thin film transistor.
  • the sources of the two thin film transistors are connected and the connected sources are linear, and the drains are insulated from each other.
  • the structure of the two thin film transistors on the array substrate provided by the embodiment of the invention is relatively dispersed, so that the areas of the source and the drain are approximately equal, which can effectively prevent the phenomenon of photoresist residue occurring during the patterning process. Further, the poor result of preventing the short circuit between the source and the drain caused by the residual photoresist reduces the difficulty in preparation of the array substrate and ensures the display effect of the display device.
  • a second aspect of the present disclosure provides a display device, which includes the above array substrate, and the display device can be a display device such as a liquid crystal television, a liquid crystal display, a mobile phone, or a tablet computer.

Abstract

一种显示装置，属于显示技术领域，解决了VA液晶显示器中的TFT的源极和漏极易短路的技术问题。阵列基板包括呈阵列式设置的若干子像素单元（1），每个子像素单元（1）包括主区域（11）和从区域（12），主区域（11）和从区域（12）各设置一个薄膜晶体管（2），其中，两个薄膜晶体管（2）的源极（21）相连且相连的源极（21）呈直线型，漏极（22）相互绝缘分开。

Description

一种阵列基板、显示装置
本申请要求享有2014年12月3日提交的名称为“一种阵列基板、显示装置”的中国专利申请CN201410725096.8的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板、显示装置。
背景技术
相较于传统的阴极射线管(Cathode Ray Tube，简称CRT)显示器，液晶显示器因具有轻巧超薄、低功耗、画面逼真无闪烁等诸多优点，已逐渐成为显示市场的主流发展方向。液晶显示器主要是利用液晶分子的光电效应，通过对液晶层施加电压以控制液晶层内液晶分子的偏转，从而控制背光源发出的光经过液晶层的多寡实现有选择性的明暗效果，达到显示图像的目的。
然而，液晶显示器却存在色偏问题。由于液晶显示器是利用液晶实现显示，在不同的视角下，液晶分子的有效折射率也不相同，由此会引起透射光强的变化，具体表现为大视角下透光能力降低，大视角方向和正视角方向所表现的颜色不一致，即在正视角下观察到正常的图像但在大视角下却显示不正常，存在色偏。
综上，目前广大厂商推出了垂直配向(Vertical Alignment，简称VA)液晶显示器，主区域和从区域对应的液晶分子的偏转角度不同，可解决色偏问题。具体的，如图1所示，VA液晶显示器的每一子像素单元1分为主区域11和从区域12，主区域11和从区域12各设置有一个薄膜晶体管2(Thin Film Transistor，简称TFT)，两个薄膜晶体管2的源极21相连，数据信号经由相连的源极31，同时进入主区域11和从区域12。为了使得主区域11和从区域12对应的液晶分子的偏转角度不同，每一子像素单元1内还设置有分压电容3，该分压电容3可降低从区域12的电位，从而降低从区域12驱动液晶分子的能力。
如图1所示，现有技术中的主区域11和从区域12的薄膜晶体管2源极21均为弧线形，两源极2的连接点位于弧线形的顶端。发明人发现，在阵列基板的制备过程中，图1所示的源极21设置方式容易导致源极21和漏极22之间的区域曝光不充分，导致光刻胶 残留。残留的光刻胶导致源极21和漏极22之间的区域刻蚀不充分，进而导致源极21和漏极22短路，提高了阵列基板的制备难度，同时影响液晶显示器的显示效果。
发明内容
本发明的目的在于提供一种阵列基板、显示装置，以解决VA液晶显示器中的TFT的源极和漏极易短路的技术问题。
本发明第一方面提供了一种阵列基板，该阵列基板包括呈阵列式设置的若干个子像素单元，每个所述子像素单元包括主区域和从区域，所述主区域和所述从区域各设置有一个薄膜晶体管，其中，
两个薄膜晶体管的源极相连且相连的源极呈直线型，漏极相互绝缘分开。
进一步的，薄膜晶体管的漏极为弧线形，两个薄膜晶体管的漏极呈镜像对称、分别设置在源极的两端外。
进一步的，薄膜晶体管的漏极为直线型，两个薄膜晶体管的漏极分别设置在源极的两侧，与源极平行。
进一步的，薄膜晶体管的漏极为直线型，两个薄膜晶体管的漏极并排设置在源极的同一侧。
进一步的，所述的阵列基板还包括纵横交错的栅线和数据线，两相邻的栅线和两相邻的数据线划分出一个子像素单元。
进一步的，薄膜晶体管还包括栅极，栅极与栅线一体成型。
进一步的，所述的阵列基板还包括连接数据线和源极的金属走线，金属走线位于栅线和栅极的对应区域内。
进一步的，所述的阵列基板还包括连接数据线和源极的金属走线，金属走线位于栅线的对应区域内。
进一步的，所述从区域和所述主区域的面积比为6∶4或5∶5或4∶6。
本发明带来了以下有益效果：本发明实施例提供了一种阵列基板，该阵列基板中的子像素单元包括主区域和从区域，主区域和从区域各设置有一个薄膜晶体管。其中，两个薄膜晶体管的源极相连且相连的源极呈直线型，漏极相互绝缘分开。本发明实施例提供的阵列基板上的两个薄膜晶体管的结构较为分散，使得源极和漏极的各处面积近似相等，可有效防止构图工艺过程中发生的光刻胶残留的现象。进而防止光刻胶残留带来的源极和漏极短路的不良结果，降低了阵列基板的制备难度，同时保证了显示装置的显示效果。
本发明第二方面提供了一种显示装置，该显示装置包括上述的阵列基板。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有技术的子像素单元的结构示意图；
图2是适用于图1的薄膜晶体管的半透掩膜板的形状示意图；
图3是图2的半透掩膜板的曝光后的显影效果示意图；
图4是图3的A-A截面图；
图5至图7是以图4为基础的制备流程示意图；
图8至图11是本发明实施例中提供的薄膜晶体管的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本实施例中提供了一种阵列基板，包括呈阵列式设置的若干个子像素单元1，每个子像素单元1包括主区域11和从区域12，主区域11和从区域12各设置有一个薄膜晶体管2。
其中，两个薄膜晶体管2的源极21相连且相连的源极21呈直线型，漏极22相互绝缘分开。
具体的，目前的阵列基板通常是通过四道构图工艺制备而成的，其中薄膜晶体管2的有源层23、源极21和漏极22的图案是在同一道构图工艺中形成的，利用的是半透掩膜板4。现有技术中的阵列基板的有源层23、源极21和漏极22的图案可利用如图2所示的半透掩膜板4制成，该半透掩膜板4包括全透光区域、半透光区域41和不透光区域42。比较图2和图1可知，不透光区域42对应的源极21和漏极22，半透光区域41对应的源极21和漏极22之间的、暴露在外的有源层23。
在阵列基板的衬底基板5上形成栅极24、栅极绝缘层25之后，在栅极绝缘层25之上依次形成非晶硅层231、N型掺杂非晶硅层232和金属层6，之后在金属层6之上通过涂覆形成光刻胶7。
如图3所示，利用图2所示的半透掩膜板4对上述的结构进行曝光工艺。曝光工艺中，半透掩膜板4放置在待曝光结构的上方，光线自半透掩膜板4之上向待曝光结构射下，将半透掩膜板4的形状投影在待曝光结构上。
之后，对曝光后的待曝光结构结构进行显影处理。如图3所示，半透掩膜板4的全透光区域对应的光刻胶7受到大量光照，显影处理后被完全去除，形成光刻胶7的完全去除区71；半透光区域41对应的光刻胶7受到部分光照，显影处理后部分被去除，形成厚度较小的部分保留区72；不透光区域42对应的光刻胶7未受到光照，显影处理后没有任何变化，形成厚度较大的完全保留区73。接下来，依次经过第一次湿法蚀刻、第一次干法蚀刻、第一次灰化工艺、第二次湿法蚀刻、第二次干法蚀刻工艺、第二次灰化工艺处理后，形成图1中所示的薄膜晶体管的结构。
其中，部分光线的光路受到半透掩膜板4的不透光区域42的影响，将以衍射的形式透过半透掩膜板4、照射在待曝光结构上，衍射的光线在待曝光结构上的照射区域主要对应着所形成的部分保留区72。因此，曝光工艺后，由于图2中的不透光区域42中的B区域面积较大，导致透过位于B区域和漏极22之间的C区域的光线相对较少，少于半透光区域41的其他区域。结合图3和图4所示，可知C区域透过的光少于其他半透光区域41。将导致C区域对应的、部分保留区72中的C1区域在显影处理后，残留的光刻胶的厚度相对于部分保留区的其余部分而言较厚，大约多了0.08微米。如图5所示，为对图4所示的结构进行了第一次湿法蚀刻和第一次干法蚀刻之后的结构示意图。如图6所示，对图5所示的结构进行了第一次灰化工艺之后，部分保留区72的C1区域极有可能残留部分光刻胶7。导致残留的光刻胶覆盖的源极21和漏极22之间的金属层6未能够去除，最终形成如图7所示的结构，此时，薄膜晶体管2的源极21和漏极22短路。
薄膜晶体管2的源极21和漏极22短路，使得该薄膜晶体管2不受控于栅极24施加的驱动信号，时刻接收来自数据线8的数据信号，导致该薄膜晶体管2对应的子像素单元1的显示异常，通常为亮点。更严重的是，由曝光工艺导致的薄膜晶体管2的源极21和漏极22短路的现象通常是成片存在，即液晶显示面板上出现由成片的亮点组成的亮斑，而亮斑不便于修复。因此，现有技术中的两薄膜晶体管2的源极21的图形易导致液晶显示面板的显示效果不理想，使得现有技术的阵列基板的生产成本较高。
为了解决薄膜晶体管2的源极21和漏极22易短路的技术问题，本发明实施例采用了 明显区别于图1所示的薄膜晶体管2的源级21和漏极22的图形，如下所示：
例如，如图8所示，此时两个薄膜晶体管2的源极21相连且相连的源极21呈直线型，薄膜晶体管2的漏极22为弧线形，两个薄膜晶体管2的漏极22呈镜像对称、分别设置在源极1的两端外。图8中，两个薄膜晶体管2的源极21相连，并且薄膜晶体管2上的源极21和漏极22的图形各处大小相差不多，并不像图1所示的存在面积明显大于别处的部分。则在利用半透掩膜板4对该薄膜晶体管2的源极21、漏极22和有源层23等结构进行构图工艺时，半透光区域41各处透过的光线的强度几乎相等，使得在显影后所形成的部分保留区72的光刻胶7的厚度大致相等。则在进行第一次灰化工艺后，半透光区域41对应的光刻胶7可基本完全去除，不存在前文所说的光刻胶7残留的现象。之后的第二次刻蚀工艺可顺利进行，将源极21和漏极22完全分隔开来。
另外，由于阵列基板上还包括纵横交错的栅线9和数据线8，两相邻的栅线9和两相邻的数据线8划分出一个子像素单元1。则为了保证薄膜晶体管2的有源层23可以受到栅极24上加载的栅极驱动信号的驱动，导通源极21和漏极22。如图8所示，两个薄膜晶体管2整体放置在栅极24之上，且栅极24与栅线9一体成型。
同时，为了使得源极21和数据线8电连接，如图8所示，阵列基板上还设置有金属走线10。该金属走线10包括相互垂直的两部分、分别连接数据线8和源极21的两部分。连接数据线8的部分垂直于数据线8、平行于栅线9，而连接源极21的部分平行于数据线8、垂直于栅线9。在不改变栅线9和栅极24的宽度的前提下，该金属走线10部分位于栅线9和栅极21的对应区域之外，导致该子像素单元1的开口率稍微下降。
为了提高子像素单元1的开口率，可基于图8所示的结构进行调整。如图9所示，在y方向上，将金属走线10以及两个薄膜晶体管2整体变窄，直至金属走线10以及两个薄膜晶体管2均可位于栅极24和栅线9的对应区域内。显然，图9所示的金属走线10不会影响子像素单元1的开口率。
其中，在图9所示的结构中，薄膜晶体管2的沟道长度减小，由原先的4.5微米缩短为3微米。相应的，半透掩膜板4的解析度也需要减小，通常为3微米或更小。
虽然图9结构有利于提高子像素单元1的开口率，但是沟道宽度的降低，可能导致沟道不良情况的出现，例如可能导致部分子像素单元1形成亮点。此时，可通过暗点化等方式对这些亮点修补，即利用焊接工艺将栅线9或栅极24与像素电极导通，提供像素电压强迫液晶旋转使得这些子像素单元1永远呈现暗点化状态。
另外，如图10所示，本发明实施例还提供另一种明显区别于图8和图9所示的薄膜晶体管2的结构。具体的，图10中，薄膜晶体管2的漏极22为直线型，两个薄膜晶体管 2的漏极22分别设置在源极21的两侧，与源极21平行。此时，金属走线10与源极21在同一直线上，位于栅线24的对应区域内。
图10所示的设计中，有源层23的导电沟道的宽度可与现有技术或图8所示的结构一致，为4.5微米，可防止沟道宽度降低导致的一些不良情况的出现。同时，金属走线10和两个薄膜晶体管2均位于栅线9的对应区域内，可保证子像素单元1的开口率，进而保证该显示装置的显示效果。
另外，还可针对图10所示的结构进行简单的变形，得到图11所示的结构。在图11所示的结构中，薄膜晶体管2的漏极22为直线型，两个薄膜晶体管2的漏极22并排设置在源极21的同一侧。图11所示的结构较图10所示的结构而言更紧凑，有利于缩小栅极24的区域，提高子像素单元1的开口率。
需要说明的是，图8至图11中，处于同一平面的金属走线10、源极21和漏极22的间距应至少为3微米，以保证该子像素单元1的正常工作。
在本发明实施例中，子像素单元的主区域和从区域的面积比可为6∶4或5∶5或4∶6等常见的配比，也可根据实际情况进行选择、设置，本发明实施例对此不进行限定。
综上，本发明实施例提供了一种阵列基板，该阵列基板中的子像素单元包括主区域和从区域，主区域和从区域各设置有一个薄膜晶体管。其中，两个薄膜晶体管的源极相连且相连的源极呈直线型，漏极相互绝缘分开。本发明实施例提供的阵列基板上的两个薄膜晶体管的结构较为分散，使得源极和漏极的各处面积近似相等，可有效防止构图工艺过程中发生的光刻胶残留的现象。进而防止光刻胶残留带来的源极和漏极短路的不良结果，降低了阵列基板的制备难度，同时保证了显示装置的显示效果。
本实施例第二方面提供了一种显示装置，该显示装置包括上述的阵列基板，该显示装置可为液晶电视、液晶显示器、手机、平板电脑等显示装置。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。
附图标记说明：
1-子像素单元； 11-主区域；   12-从区域；
2-薄膜晶体管； 21-源极；     22-漏极；
23-有源层；    231-非晶硅层；232-N型掺杂非晶硅层；
24-栅极；          25-栅极绝缘层；    3-分压电容；
4-半透掩膜板；     41-半透光区域；    42-不透光区域；
5-衬底基板；       6-金属层；         7-光刻胶；
71-完全去除区；    72-部分保留区；    73-完全保留区；
8-数据线；         9-栅线；           10-金属走线。

Claims (18)

  1. 一种阵列基板，其中，包括呈阵列式设置的若干个子像素单元，每个所述子像素单元包括主区域和从区域，所述主区域和所述从区域各设置有一个薄膜晶体管，其中，
    两个薄膜晶体管的源极相连且相连的源极呈直线型，漏极相互绝缘分开。
  2. 根据权利要求1所述的阵列基板，其中，薄膜晶体管的漏极为弧线形，两个薄膜晶体管的漏极呈镜像对称、分别设置在源极的两端外。
  3. 根据权利要求1所述的阵列基板，其中，薄膜晶体管的漏极为直线型，两个薄膜晶体管的漏极分别设置在源极的两侧，与源极平行。
  4. 根据权利要求1所述的阵列基板，其中，薄膜晶体管的漏极为直线型，两个薄膜晶体管的漏极并排设置在源极的同一侧。
  5. 根据权利要求1所述的阵列基板，其中，还包括纵横交错的栅线和数据线，两相邻的栅线和两相邻的数据线划分出一个子像素单元。
  6. 根据权利要求5所述的阵列基板，其中，薄膜晶体管还包括栅极，栅极与栅线一体成型。
  7. 根据权利要求6所述的阵列基板，其中，还包括连接数据线和源极的金属走线，金属走线位于栅线和栅极的对应区域内。
  8. 根据权利要求6所述的阵列基板，其中，还包括连接数据线和源极的金属走线，金属走线位于栅线的对应区域内。
  9. 根据权利要求1所述的阵列基板，其中，所述从区域和所述主区域的面积比为6∶4或5∶5或4∶6。
  10. 一种显示装置，其中，包括阵列基板，所述阵列基板包括呈阵列式设置的若干个子像素单元，每个所述子像素单元包括主区域和从区域，所述主区域和所述从区域各设置有一个薄膜晶体管，两个薄膜晶体管的源极相连且相连的源极呈直线型，漏极相互绝缘分开。
  11. 根据权利要求10所述的显示装置，其中，薄膜晶体管的漏极为弧线形，两个薄膜晶体管的漏极呈镜像对称、分别设置在源极的两端外。
  12. 根据权利要求10所述的显示装置，其中，薄膜晶体管的漏极为直线型，两个薄膜晶体管的漏极分别设置在源极的两侧，与源极平行。
  13. 根据权利要求10所述的显示装置，其中，薄膜晶体管的漏极为直线型，两个薄膜晶体管的漏极并排设置在源极的同一侧。
  14. 根据权利要求10所述的显示装置，其中，还包括纵横交错的栅线和数据线，两 相邻的栅线和两相邻的数据线划分出一个子像素单元。
  15. 根据权利要求14所述的显示装置，其中，薄膜晶体管还包括栅极，栅极与栅线一体成型。
  16. 根据权利要求15所述的显示装置，其中，还包括连接数据线和源极的金属走线，金属走线位于栅线和栅极的对应区域内。
  17. 根据权利要求15所述的显示装置，其中，还包括连接数据线和源极的金属走线，金属走线位于栅线的对应区域内。
  18. 根据权利要求10所述的显示装置，其中，所述从区域和所述主区域的面积比为6∶4或5∶5或4∶6。
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