WO2016074584A1 - 一种薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

一种薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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WO2016074584A1
WO2016074584A1 PCT/CN2015/093818 CN2015093818W WO2016074584A1 WO 2016074584 A1 WO2016074584 A1 WO 2016074584A1 CN 2015093818 W CN2015093818 W CN 2015093818W WO 2016074584 A1 WO2016074584 A1 WO 2016074584A1
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photoresist
pattern
electrode
source
region
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PCT/CN2015/093818
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English (en)
French (fr)
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胡合合
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京东方科技集团股份有限公司
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Priority to EP15858837.6A priority Critical patent/EP3220415B1/en
Priority to US15/322,460 priority patent/US20170243901A1/en
Publication of WO2016074584A1 publication Critical patent/WO2016074584A1/zh
Priority to US16/388,349 priority patent/US10651212B2/en

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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor (TFT) array substrate, a method for fabricating the same, and a display device.
  • TFT thin film transistor
  • the manufacturing process of the thin film transistor array substrate includes a preparation process of 7 masks, 6 masks, 5 masks and 4 masks. It can be understood that the fewer the number of Masks in the fabrication process of the thin film transistor array substrate, the more favorable the cost reduction.
  • the present disclosure provides a thin film transistor array substrate, a preparation method thereof, and a display device for reducing the number of masks in the preparation process of the thin film transistor array substrate.
  • the present disclosure provides a method for fabricating a thin film transistor array substrate, including:
  • a pattern of the pixel electrode and the passivation layer is formed by one patterning process.
  • the step of forming a pattern of the pixel electrode and the passivation layer by one patterning process comprises:
  • the photoresist is exposed and developed by using a common mask to form a photoresist full retention area and a photoresist full removal area, and the photoresist full retention area includes a pixel electrode, a common electrode line, and a source/drain electrode. a region corresponding to the pattern, the photoresist full removal region includes a region corresponding to a pattern between the source and drain electrodes and a passivation layer;
  • the drain electrode pattern area is covered by the pixel electrode;
  • the photoresist in the fully retained region of the photoresist is stripped to form a pattern of the passivation layer.
  • the step of forming a pattern of the gate electrode, the common electrode, the gate insulating layer, the active layer, and the source/drain metal layer on the substrate comprises:
  • a pattern of a gate electrode, a common electrode, and a common electrode line connection portion is formed on the substrate by one patterning process.
  • the step of forming a pattern of the gate electrode, the common electrode and the common electrode line connection on the substrate by one patterning process comprises:
  • the remaining region includes a region corresponding to a pattern of a gate electrode and a common electrode line connection portion, and the photoresist semi-reserved region includes a region corresponding to a pattern of the common electrode, and the photoresist full removal region is in addition to the photoresist a reserved area and other areas than the photoresist semi-reserved area;
  • the photoresist in the completely remaining region of the photoresist is stripped to expose a pattern of the gate electrode and the common electrode line connection portion.
  • the step of forming a pattern of the gate electrode, the common electrode, the gate insulating layer, the active layer, and the source/drain metal layer on the substrate comprises:
  • a pattern of the gate insulating layer, the active layer, and the source/drain metal layer is formed by one patterning process.
  • the step of forming a pattern of the gate insulating layer, the active layer, and the source/drain metal layer by one patterning process includes:
  • the remaining area includes a region corresponding to the pattern of the active layer
  • the photoresist full removal region includes a region corresponding to the pattern of the common electrode line connection portion
  • the photoresist semi-reserved region is in addition to the photoresist a reserved area and other areas than the entire photoresist removal area
  • the photoresist in the completely remaining region of the photoresist is stripped to expose a pattern of the source/drain metal layer and the active layer.
  • the present disclosure also provides a thin film transistor array substrate, including: a substrate, and a gate electrode, a common electrode, a gate insulating layer, an active layer, and a source/drain electrode disposed on the substrate; and a pixel electrode disposed on the gate insulating And a layer is connected to the drain electrode; a passivation layer is disposed on the gate insulating layer and a channel region of the source and drain electrodes.
  • the thin film transistor array substrate further includes:
  • a common electrode line which is disposed in the same material as the pixel electrode.
  • the gate electrode is disposed on the substrate
  • the common electrode is disposed on the substrate
  • the thin film transistor further includes:
  • a transparent conductive film retaining portion is disposed between the gate electrode and the substrate, and is disposed in the same material as the common electrode;
  • the common electrode line connecting portion is disposed on the common electrode and includes a first transparent conductive layer and a gate metal layer, and the common electrode is connected to the common electrode line through the common electrode line connecting portion.
  • the thin film transistor array substrate further includes:
  • the common electrode line connecting portion further includes: a second transparent conductive layer disposed in the same material as the gate electrode protective layer.
  • the thin film transistor array substrate further includes:
  • the source electrode protection portion covers the source electrode and is disposed in the same material as the pixel electrode.
  • the present disclosure also provides a display device including the above-described thin film transistor array substrate.
  • the pattern of the pixel electrode and the passivation layer can be formed by one patterning process, thereby reducing the number of masks in the preparation process of the thin film transistor array substrate and reducing the production cost.
  • 1-1 to 1-7 are schematic diagrams of a method of forming a pattern of a gate electrode, a common electrode, and a common electrode line connection portion on a substrate by one patterning process according to an embodiment of the present disclosure
  • 2-1 to 2-7 are schematic views showing a method of forming a pattern of a gate insulating layer, an active layer, and a source/drain metal layer by one patterning process according to an embodiment of the present disclosure
  • 3-1 to 3-7 are schematic diagrams showing a method of forming a pattern of a pixel electrode, a common electrode line, a source/drain electrode, and a passivation layer by one patterning process according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural view of a thin film transistor array substrate according to an embodiment of the present disclosure.
  • a passivation layer (PVX) is usually deposited on the source and drain electrodes, and a via hole is formed on the passivation layer by a patterning process, and then A transparent conductive film is formed on the passivation layer, and a pattern of the pixel electrode is formed by one patterning process, wherein the pixel electrode is connected to the drain electrode through the via hole. That is to say, in the conventional thin film transistor array substrate preparation process, two masks are required to form the passivation layer and the pixel electrode.
  • the embodiment of the present disclosure provides a method for fabricating a thin film transistor array substrate, including the following steps:
  • Step S1 forming a pattern of a gate electrode, a common electrode, a gate insulating layer, an active layer, and a source/drain metal layer on the substrate;
  • Step S2 On the substrate on which the pattern of the gate electrode, the common electrode, the gate insulating layer, the active layer, and the source/drain metal layer is formed, a pattern of the pixel electrode and the passivation layer is formed by one patterning process.
  • the pattern of the pixel electrode and the passivation layer can be formed by one patterning process, thereby reducing the number of masks in the preparation process of the thin film transistor array substrate and reducing the production cost.
  • the source/drain metal layer formed in step S1 completely covers the channel between the source and drain electrodes, that is, the channel between the source electrode and the drain electrode is not formed, and may be a source.
  • the drain metal layer does not cover the channel, that is, a channel between the source electrode and the drain electrode has been formed.
  • the step of forming the pattern of the pixel electrode and the passivation layer by one patterning process includes:
  • Step S211 forming a third transparent conductive film; the third transparent conductive film may be a conductive film such as ITO or IZO.
  • Step S212 coating a photoresist on the third transparent conductive film
  • Step S213 exposing and developing the photoresist by using a common mask to form a photoresist a fully-retained area including a region corresponding to a pattern of a pixel electrode, a common electrode line, and a source-drain electrode, and a photoresist-removed area including a source-drain electrode The area corresponding to the pattern of the channel and the passivation layer;
  • Step S214 etching a third transparent conductive film in the photoresist removal region by an etching process to form a pattern of a pixel electrode, a common electrode line, and a source electrode protection portion; wherein the source electrode protection portion covers the source electrode pattern region Upper, for covering the source electrode, the drain electrode pattern area is covered by the pixel electrode;
  • Step S215 etching a source/drain metal layer of the photoresist removal region by an etching process to form a pattern of source and drain electrodes;
  • the source electrode protection portion covers the source pattern region, the source/drain metal layer of the source electrode region can be protected from being etched, and the drain electrode region is covered by the pixel electrode, thereby protecting The source/drain metal layer of the drain electrode region is not etched.
  • Step S216 forming a passivation layer film
  • Step S217 peeling off the photoresist in the photoresist-retained region to form a pattern of the passivation layer.
  • a common electrode line is formed at the same time as the pixel electrode is formed, that is, the common electrode line is coplanar with the pixel electrode, so that the overlap of the common electrode and the pixel electrode is easily realized when a bright spot occurs, and the bright point is darkened. point.
  • the common electrode line and the pixel electrode may not be simultaneously formed.
  • step S213 a pattern in which the photoresist full-retention region includes only the pixel electrode and the source-drain electrode is formed.
  • the corresponding area does not include the area corresponding to the pattern of the common electrode line.
  • the pixel electrode is formed, and the passivation layer film is formed without stripping the photoresist, and then the photoresist of the photoresist is completely removed, so that the photoresist is located.
  • the passivation layer film on the photoresist is also peeled off, and the remaining photoresist is completely removed from the passivation layer film to form a passivation layer pattern, and the formed passivation layer is not covered by the transparent conductive film. Areas that form protection for these areas. It can be seen that in this embodiment, only one patterning process is required to form the pixel electrode and the passivation layer, thereby reducing the number of masks in the preparation process of the thin film transistor array substrate and reducing the production cost.
  • the step of forming the pattern of the pixel electrode and the passivation layer by one patterning process includes:
  • Step S221 forming a third transparent conductive film; the third transparent conductive film may be a conductive film such as ITO or IZO.
  • Step S222 coating a photoresist on the third transparent conductive film
  • Step S223 exposing and developing the photoresist by using a common mask to form a photoresist full retention area and a photoresist full removal area, wherein the photoresist full retention area includes a pixel electrode and a common electrode line. a region corresponding to the pattern, wherein the photoresist full removal region includes a region corresponding to the pattern of the passivation layer;
  • Step S224 etching a third transparent conductive film in the photoresist removal region by an etching process to form a pattern of the pixel electrode and the common electrode line;
  • Step S225 forming a passivation layer film
  • Step S226 peeling off the photoresist in the entire remaining area of the photoresist to form a pattern of the passivation layer.
  • a common electrode line is formed at the same time as the pixel electrode is formed, that is, the common electrode line is coplanar with the pixel electrode, so that the overlap of the common electrode and the pixel electrode is easily realized when a bright spot occurs, and the bright point is darkened. point.
  • the common electrode line and the pixel electrode may not be simultaneously formed.
  • step S223 a pattern in which the photoresist full-retention region includes only the pixel electrode and the source-drain electrode is formed.
  • the corresponding area does not include the area corresponding to the pattern of the common electrode line.
  • the pixel electrode is formed, and the passivation layer film is formed without stripping the photoresist, and then the photoresist of the photoresist is completely removed, so that the photoresist is located.
  • the passivation layer film on the photoresist is also peeled off, and the remaining photoresist is completely removed from the passivation layer film to form a passivation layer pattern, and the formed passivation layer is not covered by the transparent conductive film. Areas that form protection for these areas. It can be seen that in this embodiment, only one patterning process is required to form the pixel electrode and the passivation layer, thereby reducing the number of masks in the preparation process of the thin film transistor array substrate and reducing the production cost.
  • a pattern of a gate electrode, a common electrode, a gate insulating layer, an active layer, and a source/drain metal layer may be formed on the substrate by using a method in the prior art, in order to further reduce the number of masks.
  • the pattern of the gate electrode, the common electrode, the gate insulating layer, the active layer, and the source/drain metal layer may be formed on the substrate by the following method.
  • a pattern of a gate electrode, a common electrode, and a common electrode line connection portion may be formed on a substrate by one patterning process.
  • the step of forming a pattern of the gate electrode, the common electrode, and the common electrode line connection portion on the substrate by one patterning process may include:
  • Step S111 sequentially forming a first transparent conductive film, a gate metal film and a second transparent conductive film on the substrate;
  • the first transparent conductive film and the second transparent conductive film may be conductive films such as ITO or IZO.
  • Step S112 coating a photoresist on the second transparent conductive film
  • Step S113 exposing and developing the photoresist by using a gray tone or a halftone mask to form a photoresist full retention region, a photoresist semi-retention region, and a photoresist full removal region, wherein the light
  • the photoresist-retained area includes a region corresponding to a pattern of a gate electrode and a common electrode line connection portion
  • the photoresist semi-reserved region includes a region corresponding to a pattern of a common electrode
  • the photoresist full removal region is in addition to the light a fully-retained area of the glue and other areas than the semi-reserved area of the photoresist;
  • the common electrode line connecting portion formed in this step is for connecting a common electrode and a common electrode line, which is coplanar with the pixel electrode and formed simultaneously with the pixel electrode as described in the above embodiment.
  • Step S114 removing the first transparent conductive film, the gate metal film and the second transparent conductive film in the photoresist removal region by an etching process
  • Step S115 removing the photoresist of the semi-reserved region of the photoresist by an ashing process
  • Step S116 etching and removing the gate metal film and the second transparent conductive film of the semi-reserved region of the photoresist by an etching process to form a pattern of the common electrode;
  • Step S117 peeling off the photoresist in the completely remaining region of the photoresist to expose a pattern of the gate electrode and the common electrode line connection portion.
  • a gate electrode protection layer formed by the remaining second transparent conductive film is formed on the gate electrode, and the gate electrode is formed in the subsequent etching of the source/drain metal layer. Protection, of course, in other embodiments of the present disclosure, if the etching process can be better controlled when the source/drain metal layer is etched, the gate electrode protection layer may not be formed. In the step S111, it is only necessary to sequentially form the first transparent conductive film and the gate metal film on the substrate, and it is not necessary to form the second transparent conductive film.
  • the common electrode line is not disposed coplanar with the pixel electrode
  • only the pattern of the gate electrode and the common electrode may be formed on the substrate by one patterning process.
  • the photoresist full-retention region formed includes only the region corresponding to the pattern of the gate electrode.
  • the patterns of the gate insulating layer, the active layer, and the source/drain metal layers may also be formed by one patterning process.
  • the step of forming a pattern of the gate insulating layer, the active layer, and the source/drain metal layer by one patterning process may include:
  • Step S121 sequentially forming a gate insulating film, an active layer film, and a source/drain metal film;
  • Step S122 coating a photoresist on the source/drain metal film
  • Step S123 exposing and developing the photoresist by using a gray tone or a halftone mask to form a photoresist full retention region, a photoresist semi-retention region, and a photoresist full removal region, wherein the light
  • the photoresist-retained region includes a region corresponding to a pattern of the active layer
  • the photoresist-removed region includes a region corresponding to a pattern of the common electrode line connection portion
  • the photoresist semi-reserved region is in addition to the light a fully-retained area of the glue and other areas than the entire removed area of the photoresist;
  • the common electrode line connecting portion in this step is for connecting the common electrode and the common electrode line, and the common electrode line is coplanar with the pixel electrode and formed simultaneously with the pixel electrode as described in the above embodiment.
  • Step S124 removing a gate insulating film, an active layer film, and a source/drain metal film in the entire removed region of the photoresist by an etching process
  • Step S125 removing the photoresist of the semi-reserved region of the photoresist by an ashing process
  • Step S126 etching and removing the source/drain metal film and the active layer film of the semi-reserved region of the photoresist by an etching process to form a pattern of the gate insulating layer;
  • Step S127 peeling off the photoresist in the completely remaining region of the photoresist to expose a pattern of the source/drain metal layer and the active layer.
  • the source/drain metal layer completely covers the channel between the source and drain electrodes, that is, the channel between the source and drain electrodes is not formed, so that the subsequent formation of the pixel electrode is performed. In the etching process, the channel is protected.
  • the method of the embodiment of the present disclosure is described by taking a bottom gate type thin film transistor array substrate as an example.
  • the pixel electrode and the passivation layer are formed by one patterning process in the preparation method of the embodiment of the present disclosure.
  • the patterning step is also applicable to the top gate type thin film transistor array substrate.
  • step S1 the pattern of the gate electrode, the common electrode, the gate insulating layer, the active layer and the source/drain metal layer can be formed on the substrate by using two patterning processes, that is, the embodiment of the present disclosure
  • the preparation method of the thin film transistor array substrate the preparation of the thin film transistor array substrate can be realized by using the three-time patterning process, so that the number of masks is minimized, and the preparation process is simple and easy to control.
  • Step S31 forming a pattern of a gate electrode, a common electrode, and a common electrode line connection portion on the substrate by one patterning process;
  • Step S32 forming a pattern of a gate insulating layer, an active layer, and a source/drain metal layer on a substrate on which a pattern of a gate electrode, a common electrode, and a common electrode line connection portion is formed by one patterning process;
  • Step S33 A pattern of the pixel electrode, the common electrode line, the source/drain electrode, and the passivation layer is formed on the substrate on which the pattern of the gate insulating layer, the active layer, and the source/drain metal layer is formed by one patterning process.
  • step S31 includes the following steps:
  • Step S311 sequentially forming a first transparent conductive film 201, a gate metal film 202, and a second transparent conductive film 203 on the substrate 101; the first transparent conductive film 201 and the second transparent conductive film 203 may be electrically conductive such as ITO or IZO. film.
  • Step S312 coating a photoresist 204 on the second transparent conductive film 203;
  • Step S313 exposing and developing the photoresist by using a gray tone or a halftone mask to form a photoresist full retention region 2041, a photoresist semi-retention region 2042, and a photoresist full removal region 2043, wherein
  • the photoresist full-retention region 2041 includes a region corresponding to a pattern of a gate electrode and a common electrode line connection portion
  • the photoresist semi-retention region 2042 includes a region corresponding to a pattern of a common electrode
  • 2043 is an area other than the photoresist full retention area 2041 and the photoresist semi-reserved area 2042;
  • Step S314 removing the first transparent conductive film 201, the gate metal film 202, and the second transparent conductive film 203 of the photoresist full removal region 2043 by an etching process;
  • Step S315 removing the photoresist of the photoresist semi-retained region 2042 by using an ashing process
  • Step S316 etching and removing the gate metal film 202 and the second transparent conductive film 203 of the photoresist semi-retained region 2042 by using an etching process to form a pattern of the common electrode 102;
  • Step S317 peeling off the photoresist of the photoresist completely remaining region 2041 to expose a pattern of the gate electrode 103 and the common electrode line connecting portion 104.
  • step S32 includes the following steps:
  • Step S321 sequentially forming a gate insulating film 301, an active layer film 302 and a source/drain metal film 303;
  • Step S322 coating a photoresist 304 on the source/drain metal film 303;
  • Step S323 exposing and developing the photoresist by using a gray tone or halftone mask to form a photoresist full retention area 3041, a photoresist semi-retention area 3042, and a photoresist full removal area 3043.
  • the photoresist full retention region 3041 includes a region corresponding to a pattern of an active layer
  • the photoresist full removal region 3043 includes a region corresponding to a pattern of the common electrode line connection portion
  • the photoresist semi-reserved region 3042 is a region other than the photoresist full retention region 3041 and the photoresist full removal region 3043;
  • Step S324 removing the gate insulating film 301, the active layer film 302, and the source/drain metal film 303 of the photoresist full removal region 3043 by an etching process;
  • Step S325 removing the photoresist of the photoresist semi-reserved region 3042 by using an ashing process
  • Step S326 etching and removing the source/drain metal film 303 and the active layer film 302 of the photoresist semi-retained region 3042 by using an etching process to form a pattern of the gate insulating layer 105;
  • Step S327 peeling off the photoresist of the photoresist completely remaining region 3041 to expose the pattern of the source/drain metal layer 107 and the active layer 106.
  • step S33 includes the following steps:
  • Step S331 forming a third transparent conductive film 401; the third transparent conductive film 401 may be a conductive film such as ITO or IZO.
  • Step S332 coating a photoresist 402 on the third transparent conductive film 401;
  • Step S333 exposing and developing the photoresist 402 by using a common mask to form light.
  • the photoresist fully-retained region 4021 and the photoresist full-removal region 4022 include a region corresponding to a pattern of a pixel electrode, a common electrode line, and a source/drain electrode, and the photoresist full removal region 4022 a region corresponding to a pattern of a channel and a passivation layer between the source and drain electrodes;
  • Step S334 etching the third transparent conductive film 401 of the photoresist full removal region 4022 by an etching process to form a pattern of the pixel electrode 108, the common electrode line 109, and the source electrode protection portion 110;
  • Step S335 etching the source/drain metal layer 107 of the photoresist full removal region 4022 by an etching process to form a pattern of the source electrode 1071 and the drain electrode 1072;
  • Step S336 forming a passivation layer film 403;
  • Step S337 peeling off the photoresist of the photoresist full retention region 4021 to form a pattern of the passivation layer 111.
  • an embodiment of the present disclosure further provides a thin film transistor array substrate, including:
  • a substrate 101 and a gate electrode 103, a common electrode 102, a gate insulating layer 105, an active layer 106, and a source electrode 1071 and a drain electrode 1072 disposed on the substrate 101;
  • a pixel electrode 108 is disposed on the gate insulating layer 105 and overlaps the drain electrode 1072;
  • a passivation layer 111 is disposed on the gate insulating layer 105 and a channel region of the source electrode 1071 and the drain electrode 1072.
  • the thin film transistor array substrate further includes: a common electrode line 109, and the common electrode line 109 is disposed in the same material as the pixel electrode 108.
  • the common electrode line 109 is coplanar with the pixel electrode 108, and when the bright spot occurs, the common electrode 102 and the pixel electrode 108 are easily overlapped, and the bright spot is changed to a dark spot.
  • the thin film transistor array substrate further has the following structure:
  • the gate electrode 103 is disposed on the substrate 101;
  • the common electrode 102 is disposed on the substrate 101;
  • the thin film transistor array substrate further includes:
  • the transparent conductive film retaining portion 112 is located between the gate electrode 103 and the substrate 101, and is disposed in the same material as the common electrode 102;
  • a common electrode line connecting portion 104 is disposed on the common electrode 102, including a first transparent guide
  • the electric layer 1041 and the gate metal layer 1042 are connected to the common electrode line 109 through the common electrode line connecting portion 104.
  • the thin film transistor array substrate further includes:
  • the common electrode line connecting portion 104 further includes a second transparent conductive layer 1043 disposed in the same material as the gate electrode protective layer 113.
  • the thin film transistor array substrate further includes:
  • the source electrode protection portion 110 covers the source electrode 1071 and is provided in the same material as the pixel electrode 108.
  • Embodiments of the present disclosure also provide a display device including the above-described thin film transistor array substrate.

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Abstract

提供一种薄膜晶体管阵列基板及其制备方法、显示装置，该制备方法包括：在基板（101）上形成栅电极（103）、公共电极（102）、栅绝缘层(105)、有源层(106)和源漏金属层的图形；以及，在形成有栅电极（103）、公共电极（102）、栅绝缘层(105)、有源层(106)和源漏金属层的图形的基板上，通过一次构图工艺形成像素电极(108)和钝化层(111)的图形。

Description

一种薄膜晶体管阵列基板及其制备方法、显示装置
相关申请的交叉引用
本申请主张在2014年11月13日在中国提交的中国专利申请号No.201410641424.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管(TFT)阵列基板及其制备方法、显示装置。
背景技术
为了实现高PPI(每英寸所拥有的像素数目)和高产能，减小薄膜晶体管的尺寸和减少其制备过程中使用的mask(掩膜工艺)数量非常有必要。目前薄膜晶体管阵列基板的制程工艺中，包括7道mask，6道mask，5道mask和4道mask的制备工艺。可以了解的是，薄膜晶体管阵列基板的制作过程中Mask数量越少，越利于成本的降低。
发明内容
有鉴于此，本公开提供一种薄膜晶体管阵列基板及其制备方法、显示装置，用以减少薄膜晶体管阵列基板的制备过程中的mask数量。
为解决上述技术问题，本公开提供一种薄膜晶体管阵列基板的制备方法，包括：
在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形；
在形成有栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的基板上，通过一次构图工艺形成像素电极和钝化层的图形。
可选地，所述通过一次构图工艺形成像素电极和钝化层的图形的步骤包括：
形成第三透明导电薄膜；
在所述第三透明导电薄膜上涂覆光刻胶；
采用普通掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域和光刻胶全去除区域，所述光刻胶全保留区域包括像素电极、公共电极线和源漏电极的图形所对应区域，所述光刻胶全去除区域包括源漏电极之间的沟道和钝化层的图形所对应区域；
利用刻蚀工艺刻蚀所述光刻胶全去除区域的第三透明导电薄膜，形成像素电极、公共电极线和源电极保护部的图形；其中，所述源电极保护部覆盖源电极图形区域上方，所述漏电极图形区域上方被所述像素电极覆盖；
利用刻蚀工艺刻蚀所述光刻胶全去除区域的源漏金属层，形成源漏电极的图形，其中，所述像素电极搭接到所述漏电极上；
形成钝化层薄膜；
剥离所述光刻胶全保留区域的光刻胶，形成所述钝化层的图形。
可选地，在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的步骤包括：
通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形。
可选地，通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形的步骤包括：
在所述基板上依次形成第一透明导电薄膜、栅金属薄膜和第二透明导电薄膜；
在所述第二透明导电薄膜上涂覆光刻胶；
采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶全去除区域，其中，所述光刻胶全保留区域包括栅电极和公共电极线连接部的图形所对应区域，所述光刻胶半保留区域包括公共电极的图形所对应区域，所述光刻胶全去除区域为除所述光刻胶全保留区域和所述光刻胶半保留区域之外的其他区域；
采用刻蚀工艺去除所述光刻胶全去除区域的第一透明导电薄膜、栅金属薄膜和第二透明导电薄膜；
利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
利用刻蚀工艺刻蚀去除所述光刻胶半保留区域的栅金属薄膜和第二透明导电薄膜，形成公共电极的图形；
剥离所述光刻胶完全保留区域的光刻胶，露出所述栅电极和所述公共电极线连接部的图形。
可选地，在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的步骤包括：
通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形。
可选地，通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形的步骤包括：
依次形成栅绝缘薄膜、有源层薄膜和源漏金属薄膜；
在所述源漏金属薄膜上涂覆光刻胶；
采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶全去除区域，其中，所述光刻胶全保留区域包括有源层的图形所对应区域，所述光刻胶全去除区域包括所述公共电极线连接部的图形所对应区域，所述光刻胶半保留区域为除所述光刻胶全保留区域和所述光刻胶全去除区域之外的其他区域；
采用刻蚀工艺去除所述光刻胶全去除区域的栅绝缘薄膜、有源层薄膜和源漏金属薄膜；
利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
利用刻蚀工艺刻蚀去除所述光刻胶半保留区域的源漏金属薄膜和有源层薄膜，形成栅绝缘层的图形；
剥离所述光刻胶完全保留区域的光刻胶，露出所述源漏金属层和有源层的图形。
本公开还提供一种薄膜晶体管阵列基板，包括：基板，以及设置于所述基板上的栅电极、公共电极、栅绝缘层、有源层和源漏电极；像素电极，设置于所述栅绝缘层上，并搭接至所述漏电极上；钝化层，设置于所述栅绝缘层上和所述源漏电极的沟道区域。
可选地，所述薄膜晶体管阵列基板还包括：
公共电极线，所述公共电极线与所述像素电极同层同材料设置。
可选地，所述栅电极，设置于所述基板上；
所述公共电极，设置于所述基板上；
所述薄膜晶体管还包括：
透明导电薄膜保留部，位于所述栅电极和所述基板之间，与所述公共电极同层同材料设置；
公共电极线连接部，设置于所述公共电极上，包括第一透明导电层和栅金属层，所述公共电极通过所述公共电极线连接部与所述公共电极线连接。
可选地，所述薄膜晶体管阵列基板还包括：
栅电极保护层，位于所述栅电极与所述栅绝缘层之间；
所述公共电极线连接部还包括：第二透明导电层，与所述栅电极保护层同层同材料设置。
可选地，所述薄膜晶体管阵列基板还包括：
源电极保护部，覆盖于所述源电极之上，与所述像素电极同层同材料设置。
本公开还提供一种显示装置，包括上述薄膜晶体管阵列基板。
本公开的上述技术方案的有益效果如下：
通过一次构图工艺便可形成像素电极和钝化层的图形，从而减少了薄膜晶体管阵列基板的制备过程中的mask数量，降低了生产成本。
附图说明
图1-1至1-7为本公开实施例的通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形的方法示意图；
图2-1至2-7为本公开实施例的通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形的方法示意图；
图3-1至3-7为本公开实施例的通过一次构图工艺形成像素电极、公共电极线、源漏电极和钝化层的图形的方法示意图；
图4为本公开实施例的薄膜晶体管阵列基板的一结构示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
现有的薄膜晶体管阵列基板制备工艺中，在形成源漏电极之后，通常在源漏电极上沉积一层钝化层(PVX)，并通过一次构图工艺在钝化层上形成过孔，然后在钝化层上形成一层透明导电薄膜，并通过一次构图工艺形成像素电极的图形，其中，像素电极通过该过孔与漏电极连接。也就是说，现有的薄膜晶体管阵列基板制备工艺中，需要2道mask，才能够形成钝化层和像素电极。
为了减少薄膜晶体管阵列基板的制备过程中的mask数量，本公开实施例提供一种薄膜晶体管阵列基板的制备方法，包括以下步骤：
步骤S1：在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形；
步骤S2：在形成有栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的基板上，通过一次构图工艺形成像素电极和钝化层的图形。
通过本公开实施例提供的方法，通过一次构图工艺便可形成像素电极和钝化层的图形，从而减少了薄膜晶体管阵列基板的制备过程中的mask数量，降低了生产成本。
下面对通过一次构图工艺形成像素电极和钝化层的图形的方法进行详细说明。
在步骤S1中，形成的源漏金属层的图形中，可以是源漏金属层完全覆盖源漏电极之间的沟道，即源电极和漏电极之间的沟道未形成，也可以是源漏金属层未覆盖沟道，即源电极和漏电极之间的沟道已形成。
当步骤S1中形成的源漏金属层的图形中源漏金属层完全覆盖源漏电极之间的沟道时，所述通过一次构图工艺形成像素电极和钝化层的图形的步骤包括：
步骤S211：形成第三透明导电薄膜；所述第三透明导电薄膜可以为ITO或IZO等导电薄膜。
步骤S212：在所述第三透明导电薄膜上涂覆光刻胶；
步骤S213：采用普通掩膜板对所述光刻胶进行曝光、显影，形成光刻胶 全保留区域和光刻胶全去除区域，所述光刻胶全保留区域包括像素电极、公共电极线和源漏电极的图形所对应区域，所述光刻胶全去除区域包括源漏电极之间的沟道和钝化层的图形所对应区域；
步骤S214：利用刻蚀工艺刻蚀所述光刻胶全去除区域的第三透明导电薄膜，形成像素电极、公共电极线和源电极保护部的图形；其中，源电极保护部覆盖源电极图形区域上方，用于覆盖源电极，所述漏电极图形区域上方被所述像素电极覆盖；
步骤S215：利用刻蚀工艺刻蚀所述光刻胶全去除区域的源漏金属层，形成源漏电极的图形；
该步骤中，由于源电极保护部覆盖在源电极图形区域上方，因而，可以保护源电极区域的源漏金属层不被刻蚀，由于漏电极区域上方被所述像素电极覆盖，因而，可以保护漏电极区域的源漏金属层不被刻蚀。
步骤S216：形成钝化层薄膜；
步骤S217：剥离所述光刻胶全保留区域的光刻胶，形成所述钝化层的图形。
在本实施例中，在形成像素电极的同时，还形成公共电极线，即公共电极线与像素电极共面，从而在出现亮点时容易实现公共电极和像素电极的搭接，将亮点变为暗点。
当然，在本公开的其他实施例中，也可以不将公共电极线和像素电极同时形成，此时，在步骤S213中，形成光刻胶全保留区域仅包括像素电极和源漏电极的图形所对应区域，不包括公共电极线的图形所对应区域。
上述实施例中，在形成源漏金属层之后，先形成像素电极，并在不剥离光刻胶的情况下，形成钝化层薄膜，然后剥离光刻胶全保留区域的光刻胶，使得位于该光刻胶之上的钝化层薄膜也随之剥落，剩下的光刻胶全去除区域的钝化层薄膜，形成钝化层的图形，形成的钝化层覆盖未被透明导电薄膜覆盖的区域，对这些区域形成保护。可以看出，本实施例中只需要一次构图工艺便可以形成像素电极和钝化层，从而减少了薄膜晶体管阵列基板的制备过程中mask的数量，降低了生产成本。
当步骤S1中形成的源漏金属层的图形中源漏金属层未覆盖源漏电极之 间的沟道，即源电极和漏电极之间的沟道已形成时，所述通过一次构图工艺形成像素电极和钝化层的图形的步骤包括：
步骤S221：形成第三透明导电薄膜；所述第三透明导电薄膜可以为ITO或IZO等导电薄膜。
步骤S222：在所述第三透明导电薄膜上涂覆光刻胶；
步骤S223：采用普通掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域和光刻胶全去除区域，所述光刻胶全保留区域包括像素电极和公共电极线的图形所对应区域，所述光刻胶全去除区域包括钝化层的图形所对应区域；
步骤S224：利用刻蚀工艺刻蚀所述光刻胶全去除区域的第三透明导电薄膜，形成像素电极和公共电极线的图形；
步骤S225：形成钝化层薄膜；
步骤S226：剥离所述光刻胶全保留区域的光刻胶，形成所述钝化层的图形。
在本实施例中，在形成像素电极的同时，还形成公共电极线，即公共电极线与像素电极共面，从而在出现亮点时容易实现公共电极和像素电极的搭接，将亮点变为暗点。
当然，在本公开的其他实施例中，也可以不将公共电极线和像素电极同时形成，此时，在步骤S223中，形成光刻胶全保留区域仅包括像素电极和源漏电极的图形所对应区域，不包括公共电极线的图形所对应区域。
上述实施例中，在形成源漏金属层之后，先形成像素电极，并在不剥离光刻胶的情况下，形成钝化层薄膜，然后剥离光刻胶全保留区域的光刻胶，使得位于该光刻胶之上的钝化层薄膜也随之剥落，剩下的光刻胶全去除区域的钝化层薄膜，形成钝化层的图形，形成的钝化层覆盖未被透明导电薄膜覆盖的区域，对这些区域形成保护。可以看出，本实施例中只需要一次构图工艺便可以形成像素电极和钝化层，从而减少了薄膜晶体管阵列基板的制备过程中mask的数量，降低了生产成本。
上述步骤S1中，可以采用现有技术中的方法，在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形，为了进一步减少mask的数 量，本公开实施例中，也可以采用以下方法，在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形。
例如，可以通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形。
具体的，通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形的步骤可以包括：
步骤S111：在基板上依次形成第一透明导电薄膜、栅金属薄膜和第二透明导电薄膜；所述第一透明导电薄膜和第二透明导电薄膜可以为ITO或IZO等导电薄膜。
步骤S112：在所述第二透明导电薄膜上涂覆光刻胶；
步骤S113：采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶全去除区域，其中，所述光刻胶全保留区域包括栅电极和公共电极线连接部的图形所对应区域，所述光刻胶半保留区域包括公共电极的图形所对应区域，所述光刻胶全去除区域为除所述光刻胶全保留区域和所述光刻胶半保留区域之外的其他区域；
本步骤中形成的所述公共电极线连接部，是用于连接公共电极和公共电极线，所述公共电极线如上述实施例中所述，与像素电极共面，且与像素电极同时形成。
步骤S114：采用刻蚀工艺去除所述光刻胶全去除区域的第一透明导电薄膜、栅金属薄膜和第二透明导电薄膜；
步骤S115：利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
步骤S116：利用刻蚀工艺刻蚀去除所述光刻胶半保留区域的栅金属薄膜和第二透明导电薄膜，形成公共电极的图形；
步骤S117：剥离所述光刻胶完全保留区域的光刻胶，露出所述栅电极和所述公共电极线连接部的图形。
上述实施例中，形成栅电极时，栅电极的上方会形成一由保留下的第二透明导电薄膜形成的栅电极保护层，在后续进行源漏金属层的刻蚀时，以对栅电极进行保护，当然，在本公开的其他实施例中，如果在源漏金属层的刻蚀时，刻蚀工艺可以较好控制的情况下，也可以不形成该栅电极保护层，此 时，步骤S111中，只需要在所述基板上依次形成第一透明导电薄膜和栅金属薄膜即可，不需要形成第二透明导电薄膜。
当然，在公共电极线不与像素电极共面设置的其他实施例中，本公开实施例中，可以通过一次构图工艺在基板上仅形成栅电极和公共电极的图形。此时，上述步骤S113中，形成的光刻胶全保留区域仅包括栅电极的图形所对应区域。
为了进一步减少mask的数量，本公开实施例中，还可以通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形。
具体的，通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形的步骤可以包括：
步骤S121：依次形成栅绝缘薄膜、有源层薄膜和源漏金属薄膜；
步骤S122：在所述源漏金属薄膜上涂覆光刻胶；
步骤S123：采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶全去除区域，其中，所述光刻胶全保留区域包括有源层的图形所对应区域，所述光刻胶全去除区域包括所述公共电极线连接部的图形所对应区域，所述光刻胶半保留区域为除所述光刻胶全保留区域和所述光刻胶全去除区域之外的其他区域；
本步骤中的所述公共电极线连接部，是用于连接公共电极和公共电极线，所述公共电极线如上述实施例中所述，与像素电极共面，且与像素电极同时形成。
步骤S124：采用刻蚀工艺去除所述光刻胶全去除区域的栅绝缘薄膜、有源层薄膜和源漏金属薄膜；
步骤S125：利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
步骤S126：利用刻蚀工艺刻蚀去除所述光刻胶半保留区域的源漏金属薄膜和有源层薄膜，形成栅绝缘层的图形；
步骤S127：剥离所述光刻胶完全保留区域的光刻胶，露出所述源漏金属层和有源层的图形。
本实施例中形成的源漏金属层的图形中，源漏金属层完全覆盖源漏电极之间的沟道，即源漏电极之间的沟道未形成，使得后续在形成像素电极的刻 蚀工艺中，对沟道进行保护。
上述实施例中，是以底栅型的薄膜晶体管阵列基板为例，对本公开实施例的方法进行说明，当然，本公开实施例的制备方法中的通过一次构图工艺形成像素电极和钝化层的图形的步骤，也适用于顶栅型的薄膜晶体管阵列基板。
通过上述描述可以看出，步骤S1中，采用两次构图工艺，便可在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形，即本公开实施例的薄膜晶体管阵列基板的制备方法中，采用3次构图工艺，即可实现薄膜晶体管阵列基板的制备，使得mask的数量最大程度的减少，制备工艺简单易控制。
下面对通过3次构图工艺实现薄膜晶体管阵列基板的制备的方法进行说明：
步骤S31：通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形；
步骤S32：通过一次构图工艺在形成有栅电极、公共电极和公共电极线连接部的图形的基板上，形成栅绝缘层、有源层和源漏金属层的图形；
步骤S33：通过一次构图工艺在形成有栅绝缘层、有源层和源漏金属层的图形的基板上，形成像素电极、公共电极线、源漏电极和钝化层的图形。
请参考图1-1至图1-7，步骤S31包括以下步骤：
步骤S311：在基板101上依次形成第一透明导电薄膜201、栅金属薄膜202和第二透明导电薄膜203；所述第一透明导电薄膜201和第二透明导电薄膜203可以为ITO或IZO等导电薄膜。
步骤S312：在所述第二透明导电薄膜203上涂覆光刻胶204；
步骤S313：采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域2041、光刻胶半保留区域2042和光刻胶全去除区域2043，其中，所述光刻胶全保留区域2041包括栅电极和公共电极线连接部的图形所对应区域，所述光刻胶半保留区域2042包括公共电极的图形所对应区域，所述光刻胶全去除区域2043为除所述光刻胶全保留区域2041和所述光刻胶半保留区域2042之外的其他区域；
步骤S314：采用刻蚀工艺去除所述光刻胶全去除区域2043的第一透明导电薄膜201、栅金属薄膜202和第二透明导电薄膜203；
步骤S315：利用灰化工艺去除所述光刻胶半保留区域2042的光刻胶；
步骤S316：利用刻蚀工艺刻蚀去除所述光刻胶半保留区域2042的栅金属薄膜202和第二透明导电薄膜203，形成公共电极102的图形；
步骤S317：剥离所述光刻胶完全保留区域2041的光刻胶，露出所述栅电极103和所述公共电极线连接部104的图形。
请参考图2-1至图2-7，步骤S32包括以下步骤：
步骤S321：依次形成栅绝缘薄膜301、有源层薄膜302和源漏金属薄膜303；
步骤S322：在所述源漏金属薄膜303上涂覆光刻胶304；
步骤S323：采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域3041、光刻胶半保留区域3042和光刻胶全去除区域3043，其中，所述光刻胶全保留区域3041包括有源层的图形所对应区域，所述光刻胶全去除区域3043包括所述公共电极线连接部的图形所对应区域，所述光刻胶半保留区域3042为除所述光刻胶全保留区域3041和所述光刻胶全去除区域3043之外的其他区域；
步骤S324：采用刻蚀工艺去除所述光刻胶全去除区域3043的栅绝缘薄膜301、有源层薄膜302和源漏金属薄膜303；
步骤S325：利用灰化工艺去除所述光刻胶半保留区域3042的光刻胶；
步骤S326：利用刻蚀工艺刻蚀去除所述光刻胶半保留区域3042的源漏金属薄膜303和有源层薄膜302，形成栅绝缘层105的图形；
步骤S327：剥离所述光刻胶完全保留区域3041的光刻胶，露出所述源漏金属层107和有源层106的图形。
请参考图3-1至图3-7，步骤S33包括以下步骤：
步骤S331：形成第三透明导电薄膜401；所述第三透明导电薄膜401可以为ITO或IZO等导电薄膜。
步骤S332：在所述第三透明导电薄膜401上涂覆光刻胶402；
步骤S333：采用普通掩膜板对所述光刻胶402进行曝光、显影，形成光 刻胶全保留区域4021和光刻胶全去除区域4022，所述光刻胶全保留区域4021包括像素电极、公共电极线和源漏电极的图形所对应区域，所述光刻胶全去除区域4022包括源漏电极之间的沟道和钝化层的图形所对应区域；
步骤S334：利用刻蚀工艺刻蚀所述光刻胶全去除区域4022的第三透明导电薄膜401，形成像素电极108、公共电极线109和源电极保护部110的图形；
步骤S335：利用刻蚀工艺刻蚀所述光刻胶全去除区域4022的源漏金属层107，形成源电极1071和漏电极1072的图形；
步骤S336：形成钝化层薄膜403；
步骤S337：剥离所述光刻胶全保留区域4021的光刻胶，形成所述钝化层111的图形。
如图4所示，本公开实施例还提供一种薄膜晶体管阵列基板，包括：
基板101，以及设置于所述基板101上的栅电极103、公共电极102、栅绝缘层105、有源层106和源电极1071和漏电极1072；
像素电极108，设置于所述栅绝缘层105上，并搭接至所述漏电极1072上；
钝化层111，设置于所述栅绝缘层105上和所述源电极1071和漏电极1072的沟道区域。
可选地，所述薄膜晶体管阵列基板还包括：公共电极线109，所述公共电极线109与所述像素电极108同层同材料设置。
即，所述公共电极线109与所述像素电极108共面，在出现亮点时容易实现公共电极102和像素电极108搭接，将亮点变为暗点。
可选地，所述薄膜晶体管阵列基板还具有以下结构：
所述栅电极103，设置于所述基板101上；
所述公共电极102，设置于所述基板101上；
所述薄膜晶体管阵列基板还包括：
透明导电薄膜保留部112，位于所述栅电极103和所述基板101之间，与所述公共电极102同层同材料设置；
公共电极线连接部104，设置于所述公共电极102上，包括第一透明导 电层1041和栅金属层1042，所述公共电极102通过所述公共电极线连接部104与所述公共电极线109连接。
可选地，所述薄膜晶体管阵列基板还包括：
栅电极保护层113，位于所述栅电极103与所述栅绝缘层105之间；
所述公共电极线连接部104还包括：第二透明导电层1043，与所述栅电极保护层113同层同材料设置。
可选地，所述薄膜晶体管阵列基板还包括：
源电极保护部110，覆盖于所述源电极1071之上，与所述像素电极108同层同材料设置。
本公开实施例还提供一种显示装置，包括上述薄膜晶体管阵列基板。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (12)

  1. 一种薄膜晶体管阵列基板的制备方法，包括：
    在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形；
    在形成有所述栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的所述基板上，通过一次构图工艺形成像素电极和钝化层的图形。
  2. 根据权利要求1所述的制备方法，其中，所述通过一次构图工艺形成像素电极和钝化层的图形的步骤包括：
    形成第三透明导电薄膜；
    在所述第三透明导电薄膜上涂覆光刻胶；
    采用普通掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域和光刻胶全去除区域，所述光刻胶全保留区域包括像素电极、公共电极线和源漏电极的图形所对应区域，所述光刻胶全去除区域包括源漏电极之间的沟道和钝化层的图形所对应区域；
    利用刻蚀工艺刻蚀所述光刻胶全去除区域的第三透明导电薄膜，形成像素电极、公共电极线和源电极保护部的图形；其中，所述源电极保护部覆盖源电极图形区域上方，所述漏电极图形区域上方被所述像素电极覆盖；
    利用刻蚀工艺刻蚀所述光刻胶全去除区域的源漏金属层，形成源漏电极的图形，其中，所述像素电极搭接到所述漏电极上；
    形成钝化层薄膜；
    剥离所述光刻胶全保留区域的光刻胶，形成所述钝化层的图形。
  3. 根据权利要求1所述的制备方法，其中，在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的步骤包括：
    通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形。
  4. 根据权利要求3所述的制备方法，其中，通过一次构图工艺在基板上形成栅电极、公共电极和公共电极线连接部的图形的步骤包括：
    在所述基板上依次形成第一透明导电薄膜、栅金属薄膜和第二透明导电 薄膜；
    在所述第二透明导电薄膜上涂覆光刻胶；
    采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶全去除区域，其中，所述光刻胶全保留区域包括栅电极和公共电极线连接部的图形所对应区域，所述光刻胶半保留区域包括公共电极的图形所对应区域，所述光刻胶全去除区域为除所述光刻胶全保留区域和所述光刻胶半保留区域之外的其他区域；
    采用刻蚀工艺去除所述光刻胶全去除区域的第一透明导电薄膜、栅金属薄膜和第二透明导电薄膜；
    利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
    利用刻蚀工艺刻蚀去除所述光刻胶半保留区域的栅金属薄膜和第二透明导电薄膜，形成公共电极的图形；
    剥离所述光刻胶完全保留区域的光刻胶，露出所述栅电极和所述公共电极线连接部的图形。
  5. 根据权利要求3所述的制备方法，其中，在基板上形成栅电极、公共电极、栅绝缘层、有源层和源漏金属层的图形的步骤包括：
    通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形。
  6. 根据权利要求5所述的制备方法，其中，通过一次构图工艺形成栅绝缘层、有源层和源漏金属层的图形的步骤包括：
    依次形成栅绝缘薄膜、有源层薄膜和源漏金属薄膜；
    在所述源漏金属薄膜上涂覆光刻胶；
    采用灰色调或半色调掩膜板对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶全去除区域，其中，所述光刻胶全保留区域包括有源层的图形所对应区域，所述光刻胶全去除区域包括所述公共电极线连接部的图形所对应区域，所述光刻胶半保留区域为除所述光刻胶全保留区域和所述光刻胶全去除区域之外的其他区域；
    采用刻蚀工艺去除所述光刻胶全去除区域的栅绝缘薄膜、有源层薄膜和源漏金属薄膜；
    利用灰化工艺去除所述光刻胶半保留区域的光刻胶；
    利用刻蚀工艺刻蚀去除所述光刻胶半保留区域的源漏金属薄膜和有源层薄膜，形成栅绝缘层的图形；
    剥离所述光刻胶完全保留区域的光刻胶，露出所述源漏金属层和有源层的图形。
  7. 一种薄膜晶体管阵列基板，包括：基板，以及设置于所述基板上的栅电极、公共电极、栅绝缘层、有源层和源漏电极；其中，所述薄膜晶体管阵列基板还包括：
    像素电极，设置于所述栅绝缘层上，并搭接至所述漏电极上；
    钝化层，设置于所述栅绝缘层上和所述源漏电极的沟道区域。
  8. 根据权利要求7所述的薄膜晶体管阵列基板，还包括：
    公共电极线，所述公共电极线与所述像素电极同层同材料设置。
  9. 根据权利要求8所述的薄膜晶体管阵列基板，其中，
    所述栅电极，设置于所述基板上；
    所述公共电极，设置于所述基板上；
    所述薄膜晶体管还包括：
    透明导电薄膜保留部，位于所述栅电极和所述基板之间，与所述公共电极同层同材料设置；
    公共电极线连接部，设置于所述公共电极上，包括第一透明导电层和栅金属层，所述公共电极通过所述公共电极线连接部与所述公共电极线连接。
  10. 根据权利要求9所述的薄膜晶体管阵列基板，还包括：
    栅电极保护层，位于所述栅电极与所述栅绝缘层之间；
    所述公共电极线连接部还包括：第二透明导电层，与所述栅电极保护层同层同材料设置。
  11. 根据权利要求8所述的薄膜晶体管阵列基板，还包括：
    源电极保护部，覆盖于所述源电极之上，与所述像素电极同层同材料设置。
  12. 一种显示装置，包括权利要求7-11任一项所述的薄膜晶体管阵列基板。
PCT/CN2015/093818 2014-11-13 2015-11-05 一种薄膜晶体管阵列基板及其制备方法、显示装置 WO2016074584A1 (zh)

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