WO2016074402A1 - Procédé et appareil d'exécution de transmission de signal, et dispositif - Google Patents
Procédé et appareil d'exécution de transmission de signal, et dispositif Download PDFInfo
- Publication number
- WO2016074402A1 WO2016074402A1 PCT/CN2015/074533 CN2015074533W WO2016074402A1 WO 2016074402 A1 WO2016074402 A1 WO 2016074402A1 CN 2015074533 W CN2015074533 W CN 2015074533W WO 2016074402 A1 WO2016074402 A1 WO 2016074402A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- clock domain
- hold
- output
- request
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Definitions
- the present invention relates to the field of communications, and in particular to a signal transmission processing method, apparatus, and device.
- the two clocks of the asynchronous FIFO are used to complete the writing of data to and from the FIFO, respectively.
- Cross-clock domain transmission of signals is accomplished through a complete write and read process.
- the above technical solution can be used to realize signal transmission across a clock domain, the following technical problem exists: if the first scheme is adopted, that is, register processing is directly performed on the signal, firstly, the metastable state cannot be guaranteed to be eliminated, and the register is beaten. In the process, due to the change of the clock domain to which the signal belongs, it may cause signal loss; if the second scheme is adopted, the asynchronous FIFO method is used to process the signal transmission across the clock domain, although the metastable state can be effectively eliminated. However, the FIFO itself occupies more hardware resources and increases the logic complexity.
- the invention provides a signal transmission processing method, device and device, so as to at least solve the technical problem that the cross-clock domain signal transmission process in the related art has more hardware resources and is complicated to implement.
- a signal processing method including: detecting a request signal generated by a first device in a first clock domain, wherein the request signal is used to indicate that the first time is allowed Receiving data in the clock domain; converting the request signal into a hold signal, the hold signal being a signal that remains valid until the hold signal is successfully synchronized in the second clock domain; using the second clock domain pair The hold signal is synchronized to obtain an output signal of the request signal and output the output signal to a second device located in the second clock domain.
- the method further includes: synchronizing the output signal by using the first clock domain to obtain an invalidation for the hold signal. signal.
- At least one of the following signals is 1 bit: the request signal, the hold signal, and the output signal.
- a signal transmission processing apparatus comprising: a detection module configured to detect a request signal generated by a first device in a first clock domain, wherein the request signal is used to indicate permission Receiving data in the first clock domain; a conversion module configured to convert the request signal into a hold signal, wherein the hold signal is a signal that remains valid until the hold signal is successfully synchronized in the second clock domain; a first synchronization module configured to synchronize the hold signal by using the second clock domain to obtain an output signal of the request signal; and an output module configured to output the output signal to be located in the second clock domain The second device in the middle.
- the apparatus further includes: a second synchronization module configured to synchronize the output signal by the first clock domain to obtain a signal for invalidating the hold signal.
- the apparatus further includes: a receiving module configured to receive a response signal generated in the second clock domain according to the output signal; and a third synchronization module configured to synchronize the response signal to the a first clock domain, and outputting the synchronized response signal to the first device, wherein the response signal is used to trigger the first device to receive data from the second device.
- a signal transmission processing apparatus comprising: a controller configured to convert the request signal into a hold when detecting a request signal from a first device in a first clock domain Transmitting, and transmitting the hold signal to a synchronization register, wherein the request signal is for indicating that data is allowed to be received in the first clock domain, the hold signal being successful for synchronizing the hold signal in a second clock domain Previously, a valid signal is continuously maintained; the synchronization register is coupled to the controller and is configured to utilize the The second clock domain synchronizes the hold signal to obtain an output signal of the request signal, and outputs the output signal to a second device located in the second clock domain.
- the device further includes: a feedback register connected to the synchronization register, configured to feed back the output signal to the controller, and synchronize the output signal by using the first clock domain And obtaining a signal for invalidating the hold signal, and transmitting a signal invalidating the hold signal to the controller.
- a feedback register connected to the synchronization register, configured to feed back the output signal to the controller, and synchronize the output signal by using the first clock domain And obtaining a signal for invalidating the hold signal, and transmitting a signal invalidating the hold signal to the controller.
- the controller is further configured to receive a response signal generated in the second clock domain according to the output signal, and synchronize the response signal to the first clock domain, and synchronize The subsequent response signal is output to the first device, wherein the response signal is used to trigger the first device to receive data from the second device.
- the embodiment of the present invention solves the related art by using a technical means for converting a request signal generated by a first device in a first clock domain into a hold signal, and synchronizing and outputting the hold signal by using the second clock domain.
- the cross-clock domain signal transmission process has technical problems such as occupying more hardware resources and realizing complexity, thereby ensuring elimination of metastability while reducing hardware resources and reducing implementation complexity.
- FIG. 1 is a flowchart of a method for processing a signal transmission according to an embodiment of the present invention
- FIG. 2 is a block diagram showing the structure of a signal transmission processing apparatus according to an embodiment of the present invention.
- FIG. 3 is a block diagram showing another structure of a signal transmission processing apparatus according to an embodiment of the present invention.
- FIG. 4 is a block diagram showing the structure of a signal transmission processing device according to an embodiment of the present invention.
- FIG. 7 is a schematic diagram showing the internal working principle of a Sync & Pulse Broaden module according to an embodiment of the present invention.
- FIG. 8 is a waveform diagram for embodying a signal trans-clock domain transmission process in accordance with an embodiment of the present invention.
- the embodiments of the present invention provide a solution for signal transmission between different clock domains, which is used to implement signals, in which the signals in the related art cannot completely avoid metastability, occupy more hardware resources, and implement complexities. Passing between different clock domains.
- the scheme supports signal transmission between clock domains with completely different frequency and phase, and supports transmission of signals with a pulse width smaller than a clock cycle. This implementation is described in detail below.
- Step S102 detecting a request signal generated by the first device in the first clock domain, where the request signal is used to indicate that data is allowed to be received in the first clock domain;
- Step S106 synchronizing the hold signal by using the second clock domain to obtain an output signal of the request signal, and outputting the output signal to a second device located in the second clock domain.
- the request signal transmitted to the second clock domain is converted into the hold signal, and the valid signal can be continuously maintained until the hold signal is successfully synchronized by the second clock domain, the broadening of the pulse signal can be realized. It avoids the defect that the metastable state cannot be completely eliminated, and saves register resources and reduces the complexity of realizing signals transmitted across time domains.
- the output signal may be used to set: the above-mentioned holding signal is utilized by using the second clock domain. After the synchronization, the output signal is synchronized by the first clock domain to obtain a signal for invalidating the hold signal, that is, the output signal obtained in step S106 is divided into two paths, and one output is output to the second device. The other way is to generate a signal that invalidates the above hold signal. In this way, the above-mentioned hold signal can be cleared when the above-mentioned output signal is successfully synchronized (ie, the set hold signal is invalid).
- the process of setting the hold signal to be invalid may be embodied as setting the hold signal to a low level, but is not limited thereto.
- the process for invalidating the above-mentioned hold signal may be implemented by a self-feedback mechanism.
- the execution body in steps S102-S106 is a designated device (for example, a controller)
- the output signal may be synchronized through the first clock domain. And feedback to the designated device, by which the above holding signal is set to be invalid.
- the request signal sent to the second clock domain is converted into the hold signal that remains valid, it is also necessary to detect that the first clock domain generates the request signal, and after outputting the output signal, receive the output according to the output.
- Acknowledgement signal generated by the signal in the second clock domain synchronizing the response signal to the first clock domain, and outputting the synchronized response signal to the first device, wherein the response signal is used to trigger the first
- the device receives data from the second device. This allows data to be transmitted in different clock domains. In a specific application process, it can be expressed as the following process, but is not limited to:
- the second device sends the response signal to the interface signal line Data_Out and holds it, and after the first device receives the response signal, sets the request signal to be invalid, and receives the The data of the two devices.
- At least one of the request signal, the hold signal, and the output signal may be set to 1 bit in order to save operating resources. This saves register resources:
- the request, feedback, and hold signals used in the handshake phase are single bits, the number of registers used in the intermediate handshake process is far less than a multiple of 8, and the data is one-time after the handshake is completed. Passed to the target clock domain, the intermediate process does not require register participation, so it can save more than three times the number of registers than the two- or three-level beat method.
- the built-in FIFO itself will use a lot of registers to achieve, for example, when the width is 8 and the depth is 2, at least 16 registers are used, and the number of used registers is far more than the embodiment of the present invention.
- the reason why the embodiment of the present invention can reduce the amount of register usage is to use a plurality of single-bit signals to complete the intermediate handshake. After the handshake is completed, the multi-bit data is transmitted at one time, and the multi-bit data is avoided in the intermediate step. Passing, which reduces the number of registers used.
- the embodiment of the invention further provides a signal transmission processing device for implementing the above method.
- the device includes the following processing modules:
- the detecting module 20 is configured to detect a request signal generated by the first device in the first clock domain, where the request signal is used to indicate that data is allowed to be received in the first clock domain;
- the conversion module 22 is connected to the detection module 20, and is configured to convert the request signal into a hold signal, where the hold signal is a signal that remains valid until the synchronization signal is successfully synchronized in the second clock domain;
- the first synchronization module 24 is connected to the conversion module 22, and is configured to synchronize the holding signal by using the second clock domain to obtain an output signal of the request signal.
- the output module 26 is coupled to the first synchronization module 24 and configured to output the output signal to a second device located in the second clock domain.
- the signal processing device of the embodiment of the present invention may further include: a second synchronization module 28 configured to synchronize the output signal by using the first clock domain, A signal for invalidating the above-described hold signal is obtained.
- the signal processing device of the embodiment of the present invention may further include: a receiving module 30 configured to receive a response signal generated in the second clock domain according to the output signal.
- a third synchronization module 32 coupled to the receiving module 30, configured to synchronize the response signal to the first clock domain, and output the synchronized response signal to the first device, wherein the response signal is used to trigger The first device receives data from the second device.
- the embodiment of the invention further provides a signal transmission processing device. As shown in FIG. 4, the device includes:
- a controller also referred to as a control register 40 configured to, when detecting a request signal from the first device in the first clock domain, convert the request signal into a hold signal, and send the hold signal to a sync register, wherein The request signal is used to indicate that data is allowed to be received in the first clock domain, and the hold signal is a signal that remains valid until the synchronization signal is successfully synchronized in the second clock domain;
- the synchronization register 42 is connected to the controller 40, and is configured to synchronize the hold signal by using the second clock domain to obtain an output signal of the request signal, and output the output signal to a second located in the second clock domain. device.
- the method may further include: a feedback register 44 connected to the synchronization register 42 and configured to feed back the output signal to the controller, and to output the output signal through the first clock domain. Synchronization is performed to obtain a signal for invalidating the above-described hold signal, and a signal for invalidating the hold signal is transmitted to the controller 40.
- the controller 40 is further configured to receive a response signal generated in the second clock domain according to the output signal, and synchronize the response signal to the first clock domain, and synchronize the The response signal is output to the first device, wherein the response signal is used to trigger the first device to receive data from the second device.
- the registers (for example, the synchronization register, the feedback register, and the like) involved in the signal processing device of the signal provided in the embodiment of the present invention may be one or more, and the specific number may be determined according to actual conditions.
- the preferred embodiment of the present invention provides a transmission system that can automatically spread the signal according to the handshake signal and can realize the cross-clock domain transmission of the signal, improve the correctness of the signal transmission, and ensure the normal and stable operation of the system.
- the signal transmission processing apparatus mainly includes the following parts: a host (corresponding to the first device in the above embodiment), a slave (corresponding to the second device in the above embodiment), and a synchronous stretching module (equivalent The transmission processing device and/or the signal transmission processing device of the signal provided in the above embodiment.
- the clock domain corresponding to the host is the master clock
- the clock domain of the slave is the slave clock.
- the synchronous stretch module has both the Master Clock and the Slave Clock.
- the functions of the host include: issuing a request signal, receiving data, and ending the current request signal according to the slave response signal.
- the functions of the slave are: receiving the request signal, transmitting the data, and transmitting the response signal.
- the function of the synchronous stretch module is: synchronizing the request signal of the host, automatically expanding according to the response of the slave, and transmitting to the slave module; the response signal of the slave is synchronized and transmitted to the host.
- the master sends a request signal (Master_Req_In) to indicate that data can be received.
- the output signal of the request signal (Maste_Req_Out) is synchronized by the feedback register (1, 2) of the Master Clock clock domain, and becomes a clear signal of the keep signal, which is fed back to the control register to pull the keep signal back to low. Level.
- step (2) it is possible to prevent the host request signal (Master_Req_In) from being lost when synchronizing to the slave clock domain: when the first synchronization fails due to a large difference between the master clock and the slave clock, the keep signal cannot be cleared due to the failure. The signal will remain high until it is successfully synchronized by the Slave Clock. When the synchronization is successful, keep receives the clear signal and will be lowered to low level in time.
- Master_Req_In the host request signal
- Synchronous Stretching Module Synchronous Stretching Module synchronizes the response signal (Slave_Ack_In) to the Master Clock clock domain, becomes Slave_Ack_Out and outputs it to the host.
- the transmission of signals across the clock domain is realized by the handshake signal.
- the host module can initiate the request signal again until the two handshaking successfully completes the data transmission.
- the waveform diagram of Figure 8 also exemplifies the complete steps of signal transmission across the clock domain.
- clk and pclk are two different clocks, and signals data1 ⁇ data4 are passed from pclk to clk.
- the first is that the clk clock domain issues the request signal Master_Req_In.
- the synchronous stretching module receives the request signal Master_Req_In of the host, and uses Master_Req_In as the determination signal to generate a single-bit hold signal keep in the Master Clock domain. After the keep signal is synchronized by the Slave Clock domain, it becomes the output signal of the request signal, Maste_Req_Out. Output to the slave.
- the Maste_Req_Out becomes a clear signal for keeping the keep signal, which is used to pull the keep signal back to the low level.
- the slave uses this signal to generate an acknowledge signal Slave_Ack_In in the Slave Clock domain, which will be sent at the same time.
- the data is placed on the interface signal line Data_Out and held.
- the Synchronous Stretching Module (Sync&Pulse Broaden) synchronizes the response signal Slave_Ack_In to the Master Clock clock domain, becomes Slave_Ack_Out and outputs it to the host.
- the host After the host detects the normal response signal Slave_Ack_Out, it pulls the request signal Master_Req_In back low, and the data on the slave interface signal line is stored in, thus completing the data transfer from the slave to the host. After the slave detects that the host request signal is pulled back low, it also turns its own acknowledge signal Slave_Ack_In low.
- the embodiments of the present invention achieve the following beneficial effects: (1) Compared with directly using the register beat, the metastable state cannot be completely eliminated, and when the number of signals to be transmitted is large, the number of times can be reduced. Use of register resources. (2) Compared with asynchronous FIFO, the complexity of the module and the use of hardware resources are reduced, and the implementation method is more concise.
- a storage medium is further provided, wherein the software includes the above-mentioned software, including but not limited to: an optical disk, a floppy disk, a hard disk, an erasable memory, and the like.
- modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network of multiple computing devices. Alternatively, they may be implemented by program code executable by a computing device such that they may be stored in a storage device by a computing device and, in some cases, may be executed in a different order than herein.
- the steps shown or described are either made separately into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.
- a technical means for converting a request signal generated by a first device in a first clock domain into a hold signal and synchronizing and outputting the hold signal by using the second clock domain is used.
- the signal transmission process across the clock domain has technical problems of occupying more hardware resources and realizing complexity, thereby ensuring elimination of metastability, reducing hardware resources, and reducing implementation complexity.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
La présente invention concerne un procédé et un appareil d'exécution de transmission de signal, et un dispositif. Le procédé comprend les étapes consistant à : détecter un signal de demande généré par un premier dispositif dans un premier domaine d'horloge, le signal de demande étant utilisé pour indiquer qu'il est autorisé à recevoir des données dans le premier domaine d'horloge; convertir le signal de requête dans un signal de maintien, le signal de maintien étant un signal effective restant en continu avant que le signal de maintien est synchronisée avec succès dans un second domaine d'horloge; et à synchroniser le signal de maintien à l'aide du second domaine d'horloge pour obtenir un signal de sortie du signal de demande, et délivrer en sortie le signal de sortie à un deuxième dispositif situé dans le second domaine d'horloge. La solution technique de la présente invention résout les problèmes techniques liés, dans l'état de la technique, au fait qu'un processus de transmission de signal dans un domaine inter horloges occupe une grande quantité de ressources matérielles, qu'il est complexe à implémenter, etc. L'invention réduit la quantité de ressources matérielles, simplifie l'implémentation et garantit l'élimination d'un état métastable.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410631790.3 | 2014-11-11 | ||
CN201410631790.3A CN105610532B (zh) | 2014-11-11 | 2014-11-11 | 信号的传输处理方法及装置、设备 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016074402A1 true WO2016074402A1 (fr) | 2016-05-19 |
Family
ID=55953666
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2015/074533 WO2016074402A1 (fr) | 2014-11-11 | 2015-03-18 | Procédé et appareil d'exécution de transmission de signal, et dispositif |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN105610532B (fr) |
WO (1) | WO2016074402A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112148655B (zh) * | 2019-06-28 | 2023-11-17 | 深圳市中兴微电子技术有限公司 | 多位数据跨时钟域的处理方法及装置 |
CN113821075A (zh) * | 2021-09-27 | 2021-12-21 | 上海航天计算机技术研究所 | 一种异步多比特信号跨时钟域处理方法及装置 |
CN114117972B (zh) * | 2022-01-26 | 2022-06-10 | 之江实验室 | 一种异步电路的同步装置和方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1124179A1 (fr) * | 2000-02-09 | 2001-08-16 | Texas Instruments Incorporated | Appareil à synchronisation d'un signal entre deux domaines d'horloge |
CN1552005A (zh) * | 2001-07-09 | 2004-12-01 | ����ɭ�绰�ɷ�����˾ | 状态指示检测装置和方法 |
CN102804158A (zh) * | 2010-03-19 | 2012-11-28 | 想象技术有限公司 | 总线架构中的请求和数据处理 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7977976B1 (en) * | 2010-05-21 | 2011-07-12 | Apple Inc. | Self-gating synchronizer |
-
2014
- 2014-11-11 CN CN201410631790.3A patent/CN105610532B/zh active Active
-
2015
- 2015-03-18 WO PCT/CN2015/074533 patent/WO2016074402A1/fr active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1124179A1 (fr) * | 2000-02-09 | 2001-08-16 | Texas Instruments Incorporated | Appareil à synchronisation d'un signal entre deux domaines d'horloge |
CN1552005A (zh) * | 2001-07-09 | 2004-12-01 | ����ɭ�绰�ɷ�����˾ | 状态指示检测装置和方法 |
CN102804158A (zh) * | 2010-03-19 | 2012-11-28 | 想象技术有限公司 | 总线架构中的请求和数据处理 |
Also Published As
Publication number | Publication date |
---|---|
CN105610532B (zh) | 2019-05-24 |
CN105610532A (zh) | 2016-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101574953B1 (ko) | 광 메모리 확장 아키텍처 | |
WO2020118950A1 (fr) | Dispositif esclave pour communications en série et procédé | |
US7925803B2 (en) | Method and systems for mesochronous communications in multiple clock domains and corresponding computer program product | |
JP5459807B2 (ja) | マルチプロセッサデータ処理システムにおけるデバッグシグナリング | |
JP6883377B2 (ja) | 表示ドライバ、表示装置及び表示ドライバの動作方法 | |
JP2011095978A (ja) | バスシステム及びバス制御方法 | |
KR20090061515A (ko) | Gals 시스템용 접속회로 및 그의 동작방법 | |
JP2012523616A5 (fr) | ||
WO2016074402A1 (fr) | Procédé et appareil d'exécution de transmission de signal, et dispositif | |
TW201227320A (en) | Throttling integrated link | |
JP3560793B2 (ja) | データ転送方法 | |
WO2016000376A1 (fr) | Procédé de traitement de signal et appareil de traitement de signal basés sur des interfaces pci-e | |
CN108170616B (zh) | 利用锁存器实现跨时钟域信号传输的系统 | |
WO2023103297A1 (fr) | Système et procédé d'optimisation des performances de transmission de données de bus ahb, et serveur | |
CN106101598A (zh) | 实现bt656视频信号转换为dc视频信号的fpga芯片及转换方法 | |
JP6272847B2 (ja) | クロック・ドメイン間のデータ転送 | |
WO2016127596A1 (fr) | Procédé et système de transmission de données asynchrones | |
JP5926583B2 (ja) | 情報処理装置、シリアル通信システムおよびそれらの通信初期化の方法、並びにシリアル通信装置 | |
KR102571154B1 (ko) | 반도체 장치, 반도체 시스템 및 반도체 장치의 동작 방법 | |
CN113821470B (zh) | 总线设备、嵌入式系统和片上系统 | |
JP5287394B2 (ja) | 同期伝送路及び該同期伝送路に用いられるデータ伝送方法 | |
TWI687815B (zh) | 資料發送方法、具有序列周邊介面之從屬裝置及資訊處理裝置 | |
RU2256949C2 (ru) | Способ и устройство дифференциального стробирования на коммуникационной шине | |
JP4799707B1 (ja) | データ同期化回路、通信インタフェース回路及び通信装置 | |
KR102568225B1 (ko) | 반도체 장치, 반도체 시스템 및 반도체 장치의 동작 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15859276 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15859276 Country of ref document: EP Kind code of ref document: A1 |