WO2016127596A1 - Procédé et système de transmission de données asynchrones - Google Patents

Procédé et système de transmission de données asynchrones Download PDF

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Publication number
WO2016127596A1
WO2016127596A1 PCT/CN2015/086056 CN2015086056W WO2016127596A1 WO 2016127596 A1 WO2016127596 A1 WO 2016127596A1 CN 2015086056 W CN2015086056 W CN 2015086056W WO 2016127596 A1 WO2016127596 A1 WO 2016127596A1
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WO
WIPO (PCT)
Prior art keywords
signal
data
register
synchronization
control signal
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PCT/CN2015/086056
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English (en)
Chinese (zh)
Inventor
汪波
陈杰
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中兴通讯股份有限公司
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Publication of WO2016127596A1 publication Critical patent/WO2016127596A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Definitions

  • This document refers to, but is not limited to, computer technology, especially an asynchronous data transmission method and system.
  • a handshake signal between asynchronous clock domains is used to control multi-channel asynchronous data bus transmission.
  • both the transmitting end and the receiving end need to perform the acknowledgement of the sending handshake control signal and the receiving handshake control signal, which may result in a large data transmission delay.
  • the embodiment of the invention provides an asynchronous data transmission method and system for solving the problem of large data transmission delay.
  • the embodiment of the invention provides an asynchronous data transmission method, including:
  • the method further includes:
  • the read data is output.
  • the method before the latching the latched data signal indicated by the multiplexed data latch signal according to the eigenvalue and the multiplexed data latch signal, the method further includes:
  • the first synchronization control signal is respectively subjected to at least two signal synchronization processing to obtain a second synchronization control signal and a third synchronization control signal;
  • the second synchronization control signal and the third synchronization control signal are logically processed to obtain a feature value of the first synchronization control signal.
  • the method before the acquiring the feature value of the first synchronization control signal, the method further includes:
  • the second data read signal is subjected to signal synchronization processing to obtain the first data read signal.
  • the first multiplexed data latch signal maintains a periodic delay of at least two of the second sampling clocks
  • the first data read signal maintains a periodic delay of at least three of the second sampling clocks.
  • An embodiment of the present invention further provides an asynchronous data transmission system, including: a signal synchronization module and a data latch module, and the signal synchronization module and the data latch module are connected;
  • the signal synchronization module is configured to obtain a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge;
  • the data latching module is configured to latch signals according to the characteristic value and the first multiplexed data, The latched data signal indicated by the first multiplexed data latch signal is latched.
  • the data latching module includes a first register, the first register is configured to acquire a first data read signal, and select the first data from the latched data signal according to the first data read signal. A plurality of data read read data indicated by the latch signal outputs the read data.
  • the signal synchronization module includes: a second register and a third register;
  • the second register is configured to use a first sampling clock to perform signal synchronization processing on the first synchronization control signal to obtain a second synchronization control signal;
  • the third register is configured to receive the second synchronization control signal input by the second register, and perform signal synchronization processing on the second synchronization control signal by using a first sampling clock to obtain a third synchronization control signal.
  • the signal synchronization module further includes: a fourth register, a fifth register, and a sixth register, wherein the fourth register, the fifth register, and the sixth register respectively input a second sampling clock;
  • the fourth register is configured to adopt a second sampling clock, and perform signal synchronization processing on the fourth synchronization control signal to obtain the first synchronization control signal;
  • the fifth register is configured to use a second sampling clock to perform signal synchronization processing on the second multiplexed data latch signal to obtain the first multiplexed data latch signal;
  • the sixth register is configured to perform a signal synchronization process on the second data read signal by using a second sampling clock to obtain the first data read signal.
  • the first multiplexed data latch signal maintains a periodic delay of at least two of the second sampling clocks
  • the first data read signal maintains a periodic delay of at least three of the second sampling clocks.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the above method.
  • the embodiment of the present invention includes: acquiring a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge; and according to the feature value and the first multiplexed data latch signal, The latched data signal indicated by the first multiplexed data latch signal is latched.
  • FIG. 1 is a schematic flowchart of an asynchronous data transmission method according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an asynchronous data transmission system according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an asynchronous data transmission system according to another embodiment of the present invention.
  • the asynchronous data transmission method provided by the embodiment of the present invention can be specifically applied to the asynchronous data transmission in the chip, and the chip can be a chip such as an FPGA.
  • the asynchronous data transmission method provided by this embodiment may be specifically implemented by an asynchronous data transmission system, which may be integrated in a chip, and the asynchronous data transmission system may be implemented by using software and/or hardware.
  • the asynchronous data transmission method provided in this embodiment will be described in detail below.
  • FIG. 1 is a schematic flowchart of an asynchronous data transmission method according to an embodiment of the present invention. As shown in FIG. 1 , an execution body of the method in this embodiment may be an asynchronous data transmission system. The method comprises the following steps:
  • Step 101 Acquire a feature value of the first synchronization control signal.
  • the feature value includes a rising edge or a falling edge.
  • Step 102 Latch the latched data signal indicated by the first multiplexed data latch signal according to the feature value and the first multiplexed data latch signal.
  • the applicable scenario of this embodiment is when the data terminal that initiates the request by the transmitting end is transmitted to the output data bus.
  • the first multiplexed data latch signal mux1 is sampled according to the eigenvalue sync_edge, so that the first multiplexed data latch signal mux1 can be stabilized, thereby determining that the multi-byte bit type data sampling satisfies the setup time and The time requirement is maintained to determine the correctness of the sampling of the first multiplexed data latch signal mux1, wherein the first multiplexed data latch signal mux1 is a multi-byte bit signal.
  • the eigenvalue includes a rising edge or a falling edge; and the first multiplexed data according to the eigenvalue and the first multiplexed data latch signal
  • the latched data signal indicated by the latch signal is latched, which realizes the sampling requirement of the setup and hold time during the asynchronous processing, determines the reliable transmission of the multi-way asynchronous data bus, and does not need to confirm the handshake signal, thereby reducing the handshake processing.
  • the method delays the processing of the handshake signal, which in turn increases the processing speed of the multi-way asynchronous data bus transmission.
  • the method may further include:
  • the read data is output.
  • the second data read signal is subjected to signal synchronization processing by using the second sampling clock to obtain the first data read signal.
  • the multiple asynchronous data buses data_bus[1] to data_bus[N] are selected and latched under the first sampling clock clk_r, waiting for the first data After the read signal read_en1 is valid, the latched data data_bus1 is output through the first register.
  • the first data read signal maintains a periodic delay of at least three of the second sampling clocks.
  • the method may further include:
  • the first synchronization control signal is respectively subjected to at least two signal synchronization processing to obtain a second synchronization control signal and a third synchronization control signal;
  • the second synchronization control signal and the third synchronization control signal are logically processed to obtain a feature value of the first synchronization control signal.
  • the first synchronization control signal sync1 is used to perform two-shot synchronous sampling on the first synchronization control signal sync1
  • the second synchronization control signal sync2 and the third synchronization control signal sync3 respectively generated are used to effectively reduce the asynchronous clock domain.
  • the production of metastable state is used to effectively reduce the asynchronous clock domain.
  • logic processing is performed, that is, the combination logic acquires the feature value sync_edge of the first synchronization control signal sync1, and when the sync_edge is valid, the first data bus latch signal latch_en is generated in cooperation with the second multiple data latch signal mux1, but When latching, the value of the second multiplexed data latch signal mux1 should be kept unchanged to ensure the setup time and the hold time, and to ensure reliable sampling of the asynchronous second multiplexed data latch signal mux1 data, wherein the first The multiplexed data latch signal maintains a periodic delay of at least two of said second sampling clocks.
  • the method before acquiring the feature value of the first synchronization control signal in step 101, the method further includes:
  • the second data read signal is subjected to signal synchronization processing to obtain the first data read signal.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the above method.
  • FIG. 2 is a schematic structural diagram of an asynchronous data transmission system according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an asynchronous data transmission system according to another embodiment of the present invention.
  • the asynchronous data transmission system of this embodiment is shown in FIG.
  • the method includes: a signal synchronization module and a data latch module, and the signal synchronization module and the data latch module are connected;
  • the signal synchronization module is configured to obtain a feature value of the first synchronization control signal Sync_edge, the feature value includes a rising edge or a falling edge;
  • the data latching module is configured to latch the latched data signal indicated by the first multiplexed data latch signal according to the characteristic value and the first multiplexed data latch signal.
  • the data latch module may latch the latched data signal indicated by the first multiplexed data latch signal according to the eigenvalue and the first multiplexed data latch signal, that is, the multiple asynchronous data bus data_bus [1] Select and latch to the data bus data_bus[N] (where N is an integer representing N different data buses).
  • the first multiplexed data latch signal mux1 is sampled according to the eigenvalue sync_edge, so that the first multiplexed data latch signal mux1 can be stabilized, thereby determining that the multi-byte bit type data sampling satisfies the setup time and The time requirement is maintained to determine the correctness of the sampling of the first multiplexed data latch signal mux1, wherein the first multiplexed data latch signal mux1 is a multi-byte bit signal.
  • the eigenvalue includes a rising edge or a falling edge; and the first multiplexed data according to the eigenvalue and the first multiplexed data latch signal
  • the latched data signal indicated by the latch signal is latched.
  • the asynchronous sampling process meets the sampling requirements, and the reliable transmission of the multi-way asynchronous data bus is determined.
  • the handshake signal is not needed, and the processing delay of the handshake handshake method is reduced, thereby improving the processing delay.
  • the data latching module includes a first register, the first register is configured to acquire a first data read signal, and select the first multiplexed data from the latched data signal according to the first data read signal The read data indicated by the latch signal is output, and the read data is output.
  • the signal synchronization module includes: a second register and a third register;
  • the second register is set to adopt a first sampling clock, and the first synchronization control signal sync1 is subjected to signal synchronization processing to obtain a second synchronization control signal sync2;
  • the third register is configured to receive the second synchronization control signal sync2 input by the second register, and perform signal synchronization processing on the second synchronization control signal by using a first sampling clock to obtain a third synchronization control signal.
  • Sync3 is configured to receive the second synchronization control signal sync2 input by the second register, and perform signal synchronization processing on the second synchronization control signal by using a first sampling clock to obtain a third synchronization control signal.
  • the signal synchronization module further includes: a fourth register, a fifth a register and a sixth register, wherein the fourth register, the fifth register, and the sixth register respectively input a second sampling clock;
  • the fourth register is set to use a second sampling clock, and the fourth synchronization control signal sync is subjected to signal synchronization processing to obtain the first synchronization control signal sync1;
  • the fifth register is set to use a second sampling clock to perform signal synchronization processing on the second multiplexed data latch signal mux to obtain the first multiplexed data latch signal mux1;
  • the sixth register is configured to perform a signal synchronization process on the second data read signal read_en by using a second sampling clock to obtain the first data read signal read_en1.
  • the processing data read signal synchronized by the sixth register may also adopt a second sampling clock, and perform synchronization processing through the seventh register to obtain a first data read signal.
  • the first multiplexed data latch signal maintains a periodic delay of at least two of the second sampling clocks
  • the first data read signal maintains a periodic delay of at least three of the second sampling clocks.
  • all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
  • the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
  • Each device/function module/function unit in the above embodiment is implemented in the form of a software function module. And when sold or used as a stand-alone product, it can be stored on a computer readable storage medium.
  • the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • the above technical solution realizes that the setup and hold time of the asynchronous processing meets the sampling requirement, determines the reliable transmission of the multi-way asynchronous data bus, and does not need to confirm the handshake signal, and reduces the processing delay of the handshake handshake method. In turn, the processing speed of the multi-way asynchronous data bus transmission is improved.

Abstract

L'invention concerne un procédé et un système de transmission de données asynchrones. Le procédé consiste à : acquérir une valeur caractéristique d'un premier signal de commande synchrone, la valeur caractéristique comprenant un front de montée ou un front de descente ; et verrouiller, en fonction de la valeur caractéristique et des premiers signaux de verrouillage de données à trajets multiples, un signal de données de verrouillage indiqué par les premiers signaux de verrouillage de données à trajets multiples. Grâce à l'invention, le temps d'établissement et de rétention répond aux exigences d'échantillonnage lorsqu'un traitement asynchrone est effectué, et une transmission fiable des bus de données asynchrones à trajets multiples est déterminée ; un signal d'établissement de liaison ne doit pas être confirmé, et le délai de traitement provoqué par les signaux d'établissement de liaison en va-et-vient dans le procédé de traitement d'établissement de liaison, ainsi que la vitesse de traitement des bus de transmission de données asynchrones à trajets multiples sont également améliorés.
PCT/CN2015/086056 2015-02-13 2015-08-04 Procédé et système de transmission de données asynchrones WO2016127596A1 (fr)

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US10157648B1 (en) * 2017-07-18 2018-12-18 Micron Technology, Inc. Data output for high frequency domain
CN113253796B (zh) * 2021-07-01 2021-10-08 北京智芯微电子科技有限公司 异步输入信号的同步方法及装置、中央处理器、芯片

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