WO2016127596A1

WO2016127596A1 - Asynchronous data transmission method and system

Info

Publication number: WO2016127596A1
Application number: PCT/CN2015/086056
Authority: WO
Inventors: 汪波; 陈杰
Original assignee: 中兴通讯股份有限公司
Priority date: 2015-02-13
Filing date: 2015-08-04
Publication date: 2016-08-18
Also published as: CN105988959B; CN105988959A

Abstract

An asynchronous data transmission method and system. The method comprises: acquiring a characteristic value of a first synchronous control signal, the characteristic value comprising a rising edge or a failing edge; and latching, according to the characteristic value and first multipath data latching signals, a latching data signal indicated by the first multipath data latching signals. It is achieved that establishment and retention time meets sampling requirements when asynchronous processing is performed, and reliable transmission of multipath asynchronous data buses is determined; a handshake signal does not need to be confirmed, the processing delay caused by back-and-forth handshake signals in the handshaking processing method, and the processing speed of the multipath asynchronous data transmission buses is further improved.

Description

[Invention name established by ISA according to Rule 37.2] Asynchronous data transmission method and system

Technical field

This document refers to, but is not limited to, computer technology, especially an asynchronous data transmission method and system.

Background technique

In field programmable gate array FPGA or chip design, data interaction of multiple asynchronous clock domains is often encountered.

In order to realize reliable transmission of asynchronous clock domain data, the related art generally adopts a handshake signal between asynchronous clock domains to control data transmission. For example, a handshake signal between asynchronous clock domains is used to control multi-channel asynchronous data bus transmission.

However, in the related art, both the transmitting end and the receiving end need to perform the acknowledgement of the sending handshake control signal and the receiving handshake control signal, which may result in a large data transmission delay.

Summary of the invention

The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims. (The following is a brief summary of subject matter that is described in greater detail herein. This summary is not intended to be limiting as to the scope of the claims.)

The embodiment of the invention provides an asynchronous data transmission method and system for solving the problem of large data transmission delay.

The embodiment of the invention provides an asynchronous data transmission method, including:

Obtaining a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge;

And latching the latched data signal indicated by the first multiplexed data latch signal according to the characteristic value and the first multiplexed data latch signal.

Optionally, after the latching the latched data signal indicated by the multiplexed data latching signal according to the eigenvalue and the multiplexed data latching signal, the method further includes:

Obtaining a first data read signal;

Selecting, according to the first data read signal, read data indicated by the first multiplexed data read latch signal from the latched data signals;

The read data is output.

Optionally, before the latching the latched data signal indicated by the multiplexed data latch signal according to the eigenvalue and the multiplexed data latch signal, the method further includes:

Using the first sampling clock, the first synchronization control signal is respectively subjected to at least two signal synchronization processing to obtain a second synchronization control signal and a third synchronization control signal;

The second synchronization control signal and the third synchronization control signal are logically processed to obtain a feature value of the first synchronization control signal.

Optionally, before the acquiring the feature value of the first synchronization control signal, the method further includes:

Using the second sampling clock, performing signal synchronization processing on the fourth synchronization control signal to obtain the first synchronization control signal; and/or

Using the second sampling clock, performing signal synchronization processing on the second multiplexed data latch signal to obtain the first multiplexed data latch signal; and/or

Using the second sampling clock, the second data read signal is subjected to signal synchronization processing to obtain the first data read signal.

Optionally, the first multiplexed data latch signal maintains a periodic delay of at least two of the second sampling clocks;

The first data read signal maintains a periodic delay of at least three of the second sampling clocks.

An embodiment of the present invention further provides an asynchronous data transmission system, including: a signal synchronization module and a data latch module, and the signal synchronization module and the data latch module are connected;

The signal synchronization module is configured to obtain a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge;

The data latching module is configured to latch signals according to the characteristic value and the first multiplexed data, The latched data signal indicated by the first multiplexed data latch signal is latched.

Optionally, the data latching module includes a first register, the first register is configured to acquire a first data read signal, and select the first data from the latched data signal according to the first data read signal. A plurality of data read read data indicated by the latch signal outputs the read data.

Optionally, the signal synchronization module includes: a second register and a third register;

The second register is configured to use a first sampling clock to perform signal synchronization processing on the first synchronization control signal to obtain a second synchronization control signal;

The third register is configured to receive the second synchronization control signal input by the second register, and perform signal synchronization processing on the second synchronization control signal by using a first sampling clock to obtain a third synchronization control signal.

Optionally, the signal synchronization module further includes: a fourth register, a fifth register, and a sixth register, wherein the fourth register, the fifth register, and the sixth register respectively input a second sampling clock;

The fourth register is configured to adopt a second sampling clock, and perform signal synchronization processing on the fourth synchronization control signal to obtain the first synchronization control signal;

The fifth register is configured to use a second sampling clock to perform signal synchronization processing on the second multiplexed data latch signal to obtain the first multiplexed data latch signal;

The sixth register is configured to perform a signal synchronization process on the second data read signal by using a second sampling clock to obtain the first data read signal.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the above method.

Compared with the related art, the embodiment of the present invention includes: acquiring a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge; and according to the feature value and the first multiplexed data latch signal, The latched data signal indicated by the first multiplexed data latch signal is latched. The above technical solution realizes that the setup and hold time of the asynchronous processing meets the sampling requirement, determines the reliable transmission of the multi-way asynchronous data bus, and does not need to confirm the handshake signal, and reduces the processing delay of the handshake handshake method. In turn, the processing speed of the multi-way asynchronous data bus transmission is improved.

Other aspects will be apparent upon reading and understanding the drawings and detailed description. (Other aspects will be appreciated upon reading and understanding the attached figures and detailed description)

BRIEF abstract

1 is a schematic flowchart of an asynchronous data transmission method according to an embodiment of the present invention;

2 is a schematic structural diagram of an asynchronous data transmission system according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an asynchronous data transmission system according to another embodiment of the present invention.

Preferred embodiment of the invention

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.

The steps illustrated in the flowchart of the figures may be executed in a computer system such as a set of computer executable instructions. Also, although logical sequences are shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than the ones described herein.

The asynchronous data transmission method provided by the embodiment of the present invention can be specifically applied to the asynchronous data transmission in the chip, and the chip can be a chip such as an FPGA. The asynchronous data transmission method provided by this embodiment may be specifically implemented by an asynchronous data transmission system, which may be integrated in a chip, and the asynchronous data transmission system may be implemented by using software and/or hardware. The asynchronous data transmission method provided in this embodiment will be described in detail below.

FIG. 1 is a schematic flowchart of an asynchronous data transmission method according to an embodiment of the present invention. As shown in FIG. 1 , an execution body of the method in this embodiment may be an asynchronous data transmission system. The method comprises the following steps:

Step 101: Acquire a feature value of the first synchronization control signal.

In this embodiment, the feature value includes a rising edge or a falling edge.

Step 102: Latch the latched data signal indicated by the first multiplexed data latch signal according to the feature value and the first multiplexed data latch signal.

The applicable scenario of this embodiment is when the data terminal that initiates the request by the transmitting end is transmitted to the output data bus.

In this embodiment, the first multiplexed data latch signal mux1 is sampled according to the eigenvalue sync_edge, so that the first multiplexed data latch signal mux1 can be stabilized, thereby determining that the multi-byte bit type data sampling satisfies the setup time and The time requirement is maintained to determine the correctness of the sampling of the first multiplexed data latch signal mux1, wherein the first multiplexed data latch signal mux1 is a multi-byte bit signal.

In this implementation, by acquiring an eigenvalue of the first synchronization control signal, the eigenvalue includes a rising edge or a falling edge; and the first multiplexed data according to the eigenvalue and the first multiplexed data latch signal The latched data signal indicated by the latch signal is latched, which realizes the sampling requirement of the setup and hold time during the asynchronous processing, determines the reliable transmission of the multi-way asynchronous data bus, and does not need to confirm the handshake signal, thereby reducing the handshake processing. The method delays the processing of the handshake signal, which in turn increases the processing speed of the multi-way asynchronous data bus transmission.

Optionally, after the step 102, the method may further include:

Obtaining a first data read signal;

Selecting, according to the first data read signal, read data indicated by the first multiplexed data latch signal from the latched data signals;

The read data is output.

Optionally, the second data read signal is subjected to signal synchronization processing by using the second sampling clock to obtain the first data read signal.

That is, the multiple asynchronous data buses data_bus[1] to data_bus[N] (where N is an integer representing N different data buses) are selected and latched under the first sampling clock clk_r, waiting for the first data After the read signal read_en1 is valid, the latched data data_bus1 is output through the first register. The first data read signal maintains a periodic delay of at least three of the second sampling clocks.

Optionally, on the basis of the foregoing embodiment, before step 102, the method may further include:

Optionally, the first synchronization control signal sync1 is used to perform two-shot synchronous sampling on the first synchronization control signal sync1, and the second synchronization control signal sync2 and the third synchronization control signal sync3 respectively generated are used to effectively reduce the asynchronous clock domain. The production of metastable state. Then, logic processing is performed, that is, the combination logic acquires the feature value sync_edge of the first synchronization control signal sync1, and when the sync_edge is valid, the first data bus latch signal latch_en is generated in cooperation with the second multiple data latch signal mux1, but When latching, the value of the second multiplexed data latch signal mux1 should be kept unchanged to ensure the setup time and the hold time, and to ensure reliable sampling of the asynchronous second multiplexed data latch signal mux1 data, wherein the first The multiplexed data latch signal maintains a periodic delay of at least two of said second sampling clocks.

Optionally, before acquiring the feature value of the first synchronization control signal in step 101, the method further includes:

2 is a schematic structural diagram of an asynchronous data transmission system according to an embodiment of the present invention, and FIG. 3 is a schematic structural diagram of an asynchronous data transmission system according to another embodiment of the present invention. As shown in FIG. 2 and FIG. 3, the asynchronous data transmission system of this embodiment is shown in FIG. The method includes: a signal synchronization module and a data latch module, and the signal synchronization module and the data latch module are connected;

The signal synchronization module is configured to obtain a feature value of the first synchronization control signal Sync_edge, the feature value includes a rising edge or a falling edge;

The data latching module is configured to latch the latched data signal indicated by the first multiplexed data latch signal according to the characteristic value and the first multiplexed data latch signal.

Optionally, the data latch module may latch the latched data signal indicated by the first multiplexed data latch signal according to the eigenvalue and the first multiplexed data latch signal, that is, the multiple asynchronous data bus data_bus [1] Select and latch to the data bus data_bus[N] (where N is an integer representing N different data buses).

In this implementation, by acquiring an eigenvalue of the first synchronization control signal, the eigenvalue includes a rising edge or a falling edge; and the first multiplexed data according to the eigenvalue and the first multiplexed data latch signal The latched data signal indicated by the latch signal is latched. The asynchronous sampling process meets the sampling requirements, and the reliable transmission of the multi-way asynchronous data bus is determined. At the same time, the handshake signal is not needed, and the processing delay of the handshake handshake method is reduced, thereby improving the processing delay. The processing speed of multi-channel asynchronous data bus transmission.

The data latching module includes a first register, the first register is configured to acquire a first data read signal, and select the first multiplexed data from the latched data signal according to the first data read signal The read data indicated by the latch signal is output, and the read data is output.

The second register is set to adopt a first sampling clock, and the first synchronization control signal sync1 is subjected to signal synchronization processing to obtain a second synchronization control signal sync2;

The third register is configured to receive the second synchronization control signal sync2 input by the second register, and perform signal synchronization processing on the second synchronization control signal by using a first sampling clock to obtain a third synchronization control signal. Sync3.

On the basis of the foregoing embodiment, the signal synchronization module further includes: a fourth register, a fifth a register and a sixth register, wherein the fourth register, the fifth register, and the sixth register respectively input a second sampling clock;

The fourth register is set to use a second sampling clock, and the fourth synchronization control signal sync is subjected to signal synchronization processing to obtain the first synchronization control signal sync1;

The fifth register is set to use a second sampling clock to perform signal synchronization processing on the second multiplexed data latch signal mux to obtain the first multiplexed data latch signal mux1;

The sixth register is configured to perform a signal synchronization process on the second data read signal read_en by using a second sampling clock to obtain the first data read signal read_en1. Optionally, the processing data read signal synchronized by the sixth register may also adopt a second sampling clock, and perform synchronization processing through the seventh register to obtain a first data read signal.

It should be noted that the first multiplexed data latch signal maintains a periodic delay of at least two of the second sampling clocks;

The embodiments disclosed in the present application are as described above, but the description is only for the purpose of understanding the present application, and is not intended to limit the present application.

One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium, such as on a corresponding hardware platform (eg, The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.

Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.

The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.

Each device/function module/function unit in the above embodiment is implemented in the form of a software function module. And when sold or used as a stand-alone product, it can be stored on a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Industrial applicability

The above technical solution realizes that the setup and hold time of the asynchronous processing meets the sampling requirement, determines the reliable transmission of the multi-way asynchronous data bus, and does not need to confirm the handshake signal, and reduces the processing delay of the handshake handshake method. In turn, the processing speed of the multi-way asynchronous data bus transmission is improved.

Claims

An asynchronous data transmission method includes:

Obtaining a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge of the first synchronization control signal;

And latching the latched data signal indicated by the first multiplexed data latch signal according to the characteristic value and the first multiplexed data latch signal.
The method of claim 1 further comprising:

And after the latched data signal indicated by the multiplexed data latch signal is latched according to the characteristic value and the multiplexed data latch signal, acquiring a first data read signal;

Selecting, according to the first data read signal, read data indicated by the first multiplexed data latch signal from the latched data signals;

The read data is output.
The method of claim 2, the method further comprising:

Before the latched data signal indicated by the multiplexed data latch signal is latched according to the feature value and the multiplexed data latch signal, the first synchronization clock is used to perform at least the first synchronization control signal 2 times signal synchronization processing, obtaining a second synchronization control signal and a third synchronization control signal;

The second synchronization control signal and the third synchronization control signal are logically processed to obtain a feature value of the first synchronization control signal.
The method of claim 3, further comprising:

Before acquiring the feature value of the first synchronization control signal, using the second sampling clock, performing signal synchronization processing on the fourth synchronization control signal to obtain the first synchronization control signal; and/or

Using the second sampling clock, performing signal synchronization processing on the second multiplexed data latch signal to obtain the first multiplexed data latch signal; and/or

Using the second sampling clock, the second data read signal is subjected to signal synchronization processing to obtain the first data read signal.
The method of claim 4 wherein said first multiplexed data latch signal maintains a periodic delay of at least two of said second sampling clocks;

The first data read signal maintains a periodic delay of at least three of the second sampling clocks.
An asynchronous data transmission system includes: a signal synchronization module and a data latch module;

The signal synchronization module is configured to obtain a feature value of the first synchronization control signal, where the feature value includes a rising edge or a falling edge;

The data latching module is configured to latch the latched data signal indicated by the first multiplexed data latch signal according to the characteristic value and the first multiplexed data latch signal.
The system of claim 6 wherein said data latching module comprises a first register,

The first register is configured to acquire a first data read signal, and select, according to the first data read signal, read data indicated by the first multiplexed data latch signal from the latched data signal, and output the Read the data.
The system of claim 7 wherein said signal synchronization module comprises: a second register and a third register;

The second register is configured to use a first sampling clock to perform signal synchronization processing on the first synchronization control signal to obtain a second synchronization control signal;

The third register is configured to receive the second synchronization control signal input by the second register, and perform signal synchronization processing on the second synchronization control signal by using a first sampling clock to obtain a third synchronization control signal.
The system of claim 8 wherein said signal synchronization module further comprises: a fourth register, a fifth register, and a sixth register,

The fourth register, the fifth register, and the sixth register are respectively set to input a second sampling clock;

The fourth register is configured to adopt a second sampling clock, and perform signal synchronization processing on the fourth synchronization control signal to obtain the first synchronization control signal;

The fifth register is set to adopt a second sampling clock to latch the second multiplexed data signal Performing signal synchronization processing to obtain the first multiplexed data latch signal;

The sixth register is configured to perform a signal synchronization process on the second data read signal by using a second sampling clock to obtain the first data read signal.
The system of claim 9 wherein

The first multiplexed data latch signal maintains a periodic delay of at least two of the second sampling clocks;

The first data read signal maintains a periodic delay of at least three of the second sampling clocks.
A computer storage medium having stored therein computer executable instructions for performing the method of any one of claims 1 to 5.