WO2016078506A1

WO2016078506A1 - Method and apparatus for asynchronously receiving serial data

Info

Publication number: WO2016078506A1
Application number: PCT/CN2015/093138
Authority: WO
Inventors: 刘伯安
Original assignee: 刘伯安
Priority date: 2014-11-18
Filing date: 2015-10-28
Publication date: 2016-05-26
Also published as: CN105893291B; CN105893291A

Abstract

In a method and an apparatus provided in the present invention, serial data is received in an asynchronous manner, thereby lowering requirements for a frequency difference and stability of a transmit clock and a receive clock, so that serial data, comprising synchronous serial data and asynchronous serial data, of any physical layer protocols can be universally received without distinguishing; only amplitude limiting, amplification, and delay need to be performed on a received serial data signal, there is no complex analog circuit, the circuit structure is simple, reliable, and easy to implement, and the maximum clock frequency of a trigger circuit is the maximum data transmission rate; the present invention has low cost, high performance, and universality, so that the present invention can be widely used for high-speed transmission of data.

Description

Method and device for asynchronously receiving serial data

Technical field

The present invention generally relates to an asynchronous receive (0001) method and apparatus for serial data (0000), such as a method and apparatus for receiving asynchronous serial data (0002), a method and apparatus for receiving synchronous serial data (0003), and the like, including a computer A method and apparatus for receiving serial data of a system memory interface, an external bus interface, an external device interface, a wired network interface, a fiber optic network interface, and the like. In particular, the present invention relates to a method and apparatus for asynchronously receiving (0001) high speed serial data (0000), based on which a low cost, high performance, single or multi-channel, single-ended drive or A communication interface device for synchronous serial data or asynchronous serial data such as differential driving generally meets the demand for high-speed data transmission.

Background technique

Serial data communication is one of the basic means to reduce the cost of data transmission. Early serial data communication is mainly based on low-speed asynchronous communication (0004), and the influence of the frequency difference between the transmission clock and the receiving clock is small, in order to increase the data transmission rate. Simultaneous transmission of clock and data synchronization (0005) is adopted, which increases the data transmission rate but increases the cost, and is difficult to meet the higher-speed data transmission requirements. Clock Data Recovery technology enables synchronous communication (0005) The synchronous transfer clock is no longer needed. This method embeds the clock into the synchronous serial data (0003) at the data transfer end, recovers the clock from the synchronous serial data (0003) at the receiving end and demodulates the serial with it. The data (0000) makes the data transmission rate higher and can be transmitted further, but it needs to continuously transmit data to keep the clock data recovery circuit in operation. The multi-bit analog-to-digital converter sampling at the double data transmission rate is also the receiving string. One of the methods of row data (0000).

The present invention provides a method and apparatus for asynchronously receiving (0001) high speed serial data (0000), which can receive either asynchronous serial data (0002) or synchronous serial data (0003).

DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in detail with reference to the embodiments of the present invention,

1 is a timing diagram of serial data (0000) transmission and reception and a multi-stage delay generation intermediate clock (0340) and intermediate data of a preferred example receive clock (0310) and receive data (0314) implemented in accordance with the method of the present invention. Schematic diagram of the method and apparatus of (0344).

2 is a diagram showing a preferred embodiment of the method according to the present invention based on a method of falling stretch (0440), rising stretch (0442), intermediate data (0344) generating a falling delay (0450), rising delay (0452), and data delay (0454). And device schematic.

3 is a block diagram of a method for sampling a falling delay (0450), a rising delay (0452), and a data delay (0454) using a sample shift register (0500) positive and negative phase intermediate clock (0340) in accordance with a preferred embodiment of the method of the present invention. And device schematic.

4 is a preferred embodiment of a method implemented in accordance with the present invention to generate a falling spread based on received data (0314) (0440), method and apparatus for ascending the broadening (0442) and matching data (0444).

5 is a schematic diagram of a method and apparatus for determining the flip timing (0602) of a preferred example positive and negative phase intermediate clock (0340) sampled signal flip (0120) output implemented in accordance with the method of the present invention.

6 is a timing diagram of signal timing for a preferred example positive and negative phase intermediate clock (0340) sampled signal flip (0120) output flip timing (0602) discrimination implemented in accordance with the method of the present invention.

7 is a timing window (0700) determination method and signal timing diagram of a preferred example intermediate clock (0340) positive sequence sampling (0530) implemented in accordance with the method of the present invention.

8 is a timing window (0700) determination method and signal timing diagram of a preferred example intermediate clock (0340) inverse sequential sampling (0532) implemented in accordance with the method of the present invention.

9 is a schematic diagram of a general purpose computer central processing unit in accordance with a preferred embodiment of the method of the present invention.

Figure 10 is a schematic illustration of a field programmable gate array chip in accordance with a preferred embodiment of the method of the present invention.

11 is a schematic diagram of a serial data interface memory chip in accordance with a preferred embodiment of the method of the present invention.

12 is a schematic diagram of a preferred embodiment of a DRAM/SDRAM or SRAM or FLASH memory and module controller implemented in accordance with the method of the present invention.

13 is a schematic diagram of an interface controller of a computer external device based on a USRT or USRT physical layer, in accordance with a preferred embodiment of the method of the present invention.

Figure 14 is a schematic illustration of a preferred embodiment of a data transfer relay device employing a USRT or UART physical layer implemented in accordance with the method of the present invention.

15 is a schematic diagram of a preferred embodiment of a system domain network switch based on a USRT or UART physical layer protocol implemented in accordance with the method of the present invention.

16 is a schematic diagram of a computer network switch and/or router based on a USRT or UART physical layer protocol, in accordance with a preferred embodiment of the method of the present invention.

17 is a schematic diagram of a preferred example of a communication network switch and/or router based on a USRT or UART physical layer protocol implemented in accordance with the method of the present invention.

references

[1]. "A universal method and device for receiving serial data", Chinese invention patent application, application number 201410313411.6, application date July 3, 2014.

detailed description

First, the description of the agreement

In the description of the method of the invention, there are the following conventions:

1. Use L and H to indicate the low level and high level of the digital signal, respectively;

2. Use x:y to represent all integer values from x to y;

3. Use Name (P/N) to represent a digital signal with the name Name, Name (N/P) for the inverted signal of Name (P/N), and NameP and NameN for the positive and negative phase signals, respectively. Sometimes, the signal is only represented by Name, and the signal can be either a single-ended signal (0100) or a double-ended differential signal (0110), which is not distinguished in the description;

4. Signal flipping (0120, transition) refers to a rapid change of a digital signal from a low level L to a high level H or from a high level H to a low level L, from a high level H to a low level L The signal flip is a fall flip (0130, fall transition), and the signal flip from a low level L to a high level H is a rise flip (0140, rise transition);

5. The signal width (0150) refers to the duration of a digital signal at a low level L or at a high level H;

6. The signal period (0160) refers to the time interval between two adjacent rising flips (0130) of a digital signal or two adjacent falling flips (0140);

7. The name of a particular meaning is indicated by a boldface (label) at the beginning of each paragraph, and then the name of that particular meaning is indicated in bold in the same paragraph.

Second, asynchronous transfer

A method for transmitting asynchronous serial data (0002) is described in the reference [1] "Detailed Description of the Invention", "Method and Apparatus for Asynchronous Serial Data Transmission", which is repeated here and modified as follows:

A transmission channel (0200) transmits data in units of transmission frames (0210) starting with 1 start bit (0220) followed by a variable number of B content bits (0222), consisting of 1 stop bit ( 0224) End, any number of idle bits (0226), which may be zero, may be inserted between adjacent transmission frames, the effective signal levels of the start bit and the stop bit are different, and the effective signal levels of the idle bit and the stop bit are Similarly, if the start bit is active high, the stop bit and the idle bit are active low. If the start bit is active low, the stop bit and the idle bit are active high, and the signal of the transmission channel is valid. It can be a single-ended signal (0100) or a differential signal (0110).

The content of the B content bits (0222) in the transmission frame (2010) is arbitrary, and may be a flag bit (0230), a data bit (0232), a command bit (0234), a parity bit (0236), an alignment bit (0238), Switching bits (0240) and the like, for example, defining a 1-bit flag bit, the transmission frame (0210) is divided into a data frame without a command bit (0212) and a command frame without a data bit (0214), and others. The number of bits of the type content bit may be 0 or 1 or more, the content bit may be original data or a command, or may be a result of scrambling, encrypting, encoding, etc. processing the original data or command, and verifying the bit The data receiving end can discover the transmission error in real time, the alignment bit is a cyclical cycle plus a change alignment number (0250), and the data receiving end is used to align the assembled combined frame (0216), and the exchange bit is a target address within a specific range. (0252), enabling the switch to implement switched transport (0260) in a simple manner, and the destination address can be subdivided into multiple hierarchical addresses (0262) for multi-level switching (0264) transmission.

Multiple transmission channels (0200) can form a combined channel (0202), and the transmission frame (0210) transmitted simultaneously by multiple transmission channels of the combined channel has a delay difference (0254), so alignment measures (0256) are required. The entire transmission frames of the combined channel can be correctly combined into one combined frame (0216). Several alternative preferred alignment measures of the present invention are as follows:

1. Set a transmission delay (0256) for each transmission channel (0200) of the combined channel (0202) at the data transmission end to control and adjust each transmission channel in the combined channel for the period or half period of the transmission clock. The transmission delay makes the delay difference (0254) as small as possible. The data receiver needs to measure the delay difference and inform the data transmitter. The data receiver needs to take measures to ensure that the delay difference does not affect the correct combination of the combined packets.

2. At a determined or indeterminate time interval, the data transmitting end transmits an alignment command frame (0214) containing alignment bits (0238), and the data receiving end realigns the transmission in the data buffer according to the alignment bits after receiving the alignment command frame. Frame (2010).

The method of item 1 is applicable to the case where the transmission channel (0200) of the combined channel (0202) is concentrated on a single chip, and the method of item 2 is applicable to the case where the transmission channel of the combined channel is distributed over a plurality of chips.

At regular intervals when data is continuously transmitted, a certain number of idle bits (0226) are inserted between the transmission frames (0210), and devices that perform relay transmission, such as repeaters (0270, repeater), switches (0272, switch) The data buffer of the receiving device with a lower clock frequency can be prevented from overflowing by increasing or decreasing the number of idle bits to accommodate the difference between the transmit clock of the data source (0280) and the receive clock of the data target (0282). .

Third, the signal delay

The upper part of Fig. 1 is a timing diagram of the serial data (0000) signal. For the sake of simplicity, the serial data in the figure is flipped once every transmission period (0302) Ttx, that is, the low level L and the high level H are alternately transmitted. The transmission data (0304) TD (P/N) is not indicated with respect to the delay of the transmission clock (0300) TK (P/N), and the reception data (0314) RD (P/N) is relative to the TK (P/N). The delay is also not indicated. Due to distortion during transmission and reception, the time between two inversions of the received data is no longer an integer multiple of Ttx. With Ttx as a reference, there is a maximum distortion time (0320) td, Ttx-td*2 The opening time of the eye diagram (Eye Diagram Pattern) displayed by the measuring instrument. The receiving clock (0310) is RK (P/N), the setup time (0332, set time) of the sampling flip-flop (0330, Flip-Flop) is ts, and the hold time (0334, hold time) is th, then the received data is received. The correct reception condition is that the reception period (0312) of the reception clock (0310) Trx is the same as Ttx and is always sampled within the sample window interval located in FIG.

The middle part of Figure 1 is a timing diagram of sampling serial data (0000) with a sampling flip-flop (0330) at the receiving end. For the sake of simplicity, the received data (0314) SI (P/N) in the figure is transmitted every 2 transmission cycles ( 0302) Flip once, that is, alternately transmit two low-level L and two high-level H. Only the case of unstable sampling is given in the figure, that is, the flipping of the received data SI (P/N) is relative to the receiving clock. (0310) The CK (P/N) sampling flip is within the interval of the advance setup time (0332) ts and the hysteresis hold time (0334)th. The receiving period (0112) of the receiving clock CK (P/N) is approximately equal to Trx and Ttx. Due to the unstable sampling, the output RUD (P/N) of the sampling flip-flop (0330) is not the result of correct sampling, and lasts for about 2 The continuous level of Ttx of the transmission period (0302) is unstablely sampled into a continuous level of one or two or three reception periods Trx, which means that the continuous level of about one transmission period Ttx may have no sampling output, RDD(P/N) is the sampling trigger output that is sampled simultaneously with CK(N/P). Since the sampling flip of CK(N/P) is in the stable region of SI(P/N), RDD(P/N) It is the correct sampling result for SI (P/N).

The lower part of FIG. 1 is based on the reception clock (0310) CK (P/N) and the number of receptions in the method and apparatus of the present invention. According to (0314) SI (P/N), the intermediate clock (0340) DK<0:N-1> and the intermediate data (0344)DI<0:N-1> are respectively generated, and the delay series (0342)N Is the number of stages of the delay component that produces the intermediate clock and intermediate data.

The receiving clock (0310) CK(P/N) is obtained by the N-stage delay unit dK<0:N-1>, and the N-phase intermediate clock (0340) DK(P/N)<0:N-1>, dK<N is obtained. > Make the load of dK<N-1> the same as the load of the previous stage delay component, dK<0:N-1> also indicates the delay time of the corresponding delay component, and the clock average of dK<0:N-1> is represented by dKa The delay (0346) value, dK<0:N-1> are approximately equal to dKa, and the time difference of DK<N> and CK is represented by the intermediate clock time difference (0347) sKa, then sKa≌(N+1)*dKa, using the mode The digital converter measures the sKa to obtain an approximation of dKa.

The received data (0314) SI(P/N) is obtained by the N-stage delay unit dM<0:N-1>, and the N-phase intermediate data (0344)DI(P/N)<0:N-1>, dM<N is obtained. > Make the load of dM<N-1> the same as the load of the previous stage delay component, dM<0:N-1> also indicates the delay time of the corresponding delay component, and dMa represents the average data of dM<0:N-1> The delay (0348) value, dM<0:N-1> are approximately equal to dMa, and the time difference of DI<N> and SI is represented by the intermediate data time difference (0349) sMa, then sMa≌(N+1)*dMa, using the mode The digital converter measures sMa to get an approximation of dMa.

The delay values of dK<0:N-1> and dM<0:N-1> are both greater than or equal to 0, and the clock average delay (0346)dKa and the data average delay (0348)dMa can both be 0 but not both. The delay value can be a fixed value or a variable value.

The delay of dK<0:N> and dM<0:N> may be generated by a preferred method such as wiring delay, delay line delay, cascade circuit delay, etc. Delay dK<0:N> may also be delayed lock loop (Delay Lock) A preferred method such as Loop), cascade latch (Latch), cascade flip-flop (Flip Flop) or the like is generated. In general, the frequency of the local clock is the same as the frequency of the receiving clock (0310). If the delay of the receiving clock is generated by a cascade latch (Latch) or a cascade flip (Flip Flop), the frequency of the local clock must be Times the frequency of the receiving clock.

Fourth, pulse broadening

Since the phase difference between the receiving clock (0310) and the received data (0314) varies randomly, when the received data is at a low level L or a high level H for only one transmission period (0302), the sampling trigger cannot be guaranteed (0330). A flipping of the received data can be acquired. Figures 4 and 2 illustrate a preferred example method and apparatus of the present invention that produces a stretched pulse (0490) of at least about two transmission cycles (0302) based on the received data, ensuring that A rollover of each received data is collected.

In FIG. 4, the sampling latch (0400, latch) 0410/0:1 constitutes a ring-shaped two-divider, and the received data (0314) SI (P/N) is divided by a spread-width pulse (0490). The output of the sampling latch 0410/0 is the falling spread (0440) SD (P/N), its flip corresponds to the falling flip of SI (P/N) (0130), and the output of the sampling latch 0310/1 is the rising spread. (0442) SU(P/N) whose flip corresponds to the rising flip of SI(P/N) (0140), and the SD (P/N) and SU(P/N) flips are inverted relative to SI(P/N) The delay time is the enable delay (0402) tpd time of the sampling latch. The output of the sample matcher (0420, match) 0430 is the matching data (0444) SM(P/N), which is flipped with SI (P/N). The flipping is the same but delays the sampling latch's enable delay (0402) tpd time, which is used to delay match when the data average delay (0348)dMa is 0, so that SM(P/N) can be used for subsequent The component samples the received data.

In Figure 2, the stretched pulse (0490) becomes the stretch delay (0492) via the sample latches (0400) 0460/0:N and 0470/0:N, and the output of the sample latch (0400) 0460/0:N is Falling delay (0450) DD(P/N)<0:N>, which flips respectively to the falling flip (0130) of DI(P/N)<0:N> but the delay enable delay (0302) tpd time, The output of the sampling latch (0400) 0470/0:N is the rising delay (0452) DU(P/N)<0:N>, and its flipping corresponds to the rising flip of DI(P/N)<0:N> respectively. (0140) but the delay enable delay (0302) tpd time, the output of the sample matcher (0420) 0480/0:N-1 is the data delay (0454) DM(P/N)<0:N-1>, The flip is the same as the flip of DI(P/N)<0:N-1> but the delay enable delay (0302) tpd time, the effect is to perform delay matching when the data average delay (0348)dMa is not 0. DM(P/N)<0:N-1> is used for subsequent component sampling to receive data (0314).

Fifth, signal sampling

Figure 3 is a sample shift register (0500) composed of a sampling flip-flop (0330), which samples the falling delay (0450) DD (P/N), rising delay (0452) DU (P/N), and data delay (0454). DM (P / N) method and device schematic, sampling flip-flop 0510 / 0: M-1 sample shift register, with the intermediate clock (0340) down flip (0130) sampling, sampling trigger 0520 / 0 The sampling shift register consisting of M-1 is sampled by the rising flip (0140) of the intermediate clock (0340), M is the sampling level (0502), that is, the number of stages of the sampling shift register, and the sampling shift register is serialized. And shift the register.

The lowercase character x in the signal identification name in Fig. 3 is D or U or M, respectively indicating that the sampled signal is a falling delay (0450) DD(P/N)<n>, a rising delay (0452) DU (P/N ) <n>, data delay (0454) DM (P/N) <n>, and the like.

The <n> in the signal identification name in Fig. 3 indicates the serial number of the sampled signal, and its range and order of change are 0 to N-1. When the data average delay (0348)dMa is 0, the falling delay (0450) DD (P) /N)<0:N-1> are both the falling spread (0440) SD (P/N), the rising delay (0452) DU(P/N)<0:N-1> are the rising stretch (0442) SU (P/N), data delay (0454) DM(P/N)<0:N-1> are all matching data (0444)SM(P/N), etc., where N is the delay series (0342) .

The <k> in the signal identification name in Fig. 3 indicates the serial number of the intermediate clock (0340), and its variation range is 0 to N-1, and the order of change may be 0 to N-1 or N-1 to 0, when the clock averages When the delay (0346) dKa is 0, the intermediate clock DK(P/N)<0:N-1> is CK(P/N), where N is the delay series (0342). If the order of change of k is 0 to N-1, it is the Foreward Sequence sample (0530). If the order of change of k is N-1 to 0, it is the Backward Sequence sample (0532). Sequential sampling means that the intermediate clock number and the sequence of the sampled signals are changed in the same order. The reverse order sampling means that the intermediate clock number and the sequence of the sampled signals are reversed.

The output of the sample shift register (0500) 0510/0:M-1 and 0520/0:M-1 is the negative edge output (0530) dQx<0:N-1,0:M-1> and the positive edge output ( 0532) uQx<0:N-1,0:M-1>, N is the delay series (0342), M is the sampling series (0502), lowercase character x is D or U or M, respectively representing the falling Delay (0450) DD(P/N)<0:N-1> sample output negative edge falling (0540) dQD<0:N-1,0:M-1> and positive edge falling (0542)uQD<0: N-1,0:M-1>, the rising edge of the sampling output of the rising delay (0452) DU(P/N)<0:N-1> (0550) dQU<0:N-1,0:M -1> and positive edge rising (0552) uQU<0:N-1,0:M-1>, data delay (0454) DM(P/N)<0:N-1> sampling output negative edge data ( 0560) dQM<0: N-1, 0: M-1> And positive edge data (0562) uQM<0:N-1,0:M-1>.

In the following description, collectively referred to as negative edge falling (0540), positive edge falling (0542), negative edge rising (0550), positive edge rising (0552) is the broadened output (0570), collectively referred to as negative edge falling (0540) and negative. The rising edge (0550) is the negative edge broadening (0572), the collective positive edge falling (0542) and the positive edge rising (0552) are the positive edge broadening (0574), collectively referred to as negative edge data (0560) and positive edge data (0562) for data output. (0580).

Six, time sorting

A signal flip (0120) is asynchronously sampled by the falling flip (0130) and the rising flip (0140) of the intermediate clock (0340), and the flip time (0600) of the negative edge output (0530) and the positive edge output (0532) is halfway. The cycle of the clock but the flip timing (0602) varies randomly. FIG. 5 is a schematic diagram of a preferred method and apparatus for determining the timing of each flip of the present invention. The negative edge output (0530) and the positive edge output (0532) use a sampling trigger (0330) 0610. :0613 is mutually sampled, 0610 is the device that outputs dQx<n,t> on the falling edge of the positive edge of the output uQx<n,t>, and its output is dFx<n,t>, and 0611 is the positive edge output uQx<n, The rising edge of the t> sampling negative edge output dQx<n, t> device, its output is dRx<n, t>, 0612 is the negative edge output dQx<n, t> falling edge sampling positive edge output uQx<n, The device of t>, whose output is uFx<n,t>, is the device with negative edge output dQx<n, t> rising edge sampling positive edge output uQx<n,t>, the output of which is uRx<n,t >.

Table 1, sampling timing status of signal flipping

6 is a schematic diagram of signal timing of the method and apparatus of FIG. 5. In FIG. 6, the light gray area determines the sampling output flip timing of the positive and negative phase intermediate clocks (0340) when determining Mx<n> falling and flipping (0130). The time zone of 0602), the dark gray zone is a time zone for determining the sampling output inversion timing (0602) of the positive phase and the negative phase intermediate clock (0340) when Mx<n> is raised and inverted (0140), and Table 1 is a discriminating state list. Where L represents a low level, H represents a high level, and x represents an arbitrary level.

Seven, time window

In the case where the positive and negative phase intermediate clock (0340) is known to sample the output flip timing (0602), the sampled signal can be inverted (0120) time to determine the time window (0700) of the intermediate clock (0340) half cycle. In the range, the falling delay (0450) and the rising delay can be further determined by the multiphase delay intermediate clock (0340) positive and negative phase sampling multiphase delay falling delay (0450) and rising delay (0452). (0452) Signal Flip (0120) The settling time (0332) and hold time (0334) of the sampling flip-flop (0330) limits the minimum value of the time window over a smaller time window.

7 and FIG. 8 are schematic diagrams showing the method and signal timing of determining the time window (0700) of the present invention, where t is 1, lowercase x is D or U, lowercase e is d or u, and the intermediate clock (0340) DK< n>Sampling falling delay (0450) MD<n-3:n+3> or rising delay (0452) MU<n-3:n+3> output flip timing (0602) are both dQx<n,t>/ uQx<n,t> or uQx<n,t>/dQx<n,t>, regardless of the effect of device delay, only consider the actual result of signal flipping and sampling, the XXX area in the figure is the sampled signal Mx <n-3:n+3> Possible flip area (0710).

7 is a timing window (0700) determination method and signal timing diagram of the intermediate clock (0340) positive sequential sampling (0530), and the following is a description of the timing of FIG. 7:

1, the clock average delay (0346) dKa is Trx / 3;

2. The average data delay (0348) dMa is Trx/6;

3. The possible flip region of Mx<n> (0710) is a Trx/2 time interval in which DK<n> is high level H or low level L, and the flipping region (0602) inferred flip region and Mx<n > possible flip areas overlap;

4. The possible flip region (0710) of Mx<n-1> is a Trx/2 time interval in which a certain DK<n-1> is a high level H or a low level L, and a flipping region (0602) inferred flip region Leading dKa*1, Mx<n-1> possible flipping area leads dMa*1, flipping time (0602) inferred flipping area overlaps with Mx<n-1> possible flipping area about Trx*2/3;

5. Mx<n-2> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n-2> is a high level H or a low level L, and the inversion region of the inversion timing (0602) is inferred. Leading dKa*2, Mx<n-2> possible flipping area leads dMa*2, flipping time (0602) inferred flipping area overlaps with Mx<n-2> possible flipping area by about Trx*1/3;

6. Mx<n-3> The possible flip region (0710) is a Trx/2 time interval in which a certain DK<n-3> is a high level H or a low level L, and a flipping region (0602) inferred flip region Leading dKa*3, Mx<n-3> possible flipping area leads dMa*3, flipping time (0602) inferred flipping area overlaps with Mx<n-3> possible flipping area about Trx*0/3;

7. Mx<n+1> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n+1> is a high level H or a low level L, and a flipping region (0602) inferred flip region The lag is about dKa*1, Mx<n+1> the possible flip region lags about dMa*1, and the flip region (0602) infers that the flip region overlaps with the possible flip region of Mx<n+1> about Trx*2/3;

8. Mx<n+2> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n+2> is a high level H or a low level L, and the inversion region of the inversion timing (0602) is inferred. The hysteresis is about dKa*2, Mx<n+2> the possible inversion region is delayed by about dMa*2, and the inversion region of the inversion timing (0602) is overlapped with the possible inversion region of Mx<n+2> by about Trx*1/3;

9. Mx<n+3> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n+3> is a high level H or a low level L, and the inversion region of the inversion timing (0602) is inferred. Lag about dKa*3, Mx<n+3> The possible flip region lags about dMa*3, and the toggle region (0602) inferred flip region overlaps with Mx<n+3> possible flip region by about Trx*0/3.

8 is a timing window (0700) determination method and signal timing diagram of the intermediate clock (0340) reverse sequential sampling (0532), and the following is a description of the timing of FIG. 8:

1. The average clock delay (0346) dKa is Trx/18;

2. The average data delay (0348) dMa is Trx/9;

4. The possible flip region (0710) of Mx<n-1> is a Trx/2 time interval in which a certain DK<n-1> is a high level H or a low level L, and a flipping region (0602) inferred flip region The lag is about dKa*1, Mx<n-1> the possible flip region leads dMa*1, and the flipping time (0602) inferred flip region overlaps with Mx<n-1> possible flip region about Trx*2/3;

5. Mx<n-2> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n-2> is a high level H or a low level L, and the inversion region of the inversion timing (0602) is inferred. The hysteresis is about dKa*2, Mx<n-2> the possible inversion region leads dMa*2, the inversion time (0602) inferred flip region overlaps with the possible flip region of Mx<n-2> about Trx*1/3;

6. Mx<n-3> The possible flip region (0710) is a Trx/2 time interval in which a certain DK<n-3> is a high level H or a low level L, and a flipping region (0602) inferred flip region The hysteresis is about dKa*3, Mx<n-3> the possible inversion region leads dMa*3, the inversion time (0602) inferred flip region overlaps with Mx<n-3> possible flip region about Trx*0/3;

7. Mx<n+1> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n+1> is a high level H or a low level L, and a flipping region (0602) inferred flip region Leading dKa*1, Mx<n+1> possible flip region lags about dMa*1, flipping time (0602) inferred flip region overlaps with Mx<n+1> possible flip region about Trx*2/3;

8. Mx<n+2> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n+2> is a high level H or a low level L, and the inversion region of the inversion timing (0602) is inferred. Leading dKa*2, Mx<n+2> possible flipping region lags about dMa*2, flipping time (0602) inferred flip region overlaps with Mx<n+2> possible flip region about Trx*1/3;

9. Mx<n+3> The possible inversion region (0710) is a Trx/2 time interval in which a certain DK<n+3> is a high level H or a low level L, and the inversion region of the inversion timing (0602) is inferred. Leading dKa*3, Mx<n+3> possible flipping region lags about dMa*3, and the flipping region (0602) inferred flip region overlaps with Mx<n+3> possible flip region by about Trx*0/3.

As can be seen from Fig. 7 and Fig. 8, the flipping timing (0602) of one phase clock sampling can infer that the time window (0700) is Trx/2, increasing the sampling output of the same flip timing of one phase, time window (0700) To narrow a time step (0720) dSa, the time step (0720) of the positive sequence sampling (0530) is dSa=abs(dKa-dMa), and the time step (0720) of the reverse order sampling (0532) is dSa. =dKa+dMa, available To narrow the time window (0700) to less than or equal to the dSa time range, the setup time (0332) and hold time (0334) of the sample trigger (0330) limits the minimum value of dSa. The maximum number of phases with the same flip timing (0602) sample output is the maximum number of phases (0730) dNa = floor (0.5 * Trx / dSa).

According to the flip timing (0602), the stretched output (0570) is divided into a negative edge output (0530) lead group and a positive edge output (0532) lead group, and the number of adjacent numbers is selected from the two, that is, the number of the same order (0760) is the largest. The minimum starting number is used as the negative edge criterion (0740) and the positive edge criterion (0742), and the starting sequence number is the same sequence number (0762) as the negative edge number (0750) and the positive edge number (0752), respectively.

The negative edge criterion (0740), the positive edge criterion (0742), the negative edge number (0750), and the positive edge number (0752) are the basis for determining the time window (0700), the negative edge number (0750) and the positive edge number ( The average value of 0752) is the mean value of the serial number (0754), the difference between the mean value of the serial number is the difference of the serial number (0756), the average value of the squared difference (0756) squared or the absolute value is the variance of the serial number (0758), the mean of the serial number (0754) ), the difference of the serial number (0756), the variance of the serial number (0758), etc. are the distortion criteria (0790) for determining the degree of signal distortion, and it is necessary to perform the discrimination result of the determined time window (0700) according to one or some of them. Correction, the serial number mean (0754) and the serial number variance (0758) can be selected by one or more data window widths to reflect the short-, medium-, and long-term distortion of the signal.

As can be seen from Fig. 7 and Fig. 8, in the negative edge criterion (0740) and the positive edge criterion (0742), the sampled signal corresponding to the smallest negative edge criterion (0740) and the positive edge criterion (0742) The sampling flip of the flip intermediate clock (0340) is close to Trx/2 time, so the corresponding data output (0580) is more likely to be the correct data (0770), the largest negative edge criterion (0740) and positive edge judgment According to (0742), the inverted sampling of the corresponding sampled signal inverted hysteresis intermediate clock (0340) is close to Trx/2 time, so the corresponding data output (0580) is also more likely to be correct data (0770). A preferred discriminating method is: if the negative edge criterion (0740) and the positive edge criterion (0742) are different in the same order number (0760), then the same order number (0760) is selected as the criterion output (0780), if negative According to the same number of orders (0760) along the criterion (0740) and the positive edge criterion (0742), the same sequence number (0762) is selected as the criterion output (0780), and a serial number selection (0782) and Phase selection (0784), phase selection determines the sampling result of the falling flip (0130) or rising flip (0140) of the intermediate clock. Also accordingly adding or subtracting a correction signal is determined according to the degree of distortion.

If the minimum number in the criterion output is selected as the serial number selection (0782), the phase selection (0784) selects the in-phase intermediate clock (0340), that is, the flip timing (0602) is the falling flip (0130) or rising of the intermediate clock (0340). If the sampling of the flip (0140) is advanced, select the falling flip (0130) or the rising flip (0140) of the intermediate clock (0340); if the maximum number in the selection criterion is selected as the serial number selection (0782), the phase selection (0784) Select the inverting intermediate clock (0340), that is, the flip timing (0602) is the falling flip (0130) or the rising flip (0140) lead of the intermediate clock (0340), then select the rising flip (0140) or falling of the intermediate clock (0340). Flip (0130).

The data output corresponding to the serial number selection (0782) and the phase selection (0784) is output as a data packet as the reception result of the serial data (0000), and the corresponding stretched output (0570) can be used as a trigger signal for the start and end of the data packet. It is also necessary to set a bit counter to give the number of bits of the data packet. The transmission frame (0210) of the asynchronous serial data (0002) receives the stretched output corresponding to the active level inversion of the received bit from the active bit of the stop bit (0224) or the idle bit (0226) to the active bit (0220). Flip start, The number of bits of a transmission frame is the number of content bits (0222) plus one start bit and one stop bit, so the generation of the end trigger signal requires the participation of the bit counter.

Eight, data reception

The basic method and apparatus of the present invention have been described above, and the following is a summary and further description of the method and apparatus for asynchronously receiving serial data of the present invention.

1. The local clock (0800) and the received data (0314) are input from the outside;

2. The local clock (0800) is directly used as the receiving clock (0310) or divided to generate the receiving clock. The receiving frequency (0312) is the same as the transmitting frequency (0302). If the receiving clock needs to be delayed, the delay level (0342) is N. The multi-stage delay component generates an N-phase intermediate clock (0340), the delay time of the delay components is greater than or equal to 0 and approximately equal, and the mean value thereof is the clock average delay (0346), and the delay can be caused by wiring delay, delay line delay, and cascade circuit delay. A preferred method such as a Delay Lock Loop is generated. The receiving clock can also be stepped through a cascade latch (Latch) or a cascade flip (Flip Flop) by a local clock whose frequency is several times the receiving frequency. The shift equalization method produces that the clock average delay is a fixed value or a variable value.

3. A widened pulse (0490) having a width of at least about two transmission cycles (0302) is generated based on the received data (0314), and if the received data is required to be matched data (0444) via the delay matching component, the flipping is aligned with the flipping of the stretched pulse. If the data needs to be received, the N-phase intermediate data (0344) is generated by the multi-stage delay component with the delay level (0342) being N. The delay time of the delay component is greater than or equal to 0 and approximately equal, and the mean value is the average data delay (0348). ), based on the intermediate data, a spread delay (0492) of N phase of at least about two transmission periods (0302) width is generated, and the delay time difference of the adjacent two-phase stretch delay (0492) is also a data average delay (0348), and the delay can be made by wiring. A preferred method of delay, delay line delay, cascade circuit delay, etc., produces that the data average delay is a fixed value or a variable value, and the N-phase intermediate data becomes a data delay (0454) via the delay matching component, causing its flip to be aligned with the rollover of the stretch delay. .

4. The average clock delay (0346) and the average data delay (0348) can be 0, but can be 0 at the same time. When the average clock delay is 0, the receiving clock (0310) is the intermediate clock (0340), that is, there is no need to generate the middle. When the clock has an average data delay of 0, the stretched pulse (0490) and the matched data (0444) are the stretched delay (0492) and the data delay (0454), respectively, that is, no spread delay and data delay are required;

5. The sampling shift register (0500) with the series of sampling stages (0502) is separately phase-sampled for the N-phase stretched delay (0492) and the N-phase data delay (0454), and the sampling intermediate clock (0340) is inverted and inverted ( 0130) and rising flip (0140) at the same time, get negative edge broadening (0572) and positive edge broadening (0574) and data output (0580), sampling can be positive sequential sampling (0530) or reverse sequential sampling (0532), positive sequential sampling It means that the intermediate clock number is the same as the sequence of the sampled signal sequence, and the reverse sequence sampling means that the intermediate clock number and the sequence of the sampled signal are reversed.

6. Let the negative edge broadening (0572) and the positive edge broadening (0574) of the same stretch width delay (0492) sample each other, and determine the flip timing (0602) of the two based on the sampling result, according to the flip timing. The stretched output (0570) is divided into a negative edge output (0530) lead group and a positive edge output (0532) lead group, and the number of adjacent numbers is selected from the two, that is, the number of the same order (0760) is the largest and the starting number is the smallest. As the negative edge criterion (0740) and the positive edge criterion (0742), the starting sequence number is the same sequence number (0762) as the negative edge number (0750) and the positive edge number (0752);

7. Calculate the mean number of the negative edge number (0750) and the positive edge number (0752) (0754), the variance of the serial number (0758), and the difference of the serial number (0756) as the distortion criterion (0790). One or more data can be selected. Window width calculation serial number mean (0754) and serial number variance (0758);

8. If the negative edge criterion (0740) and the positive edge criterion (0742) are different in the same order number (0760), then the same order number (0760) is selected as the criterion output (0780), if the negative edge criterion ( 0740) and the same order number (0760) of the positive edge criterion (0742), then the same sequence number (0762) is selected as the criterion output (0780), and the smallest sequence number in the selection criterion output is selected as the serial number (0782). ), the phase selection (0784) selects the in-phase intermediate clock (0340). If the maximum number in the selection criterion output is selected as the serial number selection (0782), the phase selection (0784) selects the inverted intermediate clock (0340), and the serial number selection is also It is determined whether to add 1 or subtract 1 correction according to one or part or all of the distortion criterion (0790);

9. The data output (0580) corresponding to the serial number selection (0782) and phase selection (0784) is output as the reception result data packet of the serial data (0000), and the corresponding stretched output (0570) can be used as the start and end of the data packet. The trigger signal needs to set a bit counter to give the number of bits of each data packet. The transmission frame (0210) of the asynchronous serial data (0002) is received in response to the effective level of the start bit (0220) from the active level of the stop bit (0224) or the idle bit (0226) to the received data (0314). The start of the rollover of the spread output, the number of bits of one transmission frame is the number of content bits (0222) plus one start bit and one stop bit, so the end trigger signal generating the data packet requires the participation of the bit counter.

Nine, application areas

In the foregoing description, the present invention provides a receiving method and apparatus for asynchronously receiving serial data (0000). The method and apparatus for serial data transmission are relatively simple, and the method of serial data receiving is complicated and difficult to implement. The method and device provided by the invention simplifies the structure of the serial data receiving device to the utmost, so that the cost is low and easy to implement, and not only can meet the requirements of high performance applications, but also can meet the requirements of low cost and low power consumption. Application requirements.

With the method and device of the present invention, two serial data transceivers can be realized, one is a Universal Serial Receievr/Transmitter (USRT), and the function can be any existing synchronous serial data. The function of the transmission interface, the other is the asynchronous serial transceiver (Universal Asynchronous Receievr/Transmitter, USRT), its data transmission rate can be as high as the data transmission rate of the synchronous serial data interface, and its physical layer protocol can be like universal input / The physical layer protocol of the Output Interface (General Purpose Input/Output, GPIO) is as simple as the following: The characteristics of the two serial data transceivers (0900) are as follows:

1. The method and apparatus of the present invention receive asynchronous serial data or synchronous serial data;

2, one-way or two-way electrical connection (0901), single-ended or differential drive, one-way electrical connection (0902) transmitting data only or receiving data only, the two-way electrical connection (0903) can transmit data and receive data in a time-sharing manner;

3. One-way or two-way data transmission channel (0904). The one-way data transmission channel (0905) consists of a one-way electrical connection (0902) that only transmits data or only receives data. The two-way data transmission channel (0906) consists of one. The two-way electrical connection (0902) constitutes or consists of a combination of a one-way electrical connection that only transmits data and a one-way electrical connection that only receives data;

4. One-way or two-way data transmission port (0907), one-way data transmission port (0908) consists of one or more unidirectional data transmission channels (0905), and two-way data transmission port (0909) consists of one or more two-way The data transmission channel (0906) is constructed.

The following is a section explaining the application of the method and apparatus of the present invention. For the sake of brevity, the universal serial data communication apparatus implemented by the universal interface or the USRT method of the present invention is asynchronously implemented by the asynchronous interface or the UART. Serial data communication device.

(1) Synchronous serial data communication over the physical layer of asynchronous serial data communication

With the method and apparatus of the present invention, asynchronous serial data (0002) communication with the same high data transmission rate as synchronous serial data (0003) communication can be realized, so that synchronization can be realized on the physical layer of asynchronous serial data communication. The data link layer and protocol layer protocol of serial data communication reduce the power consumption and cost of the interface. The characteristics of this method are as follows:

1. A method and apparatus according to the present invention for implementing a physical layer protocol for receiving and transmitting asynchronous serial data transmissions;

2. The synchronous serial data of the data link layer and the protocol layer is transmitted as the content bit of the asynchronous serial data of the physical layer;

3. The received content bit of the asynchronous serial data of the physical layer is submitted to the data link layer and the protocol layer of the synchronous serial data communication;

4. The data transmission port is implemented based on the method and apparatus of the present invention.

(2) A general purpose computer central processor

The current general purpose computer central processing unit (0910, CPU) has a variety of external interfaces. With the method and device of the present invention, only two (USRT and UART) physical layers can be realized, and only one (UART) physical layer external interface can be realized. General-purpose CPU, Figure 9 shows a schematic diagram of a general-purpose CPU using the USRT and or UART interface. In the case of a new definition or the existing data link layer and protocol layer protocol, the physical layer protocol of the CPU external interface is based on USRT. And / or UART definition, only based on the UART to define the physical layer protocol is better, in addition to CPU internal connections, such as the processor core (Core) and coprocessor, cache (Cache, L1/L2 / L3) connection, multiple The characteristics of this general-purpose single-core or multi-core CPU are as follows:

1. The internal structure of the central processing unit is arbitrary, and the new definition of the architecture or the existing architecture can be used;

2. A physical layer protocol for receiving and transmitting serial data in a unidirectional or bidirectional internal or external interface thereof as in the method and apparatus of the present invention;

3. Newly defined or adopted data link layer and protocol layer protocols of internal or external interfaces;

(3) A field programmable gate array device

Current Universal Field Programmable Gate Array (FPGA) devices (0920) have only a small number of high-speed serial data transfer ports, and when used in high-performance switches and/or routers, data transfer within the system can only be used with universal inputs. /Input (GPIO) port, resulting in a large number of pins of the device. With the method and device of the present invention, an FPGA having a USRT and/or UART port can be realized, and the USRT port is used for serial data transmission connection outside the system. Implementing various existing serial data transmission protocols, the UART port is used for serial data transmission connection inside or outside the system, and the simple performance of the method and device of the invention reduces the port overhead of the FPGA device, thereby making it more Multiple input and output resources support high-speed data transfers. Figure 10 shows a schematic of an FPGA using USRT and/or UART ports. The features of this field-programmable gate array device are as follows:

1. The internal architecture of the field programmable gate array device is arbitrary, and the new definition architecture or the existing architecture can be used;

2. A physical layer protocol for receiving and transmitting serial data in a one-way or two-way internal or external interface, as in the method and apparatus of the present invention;

(4) A memory of an asynchronous serial data transmission interface

The current general-purpose memories mainly include DRAM/SDRAM (0930), SRAM (0932), FLASH (0934), etc., all adopt parallel or serial data and control interfaces, and the UART physical layer interface can be realized by the method and device of the present invention. Single-port or multi-port DRAM/SDRAM, SRAM, FLASH, etc., can be directly connected directly to one or more general-purpose CPUs described in the “General Computer Central Processing Unit” section of this manual. Figure 11 shows the use of UART. Schematic diagram of DRAM/SDRAM, SRAM, FLASH, etc. of the interface. The characteristics of this memory are as follows:

1. The internal architecture of DRAM/SDRAM or SRAM or FLASH memory is arbitrary, and the new definition architecture or existing architecture can be used;

2. A method and apparatus according to the present invention for implementing a one-port or multi-port unidirectional or bidirectional physical layer protocol for receiving and transmitting asynchronous serial data;

3. Newly define or adopt existing operational commands and status information;

(5) A memory controller for a serial walking data transmission interface

The current general-purpose memories mainly include DRAM/SDRAM (0930), SRAM (0932), FLASH (0934), etc., all adopt parallel or serial data and control interfaces, and the UART physical layer can be realized by the method and device of the present invention. The interface of the single-port or multi-port DRAM/SDRAM, SRAM, FLASH and other memory controllers can be directly related to this specification "a general-purpose computer central processing unit" One or more general-purpose CPUs are partially connected directly. Figure 12 shows a schematic diagram of DRAM/SDRAM, SRAM, FLASH and other memory modules and controllers using a UART interface. The memory controller is connected to the DRAM/SDRAM and/or within the module. For memory such as SRAM and/or FLASH, the external port is a single port or multi port UART interface. The characteristics of this memory controller are as follows:

1. The interface structure with DRAM/SDRAM or SRAM or FLASH memory is arbitrary, and the new definition architecture or existing architecture can be used;

2. A physical layer protocol for receiving and transmitting asynchronous serial data in a one-port or two-way manner, unidirectional or bidirectional, as in the method and apparatus of the present invention;

3. Newly define or adopt existing operational commands and status information;

(6) An interface controller for a computer external device

The current common external device interfaces mainly include synchronous serial, synchronous parallel, asynchronous parallel, asynchronous serial, etc. The method and device of the present invention can implement an external device interface based on the USRT or UART physical layer protocol, which can be directly related to the present specification. One or more general purpose CPUs described in the section "General Computer Central Processing Unit" are directly connected. Figure 13 shows a schematic diagram of an interface controller of a computer external device based on the USRT or UART physical layer. The characteristics are as follows:

1. The internal architecture of the external device interface controller is arbitrary, and the new definition architecture or the existing architecture can be used;

2. A physical layer protocol for receiving and transmitting serial data in a one-way or two-way connection between an external device controller and a computer system, as in the method and apparatus of the present invention;

3. Newly define or adopt existing data link layer and protocol layer protocols;

(7) A relay device for data transmission

Any method for transmitting data has a maximum maximum distance for transmission. If a longer distance is to be transmitted, a relay device is required to transmit data. The method and apparatus of the present invention can implement a physical layer based on USRT or UART. Repeater, Figure 14 shows a schematic diagram of a data transfer relay using the USRT or UART physical layer. The original physical layer is maintained by the relay interface while maintaining the original data link layer and protocol layer protocol. It is better to be replaced by USRT or UART, and it is better to replace it with UART. The relay features of this data transmission are as follows:

1. The structure of the relayed data transmission interface is arbitrary, and the new definition architecture or the existing architecture can be used;

2. A physical layer protocol for implementing data transfer relaying according to the method and apparatus of the present invention;

3. Keep the data link layer and protocol layer protocols of the relayed interface unchanged;

(8) A switch for a system domain network

The system domain network is a data transmission network inside a high-performance computer system, and its performance and power consumption are compared. High, small to a single-processor small server internal data transfer network, up to a data transfer network inside a supercomputer with tens of thousands of processors, in a multi-processor computer system, system domain network switch It is often an indispensable core component. With the method and device of the present invention, a system domain network switch based on the USRT and/or UART physical layer can be implemented, and FIG. 15 shows a system domain based on the USRT and/or UART physical layer protocol. Schematic diagram of a network switch, the characteristics of such a system domain network switch are as follows:

1. The internal structure of the switch is arbitrary, and the new definition of the architecture or the existing architecture can be used;

2. A physical layer protocol for implementing a system domain switching network as in the method and apparatus of the present invention;

3. Newly define or adopt existing data link layer and protocol layer protocols;

(9) A switch and/or router of a computer network

The computer network is a data transmission network between computers. The scale is as small as a data transmission network inside a home. The scale is as large as a data transmission network with tens of thousands of computers inside the university. The Internet is a global domain computer network. And the router is a necessary device of the computer network, and the computer network switch and/or router based on the USRT and/or UART physical layer can be implemented by using the method and device of the present invention, and FIG. 16 shows the physical layer based on the USRT and/or UART. Schematic diagram of a protocol computer network switch and/or router. The characteristics of such a computer network switch and/or router are as follows:

1. The internal architecture of the switch and/or router is arbitrary, and the new definition of the architecture or the existing architecture can be used;

2. A physical layer protocol for implementing network switching and/or routing as in the method and apparatus of the present invention;

3. Newly define or adopt existing data link layer and protocol layer protocols;

(10) A switch or router of a communication network

The communication network is a data transmission network of the global domain. The switches and routers are indispensable components of the communication network. With the method and device of the present invention, communication network switches and/or routers based on the USRT and/or UART physical layer can be implemented. 17 shows a schematic diagram of a communication network switch and/or router based on the USRT and/or UART physical layer protocol. The characteristics of such a communication network switch and/or router are as follows:

3. Newly define or adopt existing data link layer and protocol layer protocols;

Claims

A method and apparatus for asynchronously receiving serial data, including:

a) The local clock and received data are input externally;

b) The local clock is directly used as the receiving clock or divided to generate the receiving clock. The receiving frequency is the same as the transmitting frequency. If the receiving clock is required to generate the N-phase intermediate clock through the multi-stage delay unit with the delay stage number N, the delay time of the delay component Greater than or equal to 0 and approximately equal, the mean is the clock average delay, and the delay can be generated by a preferred method such as wiring delay, delay line delay, cascade circuit delay, delay locked loop, etc., and can also be locally multiplied by the frequency of the receiving frequency. The clock generates a clock with a cascaded latch or a cascaded flip-flop equalization method, and the clock average delay is a fixed value or a variable value;

c) generating a spread pulse of at least about two transfer cycle widths based on the received data, if the received data is to be matched data via the delay matching component, and the flipping is aligned with the flipping of the stretched pulse, if the data needs to be received via the delay level N The multi-stage delay component generates N-phase intermediate data, the delay time of the delay component is greater than or equal to 0 and approximately equal, and the average value thereof is the data average delay, and the delay may be generated by a preferred method such as wiring delay, delay line delay, cascade circuit delay, and the like. The data average delay is a fixed value or a variable value. Based on the intermediate data, a spread delay of at least about two transmission period widths of the N phase is generated, and a delay time difference of adjacent two phase stretch delays is also an average data delay, and the N phase intermediate data is delayedly matched. The component becomes a data delay, causing its flip to be aligned with the flip of the stretch delay;

d) The average clock delay and the average data delay can be 0, but can be 0 at the same time. When the average clock delay is 0, the receiving clock is the intermediate clock, that is, the intermediate clock is not needed. When the average data delay is 0, the spread pulse and The matching data is the stretching delay and the data delay, respectively, that is, there is no need to generate the stretching delay and the data delay;

e) The sampling shift register with the number of sampling stages is separately phase-sampled for the N-phase broadening delay and the N-phase data delay, and the falling and flipping of the sampling intermediate clock are simultaneously performed to obtain the negative edge broadening and the positive edge broadening and data output. The sampling may be positive sequential sampling or reverse sequential sampling. The positive sequential sampling means that the intermediate clock serial number and the sequence of the sampled signal are changed in the same order, and the reverse sequential sampling means that the intermediate clock serial number and the sequence number of the sampled signal are reversed;

f) respectively, the negative edge broadening and the positive edge broadening of the same stretch width are mutually sampled, and the flip timing of the two is determined based on the sampling result, and the stretched output is divided into a negative edge output lead group and a positive edge output lead group according to the flip timing, respectively. Among them, the number adjacent to the serial number is the one with the largest number of simultaneous sequences and the lowest starting number is used as the negative edge criterion and the positive edge criterion, and the starting serial number and the same serial number are respectively used as the negative edge serial number and the positive edge serial number;

g) Calculate the mean value of the negative edge number and the positive edge number, the variance of the serial number, and the difference of the serial number as the distortion criterion, and select one or more data window widths to calculate the mean value of the serial number and the variance of the serial number;

h) If the number of the same order of the negative edge criterion and the positive edge criterion is different, the one with the same number of the same order is selected as the criterion output. If the number of the same order of the negative edge criterion and the positive edge criterion is the same, the same sequence number is selected. As the criterion output, if the smallest serial number in the selection criterion output is selected as the serial number, the phase selection selects the in-phase intermediate clock, and the maximum serial number in the selection criterion output is selected as the serial number. Then the phase selection selects the inverted intermediate clock, and the serial number selection further determines whether to add 1 or subtract 1 correction according to one or part or all of the distortion criterion;

i) The data output corresponding to the serial number selection and phase selection is output as the receiving result data packet of the serial data, and the corresponding stretched output can be used as the trigger signal for the start and end of the data packet, and a bit counter needs to be set to give each data packet. The number of bits. The transmission frame reception of the asynchronous serial data starts with the inversion of the stretched output corresponding to the start bit effective level of the received bit from the active level of the stop bit or the idle bit, and the number of bits of one transmission frame is the number of content bits. A start bit and a stop bit are added, so the end trigger signal that generates the data packet requires the participation of the bit counter.
A serial data transceiver device comprising:

a) The method and apparatus of claim 1 receiving synchronous serial data or asynchronous serial data;

b) One-way or two-way electrical connection, single-ended drive or differential drive, one-way electrical connection only transmits data or only receives data, and two-way electrical connection can transmit data and receive data in a time-sharing manner;

c) a one-way or two-way data transmission channel consisting of a one-way electrical connection that transmits only data or only receives data. The two-way data transmission channel consists of a two-way electrical connection or a single data transmission Composed of an electrical connection and a one-way electrical connection that only receives data;

d) One-way or two-way data transmission port, the one-way data transmission port is composed of one or more one-way data transmission channels, and the two-way data transmission port is composed of one or more bidirectional data transmission channels.
A method and apparatus for synchronous serial data communication over a physical layer of asynchronous serial data communication, comprising:

a) The method and apparatus of claim 1 implementing a physical layer protocol for receiving and transmitting asynchronous serial data;

b) the synchronous serial data of the data link layer and the protocol layer is sent as the content bit of the asynchronous serial data of the physical layer;

c) the content bits of the received asynchronous layer of the physical layer are submitted to the data link layer and the protocol layer of the synchronous serial data communication;

d) The data transmission port of claim 2.
A single-core or multi-core general-purpose computer central processor, comprising:

a) The internal architecture of the central processing unit is arbitrary, and the new definition of the architecture or the existing architecture can be used;

b) a physical layer protocol for receiving and transmitting serial data of the method and apparatus of claim 1 and/or 3 that implements its one-way or two-way internal or external interface;

c) newly defined or adopted data link layer and protocol layer protocols of the external interface;

d) The data transmission port of claim 2.
A field programmable gate array device comprising:

a) The internal architecture of the field programmable gate array device is arbitrary, and the new definition architecture or existing architecture can be used;

b) a method and apparatus according to claim 1 and/or 3 for implementing a physical layer protocol for receiving and transmitting serial data over a one-way or two-way internal or external interface;

c) a new definition or data link layer and protocol layer protocol using existing internal or external interfaces;

d) The data transmission port of claim 2.
A memory for an asynchronous serial data transmission interface, comprising:

a) The internal architecture of DRAM/SDRAM or SRAM or FLASH memory is arbitrary, and the new definition architecture or existing architecture can be used;

b) The method and apparatus of claim 1 implementing a one-port or multi-port unidirectional or bidirectional physical layer protocol for receiving and transmitting asynchronous serial data;

c) new definitions or use of existing operational commands and status information;

d) The data transmission port of claim 2.
A memory controller for an asynchronous serial data transmission interface, comprising:

a) interface structure with DRAM/SDRAM or SRAM or FLASH memory, any new definition architecture or existing architecture;

b) The method and apparatus of claim 1 implementing a one-port or multi-port unidirectional or bidirectional physical layer protocol for receiving and transmitting asynchronous serial data;

c) new definitions or use of existing operational commands and status information;

d) The data transmission port of claim 2.
An interface controller for a computer external device, comprising:

a) The internal architecture of the interface controller of the external device is arbitrary, and the new definition of the architecture or the existing architecture can be used;

b) a method and apparatus according to claim 1 and/or 3 for implementing a physical layer protocol for receiving and transmitting serial data in a one-way or two-way connection between an external device controller and a computer system;

c) new definition or adoption of existing data link layer and protocol layer protocols;

d) The data transmission port of claim 2.
A relay device for data transmission, comprising:

a) The architecture of the relayed data transfer interface is arbitrary, and the new definition of the architecture or the existing architecture can be used;

b) a physical layer protocol for implementing data transfer relaying by the method and apparatus of claim 1 and/or 3;

c) keeping the data link layer and protocol layer protocols of the relayed interface unchanged;

d) The data transmission port of claim 2.
A switch for a system domain network, including:

a) The internal architecture of the switch is arbitrary, and the new definition of the architecture or the existing architecture can be used;

b) a method and apparatus according to claim 1 and/or 3 for implementing a physical layer protocol of a system domain switching network;

c) new definition or adoption of existing data link layer and protocol layer protocols;

d) The data transmission port of claim 2.
A computer network switch and/or router comprising:

a) The internal architecture of the switch and / or router is arbitrary, the new definition of the architecture or the existing architecture can be used;

b) a physical layer protocol for implementing network switching and/or routing in accordance with the method and apparatus of claims 1 and/or 3;

c) new definition or adoption of existing data link layer and protocol layer protocols;

d) The data transmission port of claim 2.
A switch and/or router for a communication network, including:

a) The internal architecture of the switch and / or router is arbitrary, the new definition of the architecture or the existing architecture can be used;

b) a physical layer protocol for implementing network switching and/or routing in accordance with the method and apparatus of claims 1 and/or 3;

c) new definition or adoption of existing data link layer and protocol layer protocols;

d) The data transmission port of claim 2.