KR20050115195A - Asynchronous switch based on butterfly fat-tree for network on chip applications - Google Patents

Abstract

This paper presents an asynchronous switch circuit for network on chip application that enables communication between IPs through various IP (Intellectual Property) in network on chip.

The asynchronous switch circuit of the present invention receives and temporarily stores a plurality of data flits, and checks whether a data type is a header flit or a payload flit according to a data transmission request signal, and a header flit processing request signal from the data input part. In response to receiving the last payload fleet processing request signal, header fleet routing information, and arbitration request signal, an output port arbitration unit for outputting an output port selection signal and a data output priority determined by the data output priority determined by the output port arbitration unit Receives a header storage request signal and a payload storage request signal from a data movement path setting unit and a data input unit sequentially storing the data streams, and temporarily stores data flits inputted from the data movement path setting unit to a designated port in a predetermined order. Data output section for output Include.

Description

Asynchronous Switch Based on Butterfly Fat-Tree for Network On Chip Applications}

The present invention relates to an asynchronous switch circuit, and more particularly, to an asynchronous switch circuit using a butterfly fat-tree for network on-chip applications that enable communication between IPs through various IP (Intellectual Property) in the network on-chip. .

To meet the rapidly growing multimedia capabilities, System on Chip (SoC) technology is essential, with millions of gates on one chip. SoC can be viewed as a semiconductor integrated circuit that integrates the main functions of the system into one chip. The SoC contains all the hardware and software features that make up the system, including memory, processors, external interfaces, analog and mixed-mode blocks, embedded software, and an operating system.

SoCs generally have an interconnection structure in which all components share a single bus to communicate with each other. In this case, communication between components is slow. In addition, the signal transmission from one component to another component is not only transmitted to a specific component but to all components, so power consumption is disadvantageous. In addition, although 8 to 10 components are mounted and used in one chip, there is a need to expand the structure of the chip to mount 50 to 100 components in the future. In this case, as the number of components connected to the bus-sharing structure increases, the load increases and the transmission speed between the components decreases. Therefore, the number of components included in one chip using the bus structure is reduced. It is impossible to increase the number indefinitely.

As such, at present, system-on-chip employs a bus structure for interconnection between components, but has no scalability, delays in data transmission, and bandwidth limitations, causing bottlenecks. There is. In addition, since multiple bus masters compete to gain control of the bus, as the number of bus masters increases, data transfer delay increases, resulting in poor performance, and the performance of the bus is determined by IP. Can't. In addition, since the switching using the current bus structure is implemented synchronously, the use of a clock is essential and a problem thereof cannot be ruled out.

Meanwhile, a network on chip is being studied to solve the problem of the system on chip described above and to support smooth communication between large-scale IPs in one chip. The application of network on chip is expected to solve various problems of system on chip such as scalability limitation, data transmission delay, power consumption, etc., but more research is needed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide an asynchronous switch circuit for supporting interconnections between IPs in a network on a chip.

The present invention for achieving the above-described technical problem is an asynchronous switch circuit for a network-on-chip application for delivering a plurality of data packets, the data packet is composed of one header flit and at least one payload flit, A data input unit configured to receive a data fleet of the data fleet and temporarily store the received data fleet, and to determine whether the data fleet is a header flit or a payload flit according to a data transmission request signal; An output for outputting an output port selection signal indicating an output priority of the data in response to receiving a header flit processing request signal, a last payload flit processing request signal, routing information of the header flit, and an arbitration request signal from the data input unit; Port arbitration; A data movement path setting unit for sequentially storing the data flits according to the data output priority determined by the output port arbitration unit; And a header and payload storage completion signal indicating that the data fleet is stored after receiving a header storage request signal and a payload storage request signal from the data input unit, temporarily storing the data fleet inputted from the data movement path setting unit. And a data output unit for transmitting to the data input unit and outputting the temporarily stored data flits to a designated port in a predetermined order.

Since the switch circuit proposed in the present invention is an asynchronous method, it does not use a clock but uses a 4 phase bundled data protocol, which is one of the handshake protocols. In addition, worm hole switching technology is introduced to maximize switch performance, and the output buffering is used to simplify control logic. The handshake protocol is a sequence of messages exchanged between two or more devices for synchronization between transmitters and receivers during data transmission. It refers to the ability of the other device to verify that it is ready to receive data. It means a plurality of data bundles. In addition, when wormhole switching divides one data packet into a plurality of flits and transmits the data, the wormhole switching occupies the data transmission path from the start of the first fleet to the last fleet so that other data packets are not transmitted to the corresponding data transmission path. I say that.

In addition, the present invention adopts a butterfly fat-tree form as a topology of a switch circuit, and provides a flit format suitable for such a topology, so that a variable length flit can be transmitted and received. Butterfly fat-trees are useful structures for large-scale communication networks and have excellent features such as area and volume universality.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an example of a general network on-chip structure.

As shown, it can be seen that one switch (S) is connected to one IP (R). In such a network-on-chip structure, five I / O ports must be provided in one switch S, and a packet inputted by a predetermined routing algorithm is transmitted to a destination. In this case, as the traffic increases toward the center of the network, a high-speed switch must be used in the center of the network. Also, as the traffic increases, the length of the I / O queue in the switch increases, so the buffer of the switch in the center of the network must be designed large.

2 is a conceptual diagram of an asynchronous switch circuit according to the present invention.

As shown, the asynchronous switch circuit for a network on-chip application according to the present invention is a data input unit 110 for receiving and temporarily storing a reset signal, a control signal and a plurality of data, a reset signal is input to the data input unit 110 When a plurality of data are simultaneously input and output to the same output port, the data is moved according to the data output ranking determined by the output port arbitration unit 120 and the output port arbitration unit 120 to determine the priority of the output data. And a data output unit 140 for outputting data input from the data movement path setting unit 130 to a designated port according to the data movement path setting unit 130 and the reset signal and the control signal.

In more detail, when data is input, the data input unit 110 checks whether the data is a header or a payload from a given data format and decodes the data according to the type. 140) request processing for each data type (header, payload).

The output port arbitration unit 120 receives one of the arbitration request signal, the header fleet processing request signal, the last payload storage completion signal, and the routing information from the data input unit 110, and selects one of the data to be simultaneously output to the same output port. The result is transmitted to the data input unit 110 (arbitration signal request response signal). In addition, the output port information selected for each data is transmitted to the data movement path setting unit 130 so that the data is correctly transmitted to the data output unit 140 through the data movement path setting unit 130.

The data output unit 140 receives a data processing request signal from the data input unit 110 (header processing request signal, payload storage completion signal), receives output port information from the output port arbitration unit 120, and moves data. Outputs the data input through the path setting unit 130 to a predetermined output port. After temporarily storing the data, the data storage completion signal is transmitted to the output port arbitration unit 120 to notify that the data storage is completed, and after outputting the data to the designated port, the data input unit 110 is notified (header processing). Response signal, payload processing response signal) The data input unit may delete previously stored data to process subsequent data.

In addition, the data input unit 110 transmits a signal (input request response signal) indicating that the input data has been processed by another switch or IP requesting data transmission, and the data output unit 140 outputs data to the corresponding output port. After that, the output request signal is transmitted to the data input unit of the next stage switch, so that the data is output by the above-described process in the next stage switch, and the data input unit of the next stage switch is a response signal (output response signal) for the output request signal. ) Is transmitted to the data output unit 140.

Such a switch circuit can be implemented in a 6 * 6 butterfly fat-tree structure having six input ports and six output ports, and a data packet is composed of a plurality of flits, and a fleet of 23 bits can be implemented. . In addition, the input and output ports consist of four lower ports and two upper ports, respectively.

FIG. 3 is a detailed configuration diagram of the asynchronous switch circuit shown in FIG. 2.

First, the data input unit 110 inputs six 23-bit data (in0 (22: 0>, in1 (22: 0>, in2 (22: 0>, in3 (22: 0>, in4 (22: 0>)). , in5 (22: 0>), and the input data packet has a format as shown in Fig. 4. The data packet is composed of one header flit and a plurality of payload flit, and Fig. 4a shows a header flit and Fig. 4b. Indicates a payload fleet.

The header flit shown in FIG. 4A is composed of a type field (2 bits), a source address field (6 bits), and a routing information field (15 bits). The source address field is a part representing a subject (IP) that transmitted data. By assigning it 6 bits, 64 IPs can be connected to a single switch. In case of connecting and using 64 IPs, the maximum number of switches to pass through is 5, so one switch information can be represented by 3 bits, and thus the routing information field becomes 15 bits. Here, the routing information is generally determined at the interface unit connected between each IP and the asynchronous switch. Since the interface unit is far from the technical field of the present invention, a detailed description thereof will be omitted.

On the other hand, the payload flit shown in Fig. 4B is composed of a type field (2 bits) and a payload field (21 bits), and actual data is recorded in the payload field. In this case, the type field is set to 00 for a header flit, 10 for a payload flit, and 11 for a last payload flit.

In the data format applied to the present invention, the routing information can be considered as a movement path of data, that is, output port information of a switch (or input port information of a switch to which data is to be input). That is, the routing information is composed of five bits of three bits. When data is input, the data input unit 110 refers to the type field to distinguish whether the header flit or the payload flit, and in the case of the header flit, selects the least significant three bits of the routing information. Check it. The lowest 3 bits are the information that identifies the output port of the switch, and the asynchronous switch sends this header fleet to the next switch through the output port indicated by the least significant 3 bits. In addition, the transmission path is maintained to transmit the payload flit after the header flit to the next switch through the same output port, and other data packets can use the output port after transmitting all the way to the last payload.

In addition, after acquiring the output port information by checking the lower 3 bits of the header flit, the data input unit 110 deletes the lower 3 bits information, shifts the remaining 12 bits of routing information to the right by 3 bits, and then selects the highest 3 bits. Bits (12th to 14th bits) are zeroed out. In this way, after the header flit is transmitted to the next switch, output port information can be obtained by using the least significant 3 bits of the header flit in the next switch.

The data input unit 110 also includes a reset signal resetb, a data transmission request signal input_req0 to input_req5 transmitted from the data transmission entity, a header storage completion signal Datah_a0 to Datah_a5 transmitted from the data output unit 140, and a payload. The storage completion signals Datap_a0 to Datap_a5 and the arbitration signal request response signals Arb_ack0 to Arb_ack5 transmitted from the output port arbitration unit 120 are input.

Data packets input to six input ports are numbered according to input ports and processed by other modules that perform the same function. The input ports consist of four lower ports and two upper ports. Data input to the four lower ports is processed in the corresponding lower input processing module, and data input to the two upper ports is processed in the corresponding upper input processing module, which is illustrated in FIG. 5.

FIG. 5 is a detailed configuration diagram of a data input unit applied to the present invention and shows four lower input processing modules 111, 112, 113, and 114 and two upper input processing modules 115 and 116.

Referring to the difference between the lower input processing module and the upper input processing module, the lower input processing modules 111, 112, 113, and 114 can transmit data to six output ports including themselves, respectively, so that three bits of routing information bits ( It has a RIB <2: 0>, whereas the upper input processing modules 115 and 116 always have two bits of routing information bits (RIB <1: 0>) because they always output data to the upper output port. .

Each input processing module 111 to 116 checks the type field of the data when 23 bits of data are input and processes the input data differently depending on whether the input data is a header flit or a payload flit. That is, when data is input together with the data transmission request signal (Input_req) (In <22: 0>) and the header field is determined as a result of checking the type field, the data transmission request response signal (Input_ack) is transmitted to the data transmission subject and the header fleet is transmitted. Store in a buffer. Subsequently, the mediation request signal Arb_req is transmitted to the output port arbitration unit 120 together with the routing information RIB. When the response Arb_ack is received, the header storage request signal Datah_r is transmitted to the data output unit 140. Send it. After outputting the header flit (Out <22: 0>) from the data output unit 140, the header storing completion signal Datah_a indicating the message is transmitted to the data input unit 110.

On the other hand, if the input data is a payload flit, the data may be transmitted along the path of the header flit. First, the data transmission request response signal (Input_ack) is transmitted to the data transmission entity, and the payload flit is stored in a buffer. The payload storage request signal Datap_r is transmitted to the output unit 140. After the payload flit is output (Out <22: 0>) by the data output unit 140, the payload storage completion signal Datap_a indicating this is transmitted to the data input unit 110.

Meanwhile, the header flit processing request signal H_r is a signal transmitted from the data input unit 110 to the output port arbitration unit 120 together with the arbitration processing request signal, and means that data transmission for one data packet is started. The last payload processing request signal L_r indicates that the last payload flit for one data packet is transmitted. The last payload flit is output until the last payload storage completion signal is activated. Until that output port is reserved for specific data transfers. In addition, the routing information transmitted to the output port arbitration unit 120 uses 3 bits for the lower input processing module and 2 bits for the upper input processing module, and after checking the least significant routing information (3 bits) of the header fleet, Shift the routing information to the right so that the next switch can refer to it.

The input processing module will be described in more detail as follows.

6 is a detailed configuration diagram of the lower input processing module illustrated in FIG. 5, and FIG. 7 is a detailed configuration diagram of the upper input processing module illustrated in FIG. 5. Since the lower and upper input processing modules operate in the same manner only with differences in routing information bits, they will be described together.

As shown, the input processing module includes payload controllers 1111 and 1151, header controllers 1112 and 1152, data storage units 1113 and 1153, and header fleet processing request signal generators 1114 and 1154. , Each component is controlled by a reset signal resetb.

When the data transmission request signal Input_req is input from the data transmission entity and data is input to the data storage units 1113 and 1153 (In <22: 0>), the data storage units 1113 and 1153 are configured to input the data. The flit type is checked by referring to the type field (F_type <1: 0>) among the data fields, and when it is determined that the input data flit is a header flit (00), the header flit processing request signal generators 1114 and 1154 are used. Is transmitted to the input terminal D, and the header flit processing request signal H_r of the header controllers 1112 and 1152 is activated.

Subsequently, the header controllers 1112 and 1152 transmit the arbitration request signal Arb_req to the output port arbitration unit 120, receive a response signal Arb_ack thereto, and transmit the header flits to the data storage units 1113 and 1153. Request to save (Bufh_r) and request to shift routing information (Shift_r). In addition, the header flit buffering request signal Buhf_r is transmitted to the input terminal E of the header flit processing request signal generating units 1114 and 1154 to generate the header flit processing request signal H_r indicating that an output port based on routing information is occupied. To be used in. Accordingly, the header flit processing request signal generating units 1114 and 1154 perform header flit processing indicating that the corresponding output port is occupied by the reset signal, the header flit input signal D, and the header flit buffering request signal E. The request signal H_r is output. In addition, the header output completion signal Dtah_r is transmitted to the data output unit 140.

Meanwhile, the data storage units 1113 and 1153 store the corresponding header flit according to the header flit buffering request signal Buf_r transmitted from the header controllers 1112 and 1152, and then transmit the response signal Buf_a to the header controller ( 1112 and 1152, the routing information RIB is transmitted to the output port arbitration unit 120, and the routing information bit string is right according to the routing information shift request signal Shft_r of the header controllers 1112 and 1152. After shifting by 3 bits and filling the most significant 3 bits of the routing information field with 0, the response signal Shift_a is transmitted to the header controllers 1112 and 1152. The routing information is represented using 3 bits (RIB <2: 0>) when the input processing module is a lower input processing module and 2 bits (RIB <1: 0>) when the input processing module is an upper input processing module. In addition, the data storage units 1113 and 1153 transmit the data Out <22: 0> to the data movement path setting unit 130.

Meanwhile, when the data transmission request signal Input_req is input from the data transmission entity and data is input to the data storage units 1113 and 1153 (In <22: 0>), the data storage units 1113 and 1153 are inputted. Extract the type field (F_type <1: 0>) of the data field of the data to check the type of the fleet, and if the input data flit is determined to be a payload flit (10), it is notified to the payload processing unit to process the payload flit The request signal P_r is activated. Accordingly, the payload controllers 1111 and 1151 output a response signal P_a for the payload flit processing request, a response signal H_a for the header flit processing request signal, and a response signal for the payload flit processing request. Using the P_a and the flit type information F_type <0>, a transmission request response signal Input_ack indicating that data transmission has started is transmitted to the data transmission entity.

Subsequently, the payload control units 1111 and 1151 transmit the payload storage completion signal Dtap_r to the data output unit 140, and request to store the payload flits to the data storage units 1113 and 1153 (Bufp_r). )do. Accordingly, the data storage units 1113 and 1153 store the corresponding payload flits according to the payload flit buffering request signal Bupf_r transmitted from the payload controllers 1111 and 1151, and then respond with a response signal Bupf_a. Is transmitted to the payload controllers 1111 and 1151.

Thereafter, the data storage units 1113 and 1153 transmit data Out <22: 0> to the data movement path setting unit 130, and the payload flit is a transmission path of the header flit (output port arbitration unit 120). Is transmitted to the data output unit 140 in accordance with the transmission path determined in step.

On the other hand, after storing the data for outputting data from the data output unit 140, a signal indicating that the data fleet has been output to the payload controllers 1111 and 1151 and the header controllers 1112 and 1152, that is, the payload. The storage completion signal Datap_a and the header storage completion signal Datah_a are transmitted.

In addition, as a result of checking the type field F_type <1: 0> among the data fields of the data input to the data storage units 1113 and 1153, if the input data is identified as the last payload flit (11), the header flit processing is performed. Transmitted to the request signal generators 1114 and 1154 so that the header flit processing request signal H_r is switched to an inactive state and the last payload processing request signal L_r is activated to occupy the corresponding data packet. Release the output port.

FIG. 8 is a detailed configuration diagram of the payload control unit illustrated in FIGS. 6 and 7.

As illustrated, the payload controllers 1111 and 1151 delay the payload fleet processing request signal P_r generated from the data transmission request signal Input_req for a specified time and then request to store the payload flits (bufp_r). It includes a delay element (D1) for generating a). The payload flit buffering request signal bufp_r is transmitted to the data storage units 1113 and 1153.

In addition, the payload controllers 1111 and 1151 may receive the payload fleet buffering response signal bufp_a, the reset signal resetb, and the previous payload received from the data storage unit 1113 and 1153. Input the save completion signal (Datap_a) for the fleet as 0. If both input values of the previous state are 0, 0 is output. If any one of the input values is 0, 0 is continuously output. 1 is outputted, and if any one of the input values is 1, the first logic element C-element (gc; L1) and the output signal of the first logic element and the payload flit buffering response signal (bufp_a) ) And a second logic element (NAND gate L2) outputting 1 when both input values are 1. Here, the first logic device outputs 0 when the reset signal is input, and the input / output relationship may be represented by a truth table as shown in [Table 1].

Input 1 (Bufp_a) Input 2 (Datap_a) Output (Datap_r) 0 0 0 0 One 0 One 0 0 One One One One 0 One 0 One One 0 0 0

Specifically, when the first logic element L1 processes the first payload flit, the response signal bufp_a for the payload flit buffering request is 1, and the storage completion signal Datap_a for the previous payload flit is performed. Since 0 is 0, the payload storage request signal Datap_r is output as 1. In addition, since the output value of the first logic element L1 and the payload flit buffering request response signal bufp_a are all 1, the output signal of the second logic element L2, that is, the response signal P_a for the payload fleet processing request. Is activated to be transmitted as a data transmission request response signal to the data transmission subject side.

9 is a detailed block diagram of the header control unit shown in FIGS. 6 and 7.

The header controllers 1112 and 1152 input the header fleet processing request signal H_r and the response signal Arb_ack for the arbitration request, and output a 1 only when both input values are 0. And a fourth logic for outputting the response signal H_a for the header flit processing request by inputting the output value of the third logic element L3, the reset signal resetb, and the response signal bufh_a for the header fleet buffering request. The inverted values of the elements gc and L4 and the fourth logic element L4 and the response signal Shift_a for the shift request are inputted, and a 1 is outputted only when both inputs are 1 so that the header storage request signal Buf_r ), The fifth logic element L5 and the reset signal resetb are inputted, and the input values of the fourth logic element L4 and the inverted value of the fifth logic element L5 output are input. If all 1, the output value of the sixth logic element L6 that outputs 1 is the first input, and the fourth As the second input, the inverted value of the output of the element L4 and the output signal of the seventh logic element L7 outputting 1 when both input values are 1 as the input of the header fleet processing request signal H_r are input. If the input values are all 0, 1 is outputted.If any one of the input values is 0, the output value is kept at 1, and if the input values are all 1, 0 is outputted. A shift request by inverting the output values of the eighth logic element L8 and the eighth logic element gc '; L8 held at 0 (that is, outputting a value opposite to the output of the fourth logic element L4) A ninth logic element L9 for outputting the signal Shift_r and a reset signal are input, and the inverted values of the header fleet processing request signal H_r and the header storage completion signal Datah_a are input, and two input values are input. If all are 0, the output value of the 10th logic element L10 that outputs 1 is the first input, and the fourth An eleventh logic element L11 that outputs 1 when the output value of the logic element L4, the inverted value of the header fleet buffering request response signal Buhf_a, and the header fleet processing request signal H_r are input, and the input value is 1, respectively. The twelfth logic element L12 having the output value of?) As the second input, the thirteenth logic element L13 for inverting the output of the twelfth logic element L12, and the reset signal are input, and the thirteenth logic element L13 A fourteenth logic element L14 and a reset signal for outputting the arbitration request signal Arb_req with the output signal of the first input, the response signal Arb_ack for the arbitration request as the second input, and the reset signal resetb are inputted. The header storage completion signal Datah_a is the first input, and the inverted values of the header fleet processing request signal H_r and the response signal Arb_ack for the arbitration request signal and the header storage completion signal Datah_a are input. If all are 1, output of the fifteenth logic element L15 outputting one. The sixteenth logic element L16 having the value as the second input, and the seventeenth logic element L17 inverting the output of the sixteenth logic element L16 to generate the header storage request signal Datah_r. Herein, when the reset signal is input, the fourteenth logic element L14 outputs 0, and the input / output relationship may be represented by a truth table as shown in [Table 2].

Input 1 (L13) Input 2 (Arb_ack) Output (Arb_req) 0 0 0 0 One One One 0 One One One One One 0 0 0 One One 0 0 0

The operation of the header controllers 1112 and 1152 shown in FIG. 9 will be described in detail as follows. First, when the header flit processing request signal H_r generated from the data transmission request signal input_req is activated, the output of the fourth logic element L4 becomes 0 once, and thus, the eighth logic element L8 When the first input is 0 and the second input is 0, the output signal of the eighth logic element L8 becomes 0, and the signal inverted by the ninth logic element, that is, the shift request signal Shift_r is activated, and the data is activated. The data are transmitted to the storage units 1113 and 1153.

Subsequently, when the data storage unit shifts the routing information and transmits the response signal Shift_a for the shift request, the output signal of the fifth logic element L5, that is, the header flit buffering request signal Buhf_r is activated to store data. Are transmitted to the units 1113 and 1153. Subsequently, after storing the header flit in the data storage units 1113 and 1153, the response signal Buf_a for the header flit storage request is transmitted. Accordingly, the header flit processing completion signal H_a, which is the output signal of the fourth logic element L4, becomes 1, while the first input of the twelfth logic element L12 becomes 0 and the second input becomes 1, Since 0 is output from the twelfth logic element L12, and the first input of the fourteenth logic element L14 is 1 and the second input is 0, the arbitration request signal Arb_req is activated.

Subsequently, when the response signal Arb_ack for the arbitration request is received from the output port arbitration unit 120, the first input of the sixteenth logic element L16 becomes 0 and the second input becomes 1, thereby providing the sixteenth logic element. 0 is outputted from L16, which is inverted by the seventeenth logic device L17 to transmit the header storage request signal Datah_r to the data output unit 140. Thereafter, the header storing completion signal Datah_ack is received from the data output unit 140.

10A to 10C are C-element circuit diagrams and asymmetric C-element circuit diagrams applied to the present invention.

First, FIG. 10A illustrates an implementation example of the first logic element L1 of FIG. 8 and the fourth logic element L4 of FIG. 9. The first logic element L1 of FIG. 9 is connected to a power supply terminal and driven by the first input signal a. Connected in series to the 1 P type transistor P1 and the first P type transistor, and connected in series to the second P type transistor P2 and the second P type transistor driven by the inverted signal of the second input signal b. A first N-type transistor N1 driven by the first input signal a, a second N-type transistor connected in series between the first N-type transistor and the ground terminal and driven by an inverted signal of the second input signal b; Type transistor N2, connected between the power supply terminal and the output terminal of the second P type transistor, and connected to the output terminal of the third P type transistor P3 and the second P type transistor driven by a reset signal resetb. Including a first latch circuit (latch 1) as a delay element All.

Next, FIG. 10B illustrates an implementation of the eighth, twelfth, and sixteenth logic elements L8, L12, and L16 of FIG. 9, and is connected to a power supply terminal and driven by a first input signal a. A fourth P type transistor P4 and a fourth P type transistor connected in series and driven in series by an inverted signal of the second input signal b, connected in series to a fifth P type transistor P5 and a fifth P type transistor, Third N-type transistor N3 driven by the first input signal a, fourth N-type transistor connected in series between the third N-type transistor and the ground terminal and driven by the inverted signal of the second input signal b Transistor N4, connected between the output terminal of the fifth P-type transistor and the ground terminal, and connected to the output terminals of the fifth N-type transistor N5 and the fifth P-type transistor driven by the inverted signal of the reset signal reset. Second latch circuit as a delay element to be connected (latch It includes 2).

FIG. 10C illustrates an implementation of the fourteenth logic element L14 of FIG. 9. The sixth P-type transistor P6 and the sixth P-type transistor P6 are connected to a power supply terminal and driven by an inverted signal of the first input signal a. A sixth N-type transistor N6 connected in series with the P-type transistor and driven by an inverted signal of the first input signal a, a second input signal b connected in series between the sixth N-type transistor and the ground terminal; Is connected between a power supply terminal and an output terminal of a sixth P-type transistor, and is driven by a reset signal resetb, and is driven by a reset signal resetb. And a third latch circuit (latch 3) as a delay element connected to the output terminal of the transistor.

11A and 11B are detailed block diagrams of the input data storage unit shown in FIGS. 6 and 7.

Referring to FIG. 11A, data for inputting 23 bits of data from the 0th data bit to the 14th data bit, the shift request signal Shift_r, the inversion signal of the shift request signal, and the data bits to the right of 3 bits are input. The selection means 1115, the data bit value 0, the shift request signal Shift_r, the inverted signal of the shift request signal, and three auxiliary data selection means 1115 'that respectively input data bits to the right of the three bits, and the reset signal ( the lower data storage means 1116, which is controlled by the resetb and which stores the output value of the data selection means 1115 by inputting the output signal of the data selector 1115 and the output signal of the eighteenth logic element L18, respectively. And an output signal of the auxiliary data selection unit 1115 'and an output signal of the eighteenth logic element L18, which are controlled by the reset signal resetb, to store the output value of the data selection means 1115, respectively. Controlled by an auxiliary data storage means 1116 'and a reset signal resetb and inputting the output signal of the eighteenth logic element L18 and the fifteenth data bit from the fifteenth data bit to the 23-bit data, And upper data storage means 1116 " for storing the data bit values, respectively. In addition, the most significant two bits of the input data bit string are payload controllers 1111 and 1151 according to the data flit types F_type0 and F_type1. Or input to the header controllers 1112 and 1152.

Herein, the eighteenth logic element L18 receives the header fleet buffering request signal Buhf_r and the payload flit buffering request signal Bupf_r as inputs, and outputs a 1 when one of the two signals is 1 (OR). ) Can be implemented with a gate. In addition, since the lower three data selection means 1115 cannot receive the data bits to the right of the three bits, the lower three data selection means 1115 receive the output values of the lower data storage means 1116 connected to the respective output terminals.

Meanwhile, the shift request signal Shift_r, the header flit buffering request signal Buf_r, and the payload flit buffering request signal Bup_r are respectively delayed after a specified time delay, and the shift request response signal Shift_a, the header flit buffering response signal Buf__, As a payload flit buffering response signal Bupf_a, it is transmitted to a payload control unit and a header control unit.

In addition, in the present embodiment, the case in which the routing information of one switch is represented by 3 bits has been described. However, the number of auxiliary data selection units and the number of shift bits of the routing information may be changed according to the routing information bits.

FIG. 11B is an example of the configuration of the data selecting means 1115 and the auxiliary data selecting means 1115 'shown in FIG. 11A. When the shift request signal Shift_r and the data bit are input, 1 is 1 when both inputs are 1. The 19th logic element L19 to be output, the inversion signal of the shift request signal Shift_r, and the data bits to the right of the three bits (the output values of the data storage means connected to each of the three lower data selection means) are input. A twenty-first logic element L20 that outputs one when the inputs are all one, and a twenty-first logic element that outputs one when the input values of one of the two input values are one; L21).

The operations of the data storage units 1113 and 1115 having such a configuration will be described in detail as follows when the input data is a header flit and a payload flit.

First, when the header flit is input, the 21st data bit and the 22nd data bit value, that is, the data type fields F_type0 and F_type1 are detected and transmitted to the header controllers 1112 and 1152. Accordingly, the shift request signal Shift_r and the header flit buffering request signal Buhf_r are activated. In this case, the output of the nineteenth logic element L19 constituting the data selection means 1115 and the auxiliary data selection means 1115 'is determined in accordance with the input data bit value, and the output of the twentieth logic element L20. Becomes 0, so that the output value of the twenty-first logic element L21, that is, the output value of the data selecting means 1115 and the auxiliary data selecting means 1115 ', becomes the data bit value. As a result, each data bit value is stored in the lower data storage means 1116 and the auxiliary data storage means 1116 'as it is.

In the case of the header flit, since the least significant 3 bits indicate routing information, the lower data storage means 1116 outputs the least significant 3 bits information to the output port arbitration unit 120.

In addition, 23 bits of data excluding the lower 3 bits are outputted to the data movement path setting unit 130, and the upper 3 bits of the routing information field are set by the auxiliary data selecting means 1115 'having 0 as the input data bit value. It will be filled with zeros. The data type fields 21 to 22 and the source address fields 15 to 20 are stored in the upper data storage unit 1116 ″ as the original data is intact.

On the other hand, when the payload flit is input, since the shift request signal Shift_r is inactive, the output value of the nineteenth logic element L19 constituting the data selection means 1115 and the auxiliary data selection means 1115 'becomes zero. The output value of the twentieth logic element L20 is the data bit value on the right side of the three bits (in the case of the lowest three data selection means, the output value of the data storage means connected to each).

In this case, the values stored in the lower three data storage means 1116 are not used in the case of a payload flit, and the values stored in the top 23 data storage means 1116 are output as actual data. Specifically, the 0th bit to the 14th bit of the actual input data are shifted left by 3 bits and stored in the lower data storing means 1116, and the auxiliary data storing means 1116 'from the 15th bit to the 17th bit. ), The 18th bit to the 22nd bit are directly transmitted to the upper data storage means 1116 and stored, and then output to the data movement path setting unit.

The configuration and operation of the data input unit 110 have been described above, and the output port arbitration unit 120 will be described below.

12 is a detailed configuration diagram of the output port arbitration unit applied to the present invention.

As shown, the output port arbitration unit 120 receives the arbitration request signals Arb_req0 to Arb_req5 and routing information ribs of the data from the data input unit 110 for data input to each input port. First to sixth demultiplexers DM0 to DM5 for determining a transmission path of the arbitration request signal, and receiving a header flit processing request signal H_r for data input through each input port, and transmitting each header flit processing request signal. The seventh to twelfth demultiplexers DM6 to DM11 for determining a path, and receive a last payload processing request signal L_r for data input to each input port to determine a transmission path of each last payload storage completion signal. To generate the arbitration request response signal Arb_ack according to the arbitration request signal Arb_req input from the thirteenth to eighteenth demultiplexers DM12 to DM17 and the first to sixth demultiplexers. Mediation means 1200 for generating an output port selection signal s for the data packet to be output to one port, and data according to the arbitration request response signal Arb_ack and the selection signal s generated by the arbitration means 1200. The first to sixth multiplexers M0 to M5 transmitting the arbitration result Arb_ack to the input unit 110 are included.

Output port arbitration for data packets input to four lower ports and two upper ports from the data input unit 110 is performed in four lower arbitration modules and two upper arbitration modules, respectively, which are illustrated in FIG. 13.

FIG. 13 is a block diagram of an output port arbitration unit applied to the present invention and shows four lower arbitration modules 121, 122, 123, and 124 and two upper arbitration modules 125 and 126.

Referring to the difference between the lower arbitration modules 121, 122, 123, and 124 and the upper arbitration modules 125, 126, the lower arbitration modules 121, 122, 123, and 124 select one of the six output ports. Since the upper arbitration modules 125 and 126 should transmit data only to the upper output port, one of the four output ports is selected. In the arbitration request signal input to each arbitration module (for example, Arb_req00 ~ 50 for lower arbitration module 0), the first digit (0-5) represents the input port information, and the second digit (0) is output. Show port information. That is, the arbitration module determines output priorities by dividing the data to be output to the same output port.

FIG. 14 is a detailed configuration diagram of the lower arbitration module illustrated in FIG. 13, and FIG. 15 is a detailed configuration diagram of the upper arbitration module illustrated in FIG. 13. The lower and upper arbitration modules may have only a difference in the number of selectable output ports. Only the same operation will be described together.

The lower and upper arbitration modules 121 and 125 select one of the plurality of arbitration request signals Atb_req0 to Atb_req5 or Atb_req0 to Atb_req3, that is, to select any one of a plurality of data to be output to the same output port. Arbitration units 1211 and 1251 comprising a 6-by-1 tree arbiter for the case, if the arbitration request response signal Arb_ack is activated by the arbitration unit 1211, the output path is maintained until all of the corresponding data packets are transmitted. In order to prevent the 6-by-1 tree arbiter from operating, the multiplexer selection control signal en for controlling the multiplexer selection signal to be outputted when the last payload is input and the last payload processing request signal L_r is activated. Of the multiplexer selection control signal en and the arbitration unit 1211 of the wormhole routing processing units 1212 and 1252 and the wormhole routing processing units 1212 and 1252 for outputting Routing control units 1213 and 1253 for outputting multiplexer selection signals s0 to s2 or s0 to s1 in accordance with the arbitration result.

FIG. 16 is a detailed block diagram of the 6-by-1 tree arbiter shown in FIG. 14.

As shown, the 6-by-1 tree arbiter may be configured by connecting a plurality of 2-by-1 tree arbiters. That is, the first to third 2-by-1 tree arbiters 1214, 1215, and 1216 which receive two expressions from each of the six arbitration request signals and select one of the two arbitration request signals, and the first and the second. A fourth 2-by-1 tree arbiter 1217 which selects one of the outputs of the two 2-by-1 tree arbiters 1214 and 1215, and a third 2-by-1 tree arbiter 1216 And a fifth 2-by-1 tree arbiter 1218 for selecting any one of an output of the fourth 2-by-1 tree arbiter 1217, and a fifth 2-by-1 tree arbiter 1218. And a buffer 1219 for temporarily storing and outputting the output value.

A reset signal resetb is input to each 2-by-1 tree arbiter, and two arbitration request signals r0 and r1 and an output response signal g are input to one arbitration request signal r and two Output the arbitration request response signals g0 and g1.

In addition, the 4-by-1 tree arbiter applied to FIG. 15 has a structure similar to that of FIG. 16 although not shown.

That is, the 4-by-1 tree arbiter may be configured by connecting a plurality of 2-by-1 tree arbiters. That is, the sixth and seventh 2-by-1 tree arbiters which receive two expressions from each of the four arbitration request signals and select one of the two arbitration request signals, and the sixth and seventh 2-by-1 tree arbitrations. And an eighth 2-by-1 tree arbiter for selecting any one of the output values and a buffer for temporarily storing and outputting the output values of the eighth 2-by-1 tree arbiter.

FIG. 17 is a detailed configuration diagram of the 2-by-1 tree arbiter illustrated in FIG. 16 and illustrates an example of selecting one of two arbitration request signals r0 and r1.

Before explaining the operation of the 2-by-1 tree arbiter shown in FIG. 17, an ME circuit L22 that selects one of two signals that are simultaneously input and selects the remaining signals when the selected signal becomes low. ) Will be described with reference to FIG. 18.

As shown in FIG. 18, the ME circuit L22 is driven by a signal inverting the first input signal r0 and receives an eighth N-type transistor (receiving a signal inverting the second input signal r1). N8) connected to an eighth N-type transistor in series and driven by an inverted signal of the eighth P-type transistor P8 and the second input signal r1 driven by a signal inverting the first input signal r0. Is driven and is connected in series between a ninth N-type transistor N9, a ninth N-type transistor, and an eighth P-type transistor that receive a signal inverting the first input signal r0, and receives the second input signal r1. A ninth P-type transistor P9 driven by the inverted signal, the output of the eighth N-type transistor N8 becomes the first output signal g0, and the ninth N-type transistor N9 The output becomes the second output signal g1.

In the ME circuit L22 having such a configuration, for example, when the first input signal r0 is 1 and the second input signal r2 is 0, the eighth N-type transistor N8 and the ninth P-type The transistor P9 is turned off, the ninth N-type transistor N9 and the eighth P-type transistor P8 are turned on, so that the first output signal g0 becomes 1 and the second output signal g1 It becomes zero. That is, when the input signal is 1 and the second input signal is 0, the first input signal is selected.

Referring to the ME circuit L22, the configuration and operation of the 2-by-1 tree arbiter shown in FIG. 17 will be described as follows.

As shown, as two arbitration request signals r0 and r1 are input to the ME (Mutual Exclusion) circuit L22, the ME circuit L22 receives the first output signal r0out and the second output signal r1out. Select and output any one of). When the twenty-third logic element L23 receives a reset signal, an inverted value of the output terminal response signal g, and an output signal of the twenty-fourth logic element L24, both input values of the previous state are zero. It outputs 0 and if any input value is 0, it keeps outputting 0. If all input values are 1, it outputs 1, and if any input value is 1, it keeps outputting 1. The signal g is a response signal transmitted from the output signal receiving end of the 2-by-1 tree arbiter. When this signal is input as 1, the output signal of the twenty-third logic element L23 becomes 0, and the signal inverted thereof. That is, the second arbitration request response signal g1 becomes one. Therefore, the output value of the 25th logic element L25 which inputs the 2nd output signal r1out of the ME circuit L22 and the 2nd arbitration request response signal g1 becomes 1.

On the other hand, the output of the twenty-sixth logic element L26 which receives the reset signal resetb, the inverted value of the output terminal response signal g, and the output signal of the twenty-fifth logic element L25 becomes 0, and the inverted signal is zero. That is, the first arbitration request response signal g0 is 1. Therefore, the output value of the twenty-fourth logic element L24 that takes the first arbitration request response signal g0 and the first output signal r0out of the ME circuit L22 as an input value becomes zero. In addition, the output value r of the twenty-seventh logic element L27 that receives the output signals of the twenty-fourth logic element and the twenty-fifth logic elements L24 and L25 is one. That is, the first input signal r0 is selected.

In FIG. 17, the twenty-third and twenty-sixth logic elements L23 and L26 are the above-described C-element elements, and the twenty-fourth and twenty-seventh logic elements and the twenty-seventh logic elements L24, L25 and L27 have both inputs 1. In this case, the device outputs 0, and may be implemented as, for example, a NAND gate.

In the above, the detailed configuration and operation of the output port arbitration unit applied to the asynchronous switch circuit of the present invention have been described. Hereinafter, the detailed configuration and operation of the data movement path setting unit 130 applied to the present invention will be described.

19 is a detailed configuration diagram of a data movement path setting unit applied to the present invention.

The data movement path setting unit 130 receives 23 bits of data from the data input unit 110, receives output port information (output port selection signal) from the output port arbitration unit 120, and sends data to the corresponding output port. As shown in FIG. 19, four lower movement path setting units 131, 132, 133, and 134 and two upper movement path setting units 135 and 136 are provided.

Six data (In0 <22: 0> to In5 <22: 0>) having a size of 23 bits are input to the lower movement path setting unit 131, 132, 133, and 134, and the upper movement path setting unit 135 136 inputs four pieces of data In0 <22: 0> to In3 <22: 0> having a size of 23 bits. This is because the lower movement path setting unit transmits data to any one of six output ports, and the lower movement path setting unit transmits data to any one of four upper output ports.

Each movement path setting unit 131 ˜ 136 receives data while the selection signals s0 <2: 0> to s3 <2: 0> and s4 <1: 0> transmitted from the output port arbitration unit 120. , s5 <1: 0>), and transmits specific data to the output port indicated by the selection signal (out0 <22: 0> to out5 <22: 0>).

FIG. 20 is a detailed configuration diagram of the lower movement path setting unit shown in FIG. 19, and FIG. 21 is a detailed configuration diagram of the upper movement path setting unit shown in FIG. 19, and the lower movement path setting unit and the upper movement path setting unit are input data. Since the number of and the number of selection signals are different, they have the same configuration, which will be described together.

The 23 bit data bit values constituting one data fleet are inputted into 23 multiplexers (multiplexer 10 to multiplexer 122) one bit each. In the lower movement path setting unit 131, 132, 133, and 134, since six data flits are input, for example, the multiplexer 10 has a 0 th bit data value (In0 <0>) of the first data and a second data. 0th bit data value (In1 <0>), ... 0th bit data value (In5 <0>) of the 6th data is inputted. In addition, in the upper movement path setting unit 135 and 136, since four pieces of data are input, for example, the multiplexer 20 includes a 0 th bit data value (In0 <0>) of the first data and a 0 th of the second data. Bit data value (In1 <0>),... The 0 th bit data value In3 <0> of the fourth data is input.

In addition, a selection signal s is input to each of the multiplexers M10 to M122 and M20 to M222. In the case of the lower movement path setting units 131, 132, 133, and 134, three selection signals are used to indicate six output ports. (s0, s1, s2) are input, and in the case of the higher movement path setting units 135, 136, two selection signals (s0, s2) are input to indicate four output ports.

Each of the multiplexers M10 to M122 and M20 to M222 that receive the data and the selection signal has six input data in the case of the lower movement path setting unit 131, 132, 133, and 134 under the control of the selection signal s. Any one of them is selected and output, and the upper movement path setting units 135 and 136 select and output any one of four input data. The 23-bit data out <22: 0> output in this manner is transmitted to the data output unit 140.

Since the selection signal s is preset in the output port arbitration unit 120, the data bit strings of the same data flits are transmitted to the data output unit 140, and each bit string is selected in each multiplexer. Since the data is transmitted afterwards, the data transmission speed is improved.

In order to select any one of the six input signals according to the control of the selection signal from the lower movement path setting units 131, 132, 133, and 134, each of the multiplexers M10 to M122 uses 6-by-1 TG ( Transmission Gate) may be implemented as a multiplexer, and the multiplexers M20 to M222 for applying to the upper movement path setting units 135 and 136 may be implemented as a 4-by-1 TG multiplexer, which is described with reference to FIGS. 22 and 23. The description is as follows.

FIG. 22 is a detailed configuration diagram of the 6-by-1 TG multiplexer shown in FIG. 20.

As shown in FIG. 22, the 6-by-1 TG multiplexer receives each data bit in0 to in5 and is controlled by the inverted signal of the third select signal s2 and the third select signal s2. The first to fifth transfer gates TG0 to TG5 and the output signals of the first to fifth transfer gates TG0 to TG5 are input signals, respectively, and the second selection signal s1 and the second selection signal s1 are input signals. The sixth to twelfth transfer gates TG6 to TG11 and the sixth to twelfth transfer gates TG6 to TG11 that are controlled by the inverted signal of?) Are input signals, and the first select signal s0 and the first select. And thirteenth to eighteenth transfer gates TG12 to TG17 controlled by the inverted signal of the signal s0 to output any one of the input data in0 to in5.

Meanwhile, the 4-by-1 TG multiplexer shown in FIG. 23 receives respective data bits in0 to in3 and is controlled by the inversion signal of the second selection signal s1 and the second selection signal s1. Output signals of the 19th to 22nd transmission gates TG18 to TG21 and the 19th to 22nd transmission gates TG18 to TG21 are used as input signals, respectively, and the first selection signal s0 and the first selection signal s0. The twenty-third to twenty-sixth transmission gates TG22 to TG25 controlled by the inverted signal of U and outputting any one of the input data in0 to in3 are included.

As such, the data movement path setting unit 130 accurately transmits the input data to the data output unit 140 according to the output port information generated by the output port arbitration unit 120.

Next, the data output unit 140 applied to the asynchronous switch circuit according to the present invention will be described in detail.

24 is a detailed configuration diagram of a data output unit applied to the present invention.

The data output unit 140 may include header storage request signals Datah_r0 to Datah_r5 and payload storage request signals Datap_r0 to Datap_r5 and output port information input from the output port arbitration unit 120 transmitted from the data input unit 110. In response to the selection signals s0 <2: 0> to s5 <2: 0>, an input control unit 141 and a reset signal resetb are requested to store data in the corresponding output buffer, and a data input unit ( According to the input data (in0 <22: 0> to in5 <22: 0>) transmitted from 110 and the data transmission request signal (input_req) input from the input control unit 141, the data is stored in the corresponding output port, and the data When the saving is completed, the data transmission request response signal (input_ack) is transmitted to the output port arbitration unit 120, and an output request signal (output_req) for notifying the next stage switch that there is data to be output is output, and the next stage switch. Responds to this by output_ack A data transmission request signal (input_ack0 to input_ack5) is received from the buffer 142 and the buffer 142 that outputs data (out0 <22: 0> to out5 <22: 0>) to the next switch through the output port. The data input unit 110 receives the header storage request signals Datah_r0 to Datah_r5 and the payload storage request signals Datap_r0 to Datap_r5, and output port information s0 <2: 0 input from the output port arbitration unit 120. and an output control unit 143 which receives the> ~ s5 <2: 0> and transmits the header storage completion signal Datah_a0 to Datah_a5 and the payload storage completion signal Datap_a0 to Datap_a5 to the data input unit 110. .

Here, the data output unit 140 may further include a delay means 144 for delaying the output request signals output_req0 to output_req5 output from the buffer 142 for a predetermined time and then outputting them to the next stage switch. . This delay means 144 is used to ensure proper timing of signal transmission since the switch circuit of the present invention is an asynchronous circuit.

FIG. 25 is a detailed configuration diagram of the input control unit shown in FIG. 24.

As shown, the input control unit inputs a header storage completion signal and a payload storage completion signal for each data, and outputs 1 when any one of the input signals is 1 (L28 to L33). The first to sixth multiplexers M30 to M35 may be implemented using the output signals of the first and sixth multiplexers M30 to M35, and the selection signals s0 <2: 0> to s5 <2: 0> may be used as the multiplexers M30 to M35. Are respectively input, and any one of the data transfer request signals Input_req0 to Input_req5 is activated by the control of the selection signals s0 <2: 0> to s5 <2: 0>.

Here, each of the multiplexers M30 to M35 may be implemented as a 6-by-1 TG (Transmission Gate) multiplexer, and a specific configuration example is illustrated in FIG. 22. In addition, the twenty-eighth to thirty-third logic elements L28 to L33 may be implemented as an OR gate. The data output unit 140 may distinguish whether the data input to the input controller 141 is a header or a payload. Because there is no need.

FIG. 26 is a detailed configuration diagram of the buffer shown in FIG. 24.

The buffer 142 applied to the present invention may be used by connecting two two-phase first-in first-out buffers (2 stage FIFOs, 1421 to 1426) in parallel.

A reset signal resetb is input to each of the two-phase first-in first-out buffers 1421 to 1426, and input data in transmitted from the data input unit 110 and a data transmission request signal input_req input from the input control unit 141. Data is stored in the corresponding output port, and when the data storage is completed, the data transmission request response signal input_ack is transmitted to the output port arbitration unit 120.

In addition, it outputs an output request signal (output_req) that notifies the next stage switch that there is data to be outputted, and as the next stage switch responds to this (output_ack), the data is sent to the next stage switch through the designated output port. Output out.

FIG. 27 is a detailed configuration diagram of the two-phase first-in first-out buffer shown in FIG. 26 and shows that two semi-decoupled first-in first-out buffers 1427 and 1428 can be connected in series.

FIG. 28 is a detailed configuration diagram of the output control unit shown in FIG. 24.

As shown in the drawing, the output control unit 143 receives the data transmission request signal input_ack input from the buffer 142 and the selection signals s0 to s5 input from the output port arbitration unit 120 to the lower output port. First to fourth demultiplexers DM20 to DM23 for generating control signals for data to be output, and fifth and sixth demultiplexers DM24 to DM25 for generating control signals for data to be output to the upper output port, 34th to 39th logic elements L34 to L39 and 34th to receive output values of the first to sixth demultiplexers DM24 to DM25 for each output port number, and output 1 when any one of the input signals is 1; The data is output according to the header storage request signal Datah_r and the payload storage request signal Datap_r, which are output values of the 39 th logic elements L34 to L39 as input values, and are input for each output port number from the data input unit 110. Into the buffer 142 The first to sixth decoders DC0 to DC5 for transmitting the header storage completion signal Datah_a and the payload storage completion signal Datap_a to notify the data storage unit 110 are included.

In FIG. 28, only signal lines for outputting data input to the first input port and data input to the fourth input port are illustrated, but the same signal lines may be represented for the other input data in the same manner.

In the above, the structure of the switch circuit by this invention was demonstrated.

In addition, the switch circuit of the present invention may further configure delay units 150 and 160 between the data input unit 110 and the output port arbitration unit 120 and between the data input unit 110 and the data output unit 140, respectively. Can be. This is implemented for the purpose of adjusting the timing since the switch circuit of the present invention is an asynchronous circuit.

The delay unit may be implemented in the form of a buffer chain in which a plurality of buffers are connected in series between an input terminal and an output terminal of a signal. In particular, the delay unit 150 connected between the data input unit 110 and the output port arbitration unit 120 may include a data input unit 110. ) Is used to delay the header flit processing request signal (H_r) transmitted to the output port arbitration unit (120). That is, the routing information (rib) is used to output faster than the header flit processing request signal (H_r).

On the other hand, the delay unit 160 connected between the data input unit 110 and the data output unit 140 is used to delay the header storage request signal Datah_r, and the data output unit in the data movement path setting unit 130 is used. It is used to synchronize the time at which data is sent out to the 140 and the header storage request signal Datah_r.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The present invention described above implements various intellectual property (IP) on one chip, implements a switch circuit that enables communication between IPs in a butterfly fat-tree topology, and implements data by wormhole switching technology. Transmission has the advantage of speeding up data processing on the network-on-chip and simplifying its configuration.

1 is a view for explaining an example of a general network on-chip structure,

2 is a conceptual diagram of an asynchronous switch circuit according to the present invention;

3 is a detailed configuration diagram of the asynchronous switch circuit shown in FIG. 2;

4A and 4B are diagrams for explaining a data format applied to the present invention;

5 is a detailed configuration diagram of a data input unit applied to the present invention;

6 is a detailed configuration diagram of a lower input processing module shown in FIG. 5;

FIG. 7 is a detailed configuration diagram of an upper input processing module shown in FIG. 5;

FIG. 8 is a detailed configuration diagram of the payload control unit illustrated in FIGS. 6 and 7;

9 is a detailed configuration diagram of the header control unit shown in FIGS. 6 and 7;

10A to 10C are diagrams illustrating an embodiment of a C-element circuit diagram and an asymmetric C-element circuit applied to the present invention;

11A and 11B are detailed configuration diagrams of the data storage unit shown in FIGS. 6 and 7;

12 and 13 is a detailed configuration diagram of the output port arbitration unit applied to the present invention,

14 is a detailed configuration diagram of the lower arbitration module shown in FIG. 13;

15 is a detailed configuration diagram of a higher arbitration module shown in FIG. 13;

16 is a detailed configuration diagram of the 6-by-1 tree arbiter shown in FIG. 14;

17 is a detailed block diagram of the 2-by-1 tree arbiter shown in FIG. 16;

18 is a detailed configuration diagram of the ME circuit shown in FIG. 17;

19 is a detailed configuration diagram of a data movement path setting unit applied to the present invention;

20 is a detailed configuration diagram of the lower movement path setting unit shown in FIG. 19;

FIG. 21 is a detailed configuration diagram of a higher movement path setting unit shown in FIG. 19;

FIG. 22 is a detailed configuration diagram of 6-by-1 TG MUX shown in FIG. 20;

FIG. 23 is a detailed configuration diagram of the 4-by-1 TG MUX shown in FIG. 21;

24 is a detailed configuration diagram of a data output unit applied to the present invention;

25 is a detailed block diagram of the input control unit shown in FIG. 24;

FIG. 26 is a detailed configuration diagram of the buffer shown in FIG. 24;

FIG. 27 is a detailed configuration diagram of the two-phase first-in first-out buffer shown in FIG. 26;

28 is a detailed configuration diagram of the output control unit shown in FIG. 24;

<Description of the symbols for the main parts of the drawings>

110: data input unit 120: output port arbitration unit

130: data movement path setting unit 140: data output unit

150 and 160: first and second delay units

111, 112, 113, 114: lower input processing module

115, 116: upper input processing module 1111, 1151: payload control unit

1112 and 1152: Header control unit 1113 and 1153: Data storage unit

1114, 1154: header fleet processing request signal generator

1115: data selector 1 115 ': auxiliary data selector

1116: lower data storage 1116 ': auxiliary data storage

1116 ": Upper data storage 121, 122, 123, 124: Lower arbitration module

125, 126: higher arbitration module 1211, 1251: arbitration unit

1212, 1252: Wormhole routing processing unit 1213, 1253: Path setting control unit

131, 132, 133, 134: lower movement path setting unit

135, 136: higher movement path setting unit 141: input control unit

142: buffer 143: output control unit

144 delay means

Claims (26)

An asynchronous switch circuit for a network on-chip application for delivering a plurality of data packets, the data packet consists of one header flit and at least one payload flit, A data input unit configured to receive a plurality of data flits and temporarily store the received data flits, and to determine whether the type of each data fleet is a header flit or a payload flit according to a data transmission request signal; An output for outputting an output port selection signal indicating an output priority of the data in response to receiving a header flit processing request signal, a last payload flit processing request signal, routing information of the header flit, and an arbitration request signal from the data input unit; Port arbitration; A data movement path setting unit for sequentially storing the data flits according to the data output priority determined by the output port arbitration unit; And Receives a header storage request signal and a payload storage request signal from the data input unit, temporarily stores a data flit inputted from the data movement path setting unit, and then outputs a header and payload storage completion signal indicating that the data flit is stored. A data output unit for transmitting to the data input unit and outputting the temporarily stored data flits to a designated port in a predetermined order; Asynchronous switch circuit comprising a. The method of claim 1, The asynchronous switch is composed of six input ports and six output ports each consisting of four lower ports and two upper ports, The data input unit may include four lower input processing modules configured to process data flits output to the lower output port or the upper output port; And An asynchronous switch circuit comprising two upper input processing modules for processing data flits output to the upper output port. The method of claim 2, The header flit includes a type field, a source address field and a routing information field, the payload flit includes a type field and a payload field, The lower and upper input processing modules temporarily store the header flit when the input data flit is a header flit, extract routing information from the routing information field included in the header flit, and transmit the routing information to the output port arbitration unit. A data storage unit configured to shift to the right side and to temporarily store the payload flit and to transmit it to the data movement path setting unit when the input data flit is a payload flit; Generates a control signal for processing the header flit, transmits an arbitration request signal and a shift request signal to the output port arbitration unit, transmits a header flit buffering request signal to the data storage unit, and responds to the header flit buffering response. A header control unit for receiving a signal and transmitting a header storage request signal to the data output unit and receiving a header storage completion signal that is a response signal; And Generates a control signal for processing the payload flit, transmits a payload flit buffering request signal to the data storage unit, receives a payload flit buffering response signal, which is a response signal, and stores the payload in the data output unit. A payload controller for transmitting a request signal and receiving a payload storage completion signal that is a response signal thereto; Asynchronous switch circuit comprising a. The method of claim 3, wherein The payload control unit may include: a delay element configured to delay a payload flit processing request signal by a predetermined time to generate a payload flit buffering request signal; When the payload storage request signal is received from the payload flit buffering response signal received from the data storage unit and the payload storage completion signal received from the data output unit, and both input values of the previous state are 0. A first logic element for outputting 0 and continuously outputting 0 when any one of input values is 0, outputting 1 when all input values become 1, and continuously outputting 1 when any one of input values is 1; And A second logic element configured to output an output signal of the first logic element and a payload flit buffering response signal and output 1 when both input values are 1; Asynchronous switch circuit comprising a. The method of claim 3, wherein The header control unit may include a third logic element configured to output 1 only when both input values are 0 by inputting the header flit processing request signal and the response signal to the arbitration request; Outputs the response signal to the header fleet processing request by using the output value of the third logic element and the header flit buffering response signal, and outputs 0 when both input values of the previous state are 0 and any one of the input values A fourth logic device for continuously outputting 0 when 0 is input, outputting 1 when all input values are 1, and continuously outputting 1 when any one of the input values is 1; A fifth logic device configured to output a header flit buffering request signal by inputting an inverted value of the fourth logic device and a response signal for a shift request, and outputting 1 only when both inputs are 1; When the output value of the fourth logic element and the inverted value of the fifth logic element output are input and both input values are 1, the output value of the sixth logic element that outputs 1 is the first input, and the fourth logic The inverted value of the device output and the output signal of the seventh logic element outputting 1 when both input values are 1 by inputting the header fleet processing request signal as the second inputs are 1 when the input values are all 0. An eighth logic element that outputs and maintains the output value as 1 when any one of the input values is 0 and outputs 0 when the input values are all 1 and maintains the output value as 0 when any one of the input values is 1; A ninth logic element for outputting a shift request signal by inverting an output value of the eighth logic element; When the inverted values of the header fleet processing request signal and the header storage completion signal are input and both input values are 0, the output value of the 10th logic element that outputs 1 is the first input, and the output value of the 4th logic element A twelfth logic element configured as a second input of an output value of an eleventh logic element that outputs 1 when the inverted value of the header fleet buffering request response signal and the header fleet processing request signal are input as 1; A thirteenth logic element inverting the output of the twelfth logic element, A fourteenth logic element configured to output an arbitration request signal using the output value of the thirteenth logic element as a first input and a response signal to the arbitration request as a second input; A fifteenth logic for setting a header save completion signal as a first input and outputting 1 when the input value is all 1 by inputting a response signal for the header fleet processing request signal, the arbitration request signal, and an inverted value of the header save completion signal; A sixteenth logic element having an output value of the element as a second input; And A seventeenth logic element for generating a header storage request signal by inverting the output of the sixteenth logic element; Asynchronous switch circuit comprising a. The method of claim 5, The fourth logic element includes a first P-type transistor connected to a power supply terminal and driven by a first input signal; A second P-type transistor connected in series with the first P-type transistor and driven by an inverted signal of a second input signal; A first N-type transistor connected in series with the second P-type transistor and driven by the first input signal; A second N type transistor connected in series between the first N type transistor and a ground terminal and driven by an inverted signal of the second input signal; A third P-type transistor connected between the power supply terminal and an output terminal of the second P-type transistor and driven by a reset signal; And A delay element connected to an output terminal of the second P-type transistor; Asynchronous switch circuit comprising a. The method of claim 5, The eighth, twelfth and sixteenth logic elements may include a fourth P-type transistor connected to a power supply terminal and driven by a third input signal; A fifth P-type transistor connected in series with the fourth P-type transistor and driven by an inverted signal of a fourth input signal; A third N-type transistor connected in series with the fifth P-type transistor and driven by the third input signal; A fourth N-type transistor connected in series between the third N-type transistor and a ground terminal and driven by an inverted signal of the fourth input signal; A fifth N-type transistor connected between the output terminal and the ground terminal of the fifth P-type transistor and driven by an inverted signal of a reset signal; And A delay element connected to an output terminal of the fifth P-type transistor; Asynchronous switch circuit comprising a. The method of claim 5, The fourteenth logic element includes a sixth P-type transistor connected to a power supply terminal and driven by a fifth input signal; A sixth N-type transistor connected in series with the sixth P-type transistor and driven by an inverted signal of the fifth input signal; A seventh N-type transistor connected in series between the sixth N-type transistor and a ground terminal and driven by a sixth input signal; A seventh P-type transistor connected between a power supply terminal and an output terminal of the sixth P-type transistor and driven by a reset signal; And A delay element connected to the output terminal of the sixth P-type transistor; Asynchronous switch circuit comprising a. The method of claim 3, wherein The data storage unit may receive a header flit buffering request signal and a payload flit buffering request signal as inputs and output a one when one of the two signals is 1; A plurality of data selecting means for inputting each of a plurality of lower bit values among the input data flits, a shift request signal, an inverted signal of the shift request signal, and a data bit value of an n bit right side; N auxiliary data selecting means for inputting a data bit value 0, a shift request signal, an inverted signal of the shift request signal, and a data bit to the right of n bits, respectively; A plurality of lower data storage means respectively connected to said data selecting means for inputting an output signal of said data selecting portion and an output signal of said eighteenth logic element to respectively store an output value of said data selecting means; N auxiliary data storage means connected to the auxiliary data selecting means, respectively, for storing an output value of the auxiliary data selecting means as an input signal of the auxiliary data selecting portion and an output signal of the eighteenth logic element; And A plurality of upper data storage means for storing the input data bit values by inputting each of the bit strings except the data bit string input to the data selecting means and the output signal of the eighteenth logic element among the input data bits; ; Asynchronous switch circuit comprising a. The method of claim 9, When the data flit is 23 bits, the header flit includes a 2-bit type field, a 6-bit source address field and a 15-bit routing information field, and the payload flit includes a 2-bit type field and a 21-bit payload. And a load field, wherein data bits of lower 15 bits are input to the data selection means. The method of claim 9, The data selector and the auxiliary data selector include a nineteenth logic element configured to output a 1 when both inputs are 1 by inputting a shift request signal and a data bit value; A twentieth logic element configured to output an inverted signal of the shift request signal and a data bit value to the right of n bits and output 1 when both inputs are 1; And A twenty-first logic element configured to output one when the input values of the nineteenth and twentieth logic elements are input to one of the two input values; Asynchronous switch circuit comprising a. The method of claim 1, The asynchronous switch is composed of six input ports and six output ports each consisting of four lower ports and two upper ports, The output port arbitration unit may include four lower arbitration modules for processing data flits outputted to a lower output port or an upper output port; And An asynchronous switch circuit comprising two upper arbitration modules for processing data flits output to the upper output port. The method of claim 12, The lower arbitration module and the upper arbitration module may include an arbitration unit for selecting any one of a plurality of data to be output to the same output port and outputting a response signal to the arbitration request signal; The output path selection signal is maintained until one data packet including a header flit and at least one payload flit is outputted to the data output unit, and a last payload flit processing request signal is inputted from the data input unit. A wormhole routing processing unit for outputting a control signal for outputting the signal; And A path setting control unit outputting the output port selection signal in accordance with a control signal output from the wormhole routing processing unit and an arbitration request response signal of the arbitration unit; Asynchronous switch circuit comprising a. The method of claim 13, The arbitration unit of the lower arbitration module consists of a 6-by-1 tree arbiter, The 6-by-1 tree arbiter receives first of two arbitration request signals from each of six arbitration request signals for each of six data packets to be output to the same output port and selects one of two arbitration request signals. 2-by-1 tree arbiter; A fourth 2-by-1 tree arbiter for selecting any one of output values of the first and second 2-by-1 tree arbiters; A fifth 2-by-1 tree arbiter for selecting any one of the output values of the third 2-by-1 tree arbiter and the fourth 2-by-1 tree arbiter; And A buffer for temporarily storing and outputting an output value of the fifth 6-by-1 tree arbiter; Asynchronous switch circuit comprising a. The method of claim 13, The arbitration unit of the higher arbitration module consists of a 4-by-1 tree arbiter, The 4-by-1 tree arbiter receives six expressions of four arbitration request signals for each of six four data packets to be output to the same upper output port, and selects one of two arbitration request signals; Seventh 2-by-1 tree arbiter; An eighth 2-by-1 tree arbiter for selecting any one of an output value of the sixth 2-by-1 tree arbiter and the seventh 2-by-1 tree arbiter; And A buffer for temporarily storing and outputting an output value of the eighth 6-by-1 tree arbiter; Asynchronous switch circuit comprising a. The method of claim 1, The asynchronous switch is composed of six input ports and six output ports each consisting of four lower ports and two upper ports, The data movement path setting unit includes four lower movement path setting units for processing data flits output to the lower output port or the upper output port; And An asynchronous switch circuit comprising two upper moving path setting units for processing data flits output to the upper output port. The method of claim 16, The lower movement path setting unit and the upper movement path setting unit include multiplexers having the same number of data bits as one data fleet. The multiplexer receives a data bit value of 1 bit from each of the plurality of data flits input from the data input unit, receives an output port selection signal from the output port arbitration unit, and specifies a data bit designated by the output port selection signal. And outputting the respective output to the data output unit. The method of claim 16, And said multiplexer comprises a transmission gate multiplexer. The method of claim 1, The asynchronous switch is composed of six input ports and six output ports each consisting of four lower ports and two upper ports, The data output unit receives a header storage request signal and a payload storage request signal transmitted from the data input unit, an output port selection signal input from the output port arbitration unit, and outputs a data fleet to an output buffer designated by the output port selection signal. An input control unit which requests to store Storing data in the output port according to a plurality of data flits transmitted from the data input unit and a data transmission request signal input from the input control unit, and when data storage is completed, transmitting a data storage completion signal to the output port arbitration unit, A buffer for outputting an output request signal indicating that there is data to be output to a switch of a next stage, and outputting the data fleet with reference to the output port selection signal as the next stage switch responds to the output request signal; And Receives a data storage completion signal from the buffer, receives a header storage request signal and a payload storage request signal from the data input unit, receives an output port selection signal from the output port arbitration unit, and completes header storage to the data input unit. An output controller for transmitting a signal and a payload storage completion signal; Asynchronous switch circuit comprising a. The method of claim 19, And the data output unit further includes delay means for delaying the output request signal output from the buffer for a predetermined time and then outputting the signal to the next stage switch. The method of claim 19, The input control unit may include: a twenty-eighth to thirty-third logic element configured to input a header storage completion signal and a payload storage completion signal for each data fleet and output one when any one of the input signals is 1; And First to be connected to the twenty-eighth to thirty-third logic elements, respectively, the output signal of the twenty-seventh to thirty-third logic elements being an input signal, and activating any one of a data storage request signal by controlling the output port selection signal To sixth multiplexer; Asynchronous switch circuit comprising a. The method of claim 21, And the first to sixth multiplexers comprise a transmission gate multiplexer. The method of claim 19, And the buffer is configured by connecting a plurality of two-phase first-in, first-out buffers in parallel. The method of claim 19, The output controller receives the data storage completion signal input from the buffer and the output port selection signal input from the output port arbitration unit and generates first to fourth demultiplexers for generating a control signal for data to be output to the lower output port. ; Fifth and sixth demultiplexers for generating control signals for data to be output to an upper output port; A thirty-fourth to thirty-ninth logic device that receives the output values of the first to sixth demultiplexers for each output port number, and outputs 1 when any one of the input signals is 1; And An output value of the 34 th to 39 th logic elements is used as an input value, and a notification is provided that the data flits are stored in the buffer according to a header storage request signal and a payload storage request signal inputted by each output port number from a data input unit. First to sixth decoders for transmitting a header storage completion signal and a payload storage completion signal to the data input unit; Asynchronous switch circuit comprising a. The method of claim 1, And the asynchronous switch circuit further comprises a first delay section for delaying the header flit processing request signal for a predetermined time between the data input section and the output port arbitration section. The method of claim 1, The asynchronous switch circuit further comprises a second delay unit for delaying the header storage request signal for a predetermined time between the data input unit and the data output unit.