WO2016056389A1

WO2016056389A1 - Frequency synthesizer

Info

Publication number: WO2016056389A1
Application number: PCT/JP2015/076896
Authority: WO
Inventors: 出村博之; 小林薫
Original assignee: 日本電波工業株式会社
Priority date: 2014-10-08
Filing date: 2015-09-24
Publication date: 2016-04-14

Abstract

Provided is a frequency synthesizer capable of high-speed switching and having few unwanted frequency components in the output frequency signal. In this frequency synthesizer (1), a direct digital synthesizer (DDS) (2) operating on the basis of a clock signal generates a reference frequency signal having a prescribed reference frequency, and clock signal supply units (41, 42) are switched to supply clock signals having a different clock frequency to the DDS (2). A storage unit (12) stores, in association with the output frequency (f_VCO) from the frequency synthesizer (1), combinations of clock frequencies (f_clk), reference frequencies (f_c), and division numbers (N) for which spurious frequencies do not exist within a preset frequency range and the division number of a variable frequency divider (302) provided in a PLL circuit (3) is the smallest when the DDS (2) is operated by switching the clock signal. Setting units (11, 24) read the setting items stored in the storage unit (12), and perform settings in each unit.

Description

Frequency synthesizer

The present invention relates to a frequency synthesizer including a PLL circuit that performs phase comparison with a reference frequency signal generated using a DDS (Direct Digital Synthesizer) and outputs a frequency signal from a voltage controlled oscillator.

The frequency synthesizer divides the frequency signal output from the voltage controlled oscillator with a frequency divider, and extracts the phase difference between the phase of the divided frequency signal and the phase of the reference frequency signal with a phase comparator, A PLL (Phase Locked Loop) circuit that feeds back a control voltage corresponding to the phase difference to the voltage controlled oscillator via a loop filter is provided, and a stable frequency signal is output using the PLL circuit. A frequency signal with a desired frequency can be output by variously changing the frequency dividing number of the frequency divider and the frequency dividing number of the frequency divider provided on the reference frequency signal side. *

As a technique for switching the frequency of the frequency signal output from the above-described frequency synthesizer at high speed, there is a technique for increasing the frequency of the reference frequency signal. However, when a high-frequency reference frequency signal is used, the step width of the output frequency that is switched according to the frequency division number of the frequency divider becomes large, and fine frequency adjustment cannot be performed. *

Therefore, as a technique that enables fine frequency adjustment while supplying a high-frequency reference frequency signal to a frequency synthesizer, there is a technique that uses a DDS (Direct Digital Synthesizer) as a signal source of the reference frequency signal. The DDS is a device that obtains a frequency signal of a desired frequency by reading amplitude data from a waveform table based on phase data output according to the input timing of a clock signal. By using the signal generated by the DDS as a reference frequency signal, high-speed switching can be realized while finely changing the frequency of the frequency signal output from the frequency synthesizer. *

However, the frequency signal output from the DDS includes a spurious component, and this spurious component is a factor that degrades the quality of the frequency signal output from the frequency synthesizer. There are various causes for the generation of spurious components. As one of them, the harmonic component generated due to the frequency (clock frequency) of the clock signal that operates the DDS is included in the frequency band of the DDS as aliasing. May appear. *

Here, in Patent Document 1, in a frequency synthesizer using DDS, a program frequency divider is provided between a reference oscillator that generates a clock signal and the DDS, and a spurious frequency is calculated in advance according to the output frequency Fo of the DDS. A configuration is described in which the frequency division of the program frequency divider is set so that a clock signal whose spurious frequency does not exist within a preset frequency range is supplied to the DDS.

JP-A-8-256058: paragraphs 0024, 0026, 0029, FIG.

In the frequency synthesizer described in Patent Document 1, the spurious generation position included in the output of the DDS can be adjusted by changing the frequency of the clock signal supplied to the DDS by the program frequency divider. As a result, for example, a spurious having a frequency sufficiently higher than the loop band of the loop filter provided in the frequency synthesizer is generated, and this spurious is removed by the loop filter. *

However, unnecessary frequency components included in the frequency signal that is the output of the frequency synthesizer using DDS are not limited to the above-described harmonic spurious components, and may be caused by, for example, the configuration of the frequency synthesizer. For this reason, when changing the frequency of the clock signal supplied to the DDS, it is necessary to take comprehensive measures in consideration of the influence on these other factors.

The present invention has been made under such circumstances, and an object of the present invention is to provide a frequency synthesizer in which the output frequency can be switched at high speed and there are few unnecessary frequency components in the output frequency signal. .

The frequency synthesizer according to the present invention divides the frequency signal output from the voltage controlled oscillator by the variable frequency divider, and compares the phase difference between the phase of the divided frequency signal and the phase of the reference frequency signal. In a frequency synthesizer including a PLL circuit that supplies a control voltage corresponding to the phase difference from a loop filter to the voltage controlled oscillator.
A reference frequency that operates based on a clock signal and has a reference frequency corresponding to a value obtained by dividing the set value of the output frequency of the frequency signal output from the voltage controlled oscillator by the frequency division number set in the variable frequency divider A DDS for generating a signal;
A clock signal supply unit for supplying a clock signal according to a clock frequency selected from a plurality of clock frequencies prepared in advance to the DDS;
When the DDS is operated by a clock signal having a clock frequency selected from the plurality of clock frequencies and a reference frequency signal having the reference frequency is generated from the DDS, a spurious component included in a use frequency band of the DDS The reference frequency at which the frequency of the variable frequency divider does not exist within a preset frequency range and the frequency division number of the variable frequency divider is minimum is obtained in advance, and the clock frequency, the reference frequency, and the minimum frequency division number are obtained. And a storage unit for storing
A setting unit that selects a combination of a clock frequency, a reference frequency, and a minimum frequency dividing number corresponding to the set value of the output frequency and sets the clock signal supply unit, the DDS, and the variable frequency divider. It is characterized by that.

The frequency synthesizer described above may have the following features.
(A) When a frequency signal having a reference frequency associated with the minimum frequency division number is generated by the DDS, a frequency of a spurious component exists within a preset frequency range from the clock signal supply unit. When the clock signals having different clock frequencies can be supplied, the storage unit has the spurious component frequency generated due to the different clock frequencies in the neighborhood spurious component closest to the frequency range. A clock signal having a clock frequency that maximizes the absolute value of the difference between the upper and lower limit values of the frequency range and the frequency of the neighboring spurious component, and the reference frequency and the minimum frequency division number are stored in association with each other. thing.
(B) The DDS includes a DDS setting unit that sets a digital setting value corresponding to a reference frequency acquired from the setting unit and operates based on an operation clock supplied from the outside, and the clock signal supply unit includes: And a multiplier for multiplying the operation clocks by different multiplication numbers to prepare clock signals having the plurality of clock frequencies.
(C) The storage unit corresponds to a preset representative frequency included in each frequency range in association with the clock frequency and the minimum frequency division number for each of a plurality of preliminarily divided frequency ranges. A reference frequency is stored, a calculation unit for calculating which frequency range of the plurality of frequency ranges corresponds to a value in the frequency range, and a representative in the frequency range specified by the calculation unit Setting of the frequency based on a value obtained by dividing a difference value between the frequency and the set value of the frequency by the frequency dividing number set in the variable frequency divider and a reference frequency stored corresponding to the representative frequency And a generation unit for generating a reference frequency for the value.
(D) a digital / analog conversion unit that converts the frequency signal output from the DDS into an analog signal and outputs the analog signal, and the digital / analog conversion unit is based on the clock signal supplied from the clock signal supply unit. To work.

According to the present invention, the clock signal for operating the DDS is switched, and the reference frequency signal generated by the DDS is used for phase comparison of the PLL circuit to output the frequency signal from the frequency synthesizer. A combination of a clock frequency and a reference frequency that does not have spurious components in the surroundings and that minimizes the frequency dividing number of the variable frequency divider provided in the frequency synthesizer is selected. As a result, unnecessary frequency components in the frequency signal output from the frequency synthesizer are comprehensively reduced and the phase noise is optimized.

It is a block diagram which shows the whole structure of the frequency synthesizer which concerns on embodiment of this invention. It is a block diagram of a PLL circuit provided in the frequency synthesizer. It is a block diagram of DDS provided in the frequency synthesizer. It is explanatory drawing of the generation pattern of the spurious component resulting from a harmonic. It is explanatory drawing which concerns on the relationship between the generation position of a harmonic, and the calculation method of a spurious frequency. It is a table | surface which shows the 1st calculation example of a spurious frequency. It is a table | surface which shows the 2nd calculation example of a spurious frequency. It is a table | surface which shows the 3rd calculation example of a spurious frequency. It is a table | surface which shows the 4th example of calculation of a spurious frequency. It is an example of setting the reference frequency, the frequency division number of the variable frequency divider, and the clock frequency set in the memory in association with the channel. It is explanatory drawing which shows the procedure which determines each setting item. It is a block diagram of the frequency synthesizer which concerns on 2nd Embodiment. It is a block diagram of the calculation part provided in the said frequency synthesizer. It is a block diagram of the DDS setting data generation part provided in the frequency synthesizer. It is explanatory drawing of the data registered into the memory in the said frequency synthesizer.

The overall configuration of the frequency synthesizer 1 according to the embodiment of the present invention will be described with reference to FIGS.
The frequency synthesizer 1 includes a PLL circuit 3 provided with a VCO (Voltage Controlled Oscillator) 32 and a DDS 2 that supplies a reference frequency signal for phase comparison to the PLL circuit 3 and associates it with a plurality of channels. The frequency signal of the set frequency f _VCO can be output from the VCO 32.

As shown in FIG. 2, the PLL circuit 3 includes a VCO 32, a variable frequency divider 302 that divides the frequency signal output from the VCO 32 based on a preset frequency division number, and a reference frequency signal ( From the phase comparator 301 and the phase comparator 301 that compares the phase of the reference frequency f _c ) with the phase of the frequency signal divided by the variable frequency divider 302 and outputs a phase difference. A loop filter 31 that extracts a control voltage corresponding to the output phase difference and feeds it back to the VCO 32;

As shown in FIGS. 1 and 2, the phase comparator 301 and the variable frequency divider 302 of this example are provided in a common PLL-IC 30, and the variable frequency divider 302 is divided by the setting signal from the outside. N can be changed. *

As shown in FIG. 3, the DDS 2 cumulatively adds the digital set value F _DATA set corresponding to the output reference frequency f _c in accordance with the input timing of the clock signal f _clk supplied from the outside, and the reference frequency a phase accumulator 211 to output as the phase data of the signal f _c, the amplitude data of a sine wave is stored in association with the phase data, a sine wave table 212 for outputting amplitude data corresponding to the phase data obtained from the phase accumulator 211 , digital / analog converter for converting digital signals outputted from the sine wave table 212 into an analog signal (a DAC (digital analog Convertor) 22, a low pass filter for removing high frequency components included in the reference frequency signal f _c (hereinafter, 23) (referred to as “filter”).
As shown in FIGS. 1 and 3, the phase accumulator 211 and the sine wave table 212 of this example are provided in a common DDS signal processing unit 21.

For example, when the number of bits of the adder constituting the phase accumulator 211 is 20 bits (k = 20) and the digital value of the clock frequency is F _clk , the resolution D of the DDS2 is expressed by the following equation (1): The set value F _DATA can be obtained from equation (2). Here, F _c is a digital value of the reference frequency.
D = F _clk / (2 ²⁰ ) (1)
F _DATA = F _c / D
= F _c / (F _clk / (2 ²⁰ )) (2)

In general, the frequency signal generated by the DDS 2 is included as a aliasing noise spurious component of a harmonic component. Figure 4 illustrates the generation pattern of the spurious components due to harmonics of the reference frequency signal generated by DDS2 (reference frequency f _c). When operating the DDS2 by the clock signal of the clock frequency _{f clk,} use frequency band of the DDS2 is in the range of _{_{0 ≦ f c ≦ f clk /}} 2. In this use frequency band, aliasing of aliasing (n · f _c , where n = 2, 3,...) Of the reference frequency signal f _c (fundamental wave) appears as a spurious component.

In FIG. 4, the spurious component of the second harmonic (2f _c ) is generated at the position of the frequency f _clk −2f _c folded with reference to f _clk / 2 (in FIG. 4, the correspondence relationship between the frequencies before and after the folding is shown). It is indicated by a dashed line). Further, 3 spurious component of harmonic (3f _c) _is aliasing components of the frequency _2f clk -3f _c generated folded relative to the _{f clk} is further folded back relative to the _{f clk} / 2 in the frequency _-f clk + 3f It appears at the position _c (in FIG. 4, the correspondence relationship between the frequencies before and after the folding is indicated by a two-dot chain line).

In this way, considering the effect of aliasing at higher-order aliasing positions of “m · (f _clk / 2) (where m = 1, 2,...)”, The spurious component due to the effect of aliasing noise is, for example, Up to several hundreds of harmonics appear as spurious components in the frequency band used for DDS2.

The frequency (spurious frequency f _Sn ) of the spurious component of the harmonic generated in the range represented by the following equation (3) can be calculated by the following equation (4).
{(2m−1) / 2} · f _clk <n · f _c ≦ m · f _clk (3)
f _Sn = m · f _clk −n · f _c (4)
(However, m = 1, 2, 3,..., N = 2, 3,...)
In FIG. 5, the range corresponding to the expression (3) is shown in gray.

On the other hand, the harmonic spurious frequency generated in the range represented by the following equation (5) can be calculated by the following equation (6).
m · f _clk <n · f _c ≦ {(2m + 1) / 2} · f _clk (5)
f _Sn = n · f _c −m · f _clk (6)
(However, m = 1, 2, 3,..., N = 2, 3,...)
In FIG. 5, the range corresponding to the equation (5) is shown in white.

When the frequency dividing number of the variable frequency divider 302 is N and the phase of the frequency signal after frequency division by the PLL circuit 3 and the phase of the reference frequency signal are aligned (locked), the reference frequency f The relationship between _c and the output frequency f _VCO of the _VCO 32 is expressed by the following equation (7).
f _VCO = N · f _c (7)

According to the relationship of the expressions (3) to (7) described above, the clock frequency f _clk for operating the PLL circuit 3 and the variable frequency divider when the frequency synthesizer 1 outputs the frequency signal of the frequency f _VCO . knowing the frequency division number of 302, it is possible to know in advance the spurious frequency f _Sn based on the relationship between the clock frequency and the reference frequency f _c.
These relationships also mean that the generation position of the spurious frequency f _Sn can be changed by changing the clock frequency f _clk .

The frequency synthesizer 1 according to the present embodiment is configured to be able to switch the clock frequency f _clk of the clock signal supplied to the DDS 2 based on the above concept.
With respect to this configuration, as shown in FIG. 1, the DDS 2 includes a first changeover switch 25 that switches a clock signal supplied to the DDS signal processing unit 21 (phase accumulator 211), and a changeover setting of the first changeover switch 25. And a second changeover switch 26 for switching the clock signal supplied to the DAC 22 in accordance with the switching of the clock signal supplied to the DDS signal processing unit 21.

In the DDS 2 of this example, the first changeover switch 25 and the DDS control unit 24 on the DDS signal processing unit 21 side are provided in a DDS-IC 20 that is shared with the DDS signal processing unit 21. The DDS control unit 24, in addition to switching of the

first selector switch

25, 26 of the DDS signal processing unit 21, and DAC 22, a digital set corresponding to the reference frequency signal _{f c} to the phase accumulator 211 in the DDS signal processing unit 21 It has a function of outputting the value F _DATA and a function of outputting a reset signal for causing the DAC 22 to execute a reset operation.

As shown in FIG. 1, a clock signal having a clock frequency f _clk 0 is supplied to the DDS 2 as an operation clock. Then, the output obtained by multiplying the clock signal by multipliers (first multiplier 41 and second multiplier 42) having different multiplication numbers is switched by the first and second changeover switches 25 and 26. The DDS signal processing unit 21 (phase accumulator 211) and the DAC 22 are supplied.

In the present embodiment, for example, the clock frequency of the operation clock for the DDS control unit 24 is f _clk 0 = 40 MHz, and this clock signal is multiplied by 5 by the first multiplier 41 and the second multiplier 42, respectively. The clock signal having a clock frequency f _clk 1 = 200 MHz and f _clk 2 = 240 MHz is switched and supplied to the DDS 2.
The frequency source that supplies the clock signal having the clock frequency f _clk 0, the first and

second multipliers

41 and 42, and the first changeover switch 25 correspond to the clock signal supply unit of the present embodiment.

If the DDS2 capable of switching a plurality of clock signals is used, the frequency division number N of the variable frequency divider 302 and the clock frequency f _clk are appropriately changed based on the relationships of the above-described equations (3) to (7). are allowed, it is possible to determine the reference frequency f _c spurious frequency f _Sn due to harmonics within a predetermined frequency range are not present. And it can be output when operating the PLL circuit 3 performs phase comparison between the reference frequency signal with the reference frequency f _c, the less frequency signal effect of the spurious component from the frequency synthesizer 1.

On the other hand, the reference frequency according to f _c settings dividing number N is changed in the variable frequency divider 302, and in the frequency synthesizer 1 also changes the clock frequency f _clk for operating the DDS2, these frequency division number and the clock The inventors understand that the influence of the frequency on the frequency signal output from the frequency synthesizer 1 cannot be ignored.

For example, the phase noise level Noise [dBc / Hz] generated in the frequency synthesizer 1 is expressed by the following equation (8).
Noise = Noise (PLL) +10 · log (f c)
+ 20 · log (N) (8)
Here, Noise (PLL) is phase noise generated in the PLL-IC 30.

According to above-described (7), the frequency division number N of the variable frequency divider 302 is set for the frequency synthesizer 1, is in inversely proportional to the reference frequency f _c, the frequency division number (or As the reference frequency is increased, the reference frequency (or frequency division number) is decreased. On the other hand, the influence of accordance Invite frequency division number change (8), since come into play at 20x log (N), is better to choose a small frequency division number as possible, increasing the reference frequency f _c The effect of suppressing the influence of the phase noise caused by is great.

Based on this concept, the frequency synthesizer 1 according to the present embodiment has no spurious component within a preset range and a frequency division number corresponding to a channel indicating a predetermined output frequency _fVCO. A combination of the minimum clock frequency f _clk , reference frequency f _c , and frequency division number N is stored in the memory (storage unit) 12 in advance. Then, the control unit 11 provided in the frequency synthesizer 1 receives an input of the channel setting signal, selects a combination of the clock frequency f _clk , the reference frequency f _c , and the frequency division number N corresponding to the channel, The switch 25 is switched, the digital setting value F _DATA is set for the DDS signal processing unit 21, and the frequency division number is set for the variable frequency divider 302.
From this viewpoint, the control unit 11 and the DDS control unit 24 constitute a setting unit of the present embodiment.

Hereinafter, a setting example of the clock frequency f _clk , the reference frequency f _c , and the frequency division number N will be described with a simple example. Note that the following calculation examples show setting values for convenience in understanding the contents of the present invention, and do not show actual setting values.
6 to 9, the clock frequency f _{clk is set} to 200 (= f _clk 1) MHz, 240 (when the frequency signal of the output frequency f _VCO = 920 MHz, 960 MHz, 1000 MHz, 1040 MHz is output from the VCO 32. = F _clk 2) The frequency of the harmonic component from the second harmonic to the sixth harmonic (when the frequency dividing number N of the variable frequency divider 302 is changed to 20, 23, 26, 29) The upper cell) and the frequency of the spurious component of each harmonic (lower cell) are shown.

Here, in FIG. 6 to FIG. 9, cells in which the frequencies of the harmonic components generated in the range shown by the equation (3) (the range shown in gray in FIG. 5) are shown in gray. is there. Further, the preset frequency range is 48 ± 10 MHz, and the spurious frequencies included in this frequency range are underlined in the numbers in the table. *

In the example shown in FIG. 6 (f _VCO = 920 MHz), when the clock frequency f _clk 1 = 200 MHz, there is no spurious frequency within the frequency range of 48 ± 10 MHz at the frequency division number N = 20 and 26. In the case of the clock frequency f _clk 2 = 240 MHz, there is no spurious frequency within the frequency range at the frequency division number N = 26. Therefore, when the frequency division numbers selected according to the clock frequencies f _clk 1 and f _clk 2 are compared, the clock frequency f _clk 1 at which the frequency division number is minimum (N = 20) is selected. Then, the reference frequency f _c = 46.000 MHz is calculated based on the frequency division number N = 20 and f _VCO = 920 MHz.
As a result, the values of “clock frequency f _clk 1 = 200 MHz, reference frequency f _c = 46.000 MHz, frequency division number N = 20” are registered in the memory 12 as setting values corresponding to f _VCO = 920 MHz (FIG. 10 channels CH10).

On the other hand, in the example of FIG. 7 (f _VCO = 960 MHz) and FIG. 9 (f _VCO = 1040 MHz), the combination in which the spurious frequency does not exist within the frequency range and the frequency division number N is the minimum is the clock frequency. f _clk 2 is present on the side of 240 MHz (N = 23 in FIG. 7, N = 20 in FIG. 9).
As a result, as shown in the channel CH11 of FIG. 10, the setting values corresponding to f _VCO = 960 MHz are “clock frequency f _clk 2 = 240 MHz, reference frequency f _c = 41.739 MHz, frequency division number N = 23”. As shown in the channel CH13, “clock frequency f _clk 2 = 240 MHz, reference frequency fc = 52.000 MHz, frequency division number N = 20” is registered as a setting value corresponding to f _VCO = 1040 MHz.

Next, in the example of FIG. 8 (f _VCO = 1000 MHz), the spurious frequency does not exist within the frequency range at any of the clock frequencies f _clk 1 = 200 MHz and f _clk 2 = 240 MHz, and the frequency division number The frequency division numbers in the combination where N is the smallest are equal (N = 23). Therefore, in this case, the spurious frequency closest to the frequency range (neighboring spurious frequency) is compared, and the clock with the larger distance (absolute value of the frequency difference) from the upper limit value or lower limit value of the frequency range is selected. The frequency is adopted.

According to FIG. 8, when the clock frequency f _clk 1 = 200 MHz, the 6th-order spurious f _S6 = 60.870 MHz is closest to the upper limit value (58 MHz) of the frequency range. On the other hand, when the clock frequency f _clk 2 = 240 MHz, the fourth-order spurious f _S4 = 66.087 is close to the upper limit value (58 MHz) of the frequency range. The distance Δf (absolute value of the frequency difference) between these spurious components and the upper limit value or the lower limit value (upper limit value in this example) of the frequency range is larger than the clock frequency f _clk 2 = 240 MHz. (In the case of the clock frequency f _clk 1, Δf = 12.870 MHz, and in the case of the clock frequency f _clk 2, Δf = 18.087 MHz).
As a result, as shown in the channel CH12 of FIG. 10, “clock frequency f _clk 2 = 240 MHz, reference frequency fc = 43.478 MHz, frequency division number N = 23” is registered as a setting value corresponding to f _VCO = 1000 MHz. The

FIG. 11 summarizes the calculation procedure of the setting items (clock frequency f _clk , reference frequency fc, frequency division number N) registered in the memory 12 described above.
First, in accordance with the output frequency f _VCO from the frequency synthesizer 1, the spurious frequency when the reference frequency signal is generated from the DDS2 by changing the clock frequency f _clk and the frequency division number N of the variable frequency divider 302 is calculated. (Step P1).

Next, a combination of a clock frequency f _clk and a frequency division number N that does not have a spurious frequency within a preset frequency range and has a minimum frequency division number is selected (step P2). Further, when there are a plurality of combinations having the smallest frequency division number N, a clock frequency whose spurious frequency of the nearest spurious closest to the frequency range is farther from the upper limit value or the lower limit value of the frequency range is selected (step) P3).

Then, it calculates a reference frequency _{f c} from the frequency dividing number N of selected, these clock frequency _{f clk,} the reference frequency _{f c,} and minute combinations division number N in association with the output frequency _{f VCO} channel register (step P4 ).
As shown in FIG. 10, the memory 12 stores, for example, 100 channels of combinations of these setting items.

The operation of the frequency synthesizer 1 having the configuration described above will be described.
As shown in FIG. 1, the control unit 11 of the frequency synthesizer 1 accepts selection of a channel registered in the memory 12 from the outside, and reads a combination of setting items corresponding to the selected channel from the memory 12. Next, the control unit 11 sets the frequency division number of the variable frequency divider 302 for the PLL-IC 30 based on the read setting item, and also selects the selected clock frequency for the DDS control unit 24 of the DDS2. Information corresponding to f _clk and the reference frequency f _c is output.

The DDS control unit 24 performs switching between the first changeover switch 25 and the second changeover switch 26 based on the selected clock frequency f _clk . The DDS control unit 24 outputs to the phase accumulator 211 of the DDS signal processing unit 21 calculates the digital set value _{F DATA} corresponding to the reference frequency _{f c,} resets the DAC 22.

As a result, DDS2 is operated by the selected clock frequency _{f clk,} the reference frequency signal of the reference frequency _{f c} is output to the PLL circuit 3. In the phase comparator 301 of the PLL circuit 3, the phase comparison between the reference frequency signal and the output signal of the VCO 32 divided by the variable frequency divider 302 is performed, and feedback is made to the VCO 32 according to the magnitude of the phase difference. The controlled voltage is increased or decreased.

When the phase difference becomes substantially zero, the PLL circuit 3 is locked, and a frequency signal that is stable at the output frequency f _VCO and has few unnecessary frequency components is output from the VCO 32.
In the frequency synthesizer 1 having the DDS 2 according to the present embodiment, for example, even when the channel is switched every 30 to 40 microseconds, a frequency signal with a stable output frequency is output with a response time of about 20 to 30 microseconds. can do.

The frequency synthesizer 1 according to the present embodiment has the following effects. When a clock signal for operating the DDS 2 is switched and the reference frequency signal generated by the DDS 2 is used for phase comparison of the PLL circuit 3 and a frequency signal is output from the frequency synthesizer 1, a spurious component is generated around the reference frequency signal. And a combination of a clock frequency and a reference frequency that minimizes the frequency dividing number of the variable frequency divider 302 provided in the frequency synthesizer 1 is selected. As a result, unnecessary frequency components in the frequency signal output from the frequency synthesizer 1 are comprehensively reduced and the phase noise is optimized to be the lowest. *

Next, a frequency synthesizer 1a according to the second embodiment will be described with reference to FIGS. 12 to 14, the same reference numerals as those used in these drawings are attached to the same components as those of the frequency synthesizer 1 shown in FIGS.
The frequency synthesizer 1a according to the second embodiment has a frequency interval (for example, 1 kHz interval) smaller than the output frequency interval (for example, several tens MHz interval) set in association with each channel shown in FIG. The output frequency f _VCO of the _VCO 32 can be set.

Here, as described with reference to FIG. 10, the set value of the output frequency of the VCO 32 of each channel, the clock frequency f _clk selected corresponding to this set value, the reference frequency fc of DDS2, and the distribution of the PLL circuit 3 The frequency N is registered in the memory 12 in advance. However, for example, if these data are registered for all output frequencies selected at intervals of 1 kHz, the required capacity of the memory 12 becomes enormous.

As described with reference to FIGS. 5 to 9, each data registered in the memory 12 includes a reference frequency f _c (frequency obtained by dividing the output frequency f _VCO of the _VCO 32 by the frequency division number N) output from the DDS 2. It is determined based on the distance Δf between the spurious frequency _{f Sn} determined by the reference frequency _{f c} and the clock frequency _{f clk.} On the other hand, though (4) According to the formula of the spurious frequency f _Sn shown in formula or (6), in a large relatively low order spurious level, the reference frequency f _c is changed several kHz Also, the spurious frequency f _Sn does not change significantly.

Then, when the output frequency f _VCO of the _VCO 32 is gradually changed at intervals of 1 kHz, the selected clock frequencies f _clk 1, f _clk 2 and the value of the frequency division number N are changed according to the change of the output frequency f _VCO. You can see that it doesn't change. Actually, the clock frequencies f _clk 1 and f _clk 2 and the frequency division number N selected by the method described with reference to FIGS. 5 to 9 are coarser intervals of about several tens kHz to several hundreds kHz. It has been confirmed in advance that

According to this fact, even when the output frequency f _{VCO of the VCO} 32 is set at 1 kHz intervals, the clock frequencies f _clk 1 and f _clk 2 and the frequency division number N registered in the memory 12 are coarser than this. You may set by a frequency interval. Meanwhile, for the reference frequency f _c, in response to setting interval of the output frequency f _VCO, it is required to set at a high resolution.

Based on the concept described above, setting data of the clock frequencies f _clk 1 and f _clk 2 and the frequency division number N are registered in the memory 12 of the frequency synthesizer 1a of this example at intervals of 100 kHz (FIG. 15 ( a)). On the other hand, with the output frequency _{f VCO} of the set value of the VCO32 input at 1kHz intervals (designated frequency), the selection of these settings, and a frequency signal of the reference frequency _{f c} from the DDS2 corresponding to the designated frequency A digital set value F _DATA for output is generated.
In the following description, it is assumed that the clock frequency can be selected from f _clk 1 = 200 MHz and f _clk 2 = 240 MHz, and the frequency division number can be selected from N = 16, 20, 32, and 40.

In order to select each setting value and generate the digital setting value F _DATA , the frequency synthesizer 1a calculates the address of the memory 12 associated with each setting value described above from the specified frequency, and a calculation unit 13 for calculating the fractional frequency number used for generating a digital setting value _{F dATA,} includes a DDS setting data generator 14 for generating a digital setting value _{F dATA,} the.

First, the contents of various setting data registered in the memory 12 will be described with reference to FIG. For example, when an output frequency f _VCO from 1 MHz to several hundreds of MHz can be specified at 1 kHz (0.001 MHz) intervals, the memory 12 corresponds to the output frequency range of the VCO 32 set at 100 kHz intervals. In addition to the clock frequency f _clk and the frequency division number N selected by the method described above (see FIGS. 5 to 9), a value corresponding to the DDS output coarse frequency setting value F _DATA ′ for generating the digital setting value F _DATA Is registered.

For example, when the output frequency range is 199.900 to 199.999 MHz, the minimum value f _VCO (min) = 199.900 MHz (representative frequency) of the range is divided by the frequency division number N based on the equation (7). to determine the reference frequency _{f c} by. Then the digital value _{F C} of the reference frequency _{f c,} using the digital value _{F clk} of the selected clock frequency _{f clk,} is calculated (2) DDS output coarse frequency setting value _{F DATA} 'based on formula, the Data corresponding to the value is registered in the memory 12 (described as “F _DATA (199.900)” in FIG. 15A).

In the memory 12, the clock frequency f _clk , the DDS output coarse frequency setting value F _DATA ′, and the frequency division number N are a memory address set in correspondence with a value obtained by cutting out the upper 4 digits of each output frequency range. Registered in association. That is, for the output frequency range f _VCO within the output frequency range of 199.900 to 199.999 MHz, the memory address “1989” is set based on the correspondence with the specified frequency data described later. .
As shown in FIG. 15B, various setting data actually registered in the memory 12 are set and processed according to the contents of the calculation executed by the calculation unit 13 and the DDS setting data generation unit 14. The specific data structure will be described later.

The calculation unit 13 whose configuration example is shown in FIG. 13 is based on the set value (designated frequency) of the output frequency _fVCO input to the frequency synthesizer 1a, and the memory address set for the frequency range including the output frequency. And the fractional frequency number for generating the digital set value F _DATA of DDS2 in combination with the DDS output coarse frequency set value F _DATA ′ registered in the memory 12 is calculated.

Designated frequency data (binary data) is input to the frequency synthesizer 1a. The designated frequency data is a channel number set in advance corresponding to the set value (designated frequency) of the output frequency _fVCO . For example, the output frequency range of “1.000 to 1.099 MHz” shown in FIG. 15A is associated with designated frequency data of “0 to 99” at 1 kHz intervals, and “1.100 to 1 The designated frequency data of “100 to 199” is associated with the output frequency range of “.199 MHz”. Therefore, the output frequency range of “199.900 to 199.999 MHz” is associated with the designated frequency data of “198900 to 198999”, and the output frequency range of “200.000 to 200.099 MHz” is associated with the output frequency range of “199.900 to 199.999 MHz”. Is associated with designated frequency data of “199000 to 199099”.

Designated frequency data input to the frequency synthesizer 1a is in the data "1" is added by the addition unit 131, a value corresponding to "2 ^22/100" further by multiplication section 132 "41943" is multiplied Is done. The memory address is the result of performing the operation of truncating the lower 22 bits on the data obtained in this way by the truncation operation unit 133.

The above calculation is to calculate how many times the specified frequency data is 100 (natural number). For example, when the specified frequency data is “199001 (corresponding to the specified frequency of 200.001 MHz)”, the binary data “11111000110” corresponding to the memory address “1990” is output when the above calculation is performed. On the other hand, if the same calculation is performed when the specified frequency data is “198999 (corresponding to the specified frequency of 199.999 MHz)”, binary data “11111000101” corresponding to the memory address “1989” is output. *

Further, the calculation unit 13 multiplies the output from the truncation calculation unit 133 by “100” by the multiplication unit 134, and further takes the difference value from the designated frequency by the addition unit 135. Then, the cutout calculation unit 136 cuts out the lower 7 bits of the difference value to obtain a fractional frequency number. *

This calculation is to take out the last two digits of the numerical value truncated by the calculation in the truncation calculation unit 133 that counts the specified frequency data at intervals corresponding to 100 kHz. For example, the data of the fractional frequency number extracted when the designated frequency data is “199001 (designated frequency 200.001 MHz)” is “0000001” corresponding to the last two digits “01” of “199001”. On the other hand, the data taken out when the designated frequency data is “198999 (designated frequency 199.999 MHz)” is “1100011” corresponding to the numerical value “99” of the last two digits of “198999”. *

As shown in FIG. 15B, the memory 12 stores “clock frequency setting data” for setting the clock frequency f _clk in association with the memory address output from the calculation unit 13, “DDS” described above. "Output coarse frequency setting data" and "frequency division number setting data" for setting the frequency division number N are registered.

The clock frequency setting data is assigned a value of “0/1” corresponding to each clock frequency f _clk 1 = 200 MHz and f _clk 2 = 240 MHz. The DDS output coarse frequency setting value F _DATA ′ is the binary data described with reference to FIG. 15A, and data of “F _DATA ′” is associated with an operation performed in the DDS setting data generation unit 14 described later. Is registered. Further, as the frequency division number setting data, a value “00/01/10/11” is assigned in correspondence with the frequency division numbers “N = 16, 20, 32, 40” that can be selected in this example. .

For example, when the specified frequency is “199.999 MHz (specified frequency data 1989999)”, the setting data associated with the memory address “1989” output from the calculation unit 13 is output as shown in FIG. This value corresponds to the frequency range “199.900 to 199.999 MHz”. That is, based on the setting data for selecting the clock frequency f _clk = 200 MHz (= f _clk 1) and the frequency division number N = 20, and the clock frequency and the frequency division number, the equations (7) and (2) are used. The DDS2 digital setting value (F _DATA (199.900)) when the representative frequency f _VCO (min) = 199.900 MHz is calculated.
When the memory address is output from the calculation unit 13 based on the designated frequency, the setting data is read out by the control unit 11.

Also, when the specified frequency is “200.001 MHz (specified frequency data 199001)”, each setting data corresponding to the output frequency range “200.000 to 200.099 MHz” registered based on the same concept is read. *

Next, an outline of the calculation performed by the DDS setting data generation unit 14 whose configuration example is shown in FIG. 14 will be described. When the designated frequency data (channel number associated with the output frequency f _VCO to be output from the VCO 32) is input from the outside, the digital set value F _DATA to be set for the DDS2 stores the designated frequency in the memory is a value obtained by dividing the division number N corresponding to the frequency division number setting data read out from the 12, is calculated on the basis of the reference frequency f _c ((2) type).

In calculating the digital set value F _DATA , data corresponding to the DDS output coarse frequency set value F _DATA ′ in increments of 100 kHz is registered in the memory 12 in association with the output frequency range. Then, the DDS setting data generation unit 14 may calculate a digital setting value corresponding to the last two digits of the specified frequency that is rounded down at the DDS output coarse frequency.

According to FIG. 15A, for example, when the designated frequency is “199.999 MHz (199999 kHz)”, since the frequency division number is N = 20, the reference frequency is f _c = 199999/20 (= (19900 + 99) / 20) [ kHz]. On the other hand, since the DDS output coarse frequency setting value F _DATA ′ corresponding to “199900/20 kHz” is obtained from the data registered in the memory 12, if setting data corresponding to the remaining “99/20 kHz” is generated. Good.

When the specified frequency is “199999 kHz”, the above-described expression (2) can be rewritten as the following expression (2) ′.
F _DATA (199999) = F _c (199999) / (F _clk / (2 ²⁰ ))
= {F _c (199900) + F _c (99)} / (F _clk / (2 ²⁰ ))
= F _DATA '+ F _c (99) / (F _clk / (2 ²⁰ )) (2) ′
Then, the setting data corresponding to the “99/20 kHz” can be calculated from the second term “F _c (99) / (F _clk / (2 ²⁰ ))” on the right side of (2) ′.

Here, as defined in the description of the expression (2), F _c is a digital value of the reference frequency. Accordingly, the digital value F _c (99) corresponding to the designated frequency 99 kHz is 99 times the digital value F _c (1) corresponding to the designated frequency 1 kHz. Therefore, the second term on the right side of (2) ′ can be rewritten as “99 · F _c (1) / (F _clk / (2 ²⁰ ))”, and “F _c (1) / (F _clk / When (2 ²⁰ )) ”is regarded as a coefficient, the value of“ 99 ”multiplied by the coefficient is nothing but the fractional frequency number output from the calculation unit 13.

Therefore, when the frequency division number N = 20 is selected, a coefficient corresponding to “F _c (1) / (F _clk / (2 ²⁰ ))” is registered in advance and output from the calculation unit 13. By multiplying the fractional frequency number by the coefficient, setting data corresponding to “99/20 kHz” can be calculated. Then, a calculation result, by adding the DDS output coarse frequency set value F _{DATA 'obtained} from the memory 12 can generate a digital setpoint F _DATA corresponding to the reference frequency f _c.
The DDS setting data generation unit 14 shown in FIG. 14 has a configuration capable of performing the above-described calculation.

Here, as described above, in the frequency synthesizer 1a of this example, four types of frequency division numbers N can be selected, and the frequency division numbers N to be selected depend on the selection of the clock frequencies f _clk 1 and f _clk 2. Change. Accordingly, eight types of coefficients (F _c (1) / (F _clk / (2 ²⁰ ))) determined in accordance with the combination of the frequency division number N and the clock frequencies f _clk 1 and f _clk 2 are registered in advance. if it is possible to generate a reference frequency f _c corresponding to all cases.

Therefore, when the clock frequency f _clk 1 is selected, the DDS setting data generation unit 14 is registered with four types of coefficients selected according to each frequency division number N (= 16, 20, 32, 40). Registers 141a to 141d and registers 142a to 142d in which four types of coefficients selected according to the frequency division number N when the clock frequency f _clk 2 is selected are provided. In order to reduce the influence of the quantization error associated with the setting of the coefficient “F _c (1) / (F _clk / (2 ²⁰ ))” corresponding to the designated frequency in 1 kHz increments, each of the registers 142 a to 142 d includes It is registered a value increasing the number of significant digits is multiplied by 2 ⁴ to the coefficient. Further, this digit number adjustment may be omitted as appropriate according to the accuracy required for the frequency synthesizer 1a (in this case, operations in

multipliers

147 and 148 described later are also omitted).
Based on the frequency division number setting data read from the memory 12, the preceding

stage selectors

143 a and 143 b read the corresponding coefficients of the frequency division number N, and output these coefficients to the subsequent stage selector 144.

In the subsequent selector 144, based on the clock frequency setting data read from the memory 12, the clock frequency f _clk 1 / f _clk suitable for the output of the designated frequency among the coefficients selected by the two

previous selectors

143a and 143b. Select the two-sided coefficient. When this coefficient is multiplied by the fractional frequency number output from the calculation unit 13 by the multiplication unit 145, setting data corresponding to the second term on the right side of the above-described equation (2) ′ is calculated.

On the other hand, the value corresponding to the DDS output coarse frequency setting data read from the memory 12 is multiplied by “2 ⁴ ” in the multiplication unit 147 in accordance with the coefficients registered in the registers 142a to 142d. after at adding unit 146, is added to the fraction side of the setting data, the digit number adjustment performs processing further multiplying 2 ^-4 at multiplying unit 148, a digital set value corresponding to the reference frequency f _c F _dATA Is generated. The digital setting value F _DATA is output from the DDS setting data generation unit 14.

As described above, the description of the frequency synthesizer 1a according to the second embodiment described with reference to FIGS. 12 to 15 is summarized. The memory (storage unit) 12 includes, for example, a plurality of frequency ranges divided in units of 100 kHz. Further, reference frequency f _c corresponding to a preset representative frequency (for example, the minimum value of each frequency range) in association with f _clk determined by the method described with reference to FIGS. The DDS output coarse frequency setting value F _DATA ′ is stored. Then, the calculation unit 13 calculates a memory address to determine whether the set value (designated frequency) of the output frequency of the VCO 32 corresponds to a value in any one of a plurality of frequency ranges. Further, the DDS setting data generation unit 14 is a value corresponding to a value obtained by dividing the difference value (fractional number) between the representative frequency within the frequency range specified by the calculation unit 13 and the specified frequency by the frequency division number N. and (setting data outputted from the multiplication unit 145), a digital setting based on the DDS output coarse frequency set value F _{dATA 'and} registered in the memory 12, corresponding to the reference frequency f _c of the designated frequency corresponding to the representative frequency Generate the value F _DATA .

Next, the operation of the frequency synthesizer 1a according to the second embodiment will be described. When the set value (designated frequency data) of the output frequency f _VCO of the _VCO 32 is input from the outside, the calculation unit 13 calculates the memory address and the fractional frequency number.

Based on the calculated memory address, the control unit 11 reads clock frequency setting data, DDS output coarse frequency setting data, and frequency division number setting data from the memory 12 and inputs them to the DDS setting data generation unit 14. Further, the input fraction frequency number output from the calculator 13 to the DDS setting data generation unit 14, a digital set value F of the preferred reference frequency f _c to output designated frequency from VCO32 Based on these data _DATA is generated.

Further, the control unit 11 inputs the clock frequency setting data read from the memory and the digital setting value F _DATA acquired from the DDS setting data generation unit 14 to the DDS control unit 24 of the DDS2. As a result, switching of the first changeover switch 25 and the second changeover switch 26, setting of the phase accumulator 211 of the DDS signal processing unit 21 corresponding to the digital setting value _FDATA, and the like are performed.
Further, the control unit 11 outputs the frequency division number setting data read from the memory 12 to the PLL-IC 30 and sets the frequency division number of the variable frequency divider 302.

With these settings, while changing the output frequency fVCO of the VCO 32 in units of 1 kHz, unnecessary frequency components in the frequency signal are comprehensively reduced as in the frequency synthesizer 1 according to the first embodiment, and It is possible to output a frequency signal that is optimized so as to minimize phase noise.

Here, in the frequency synthesizer 1a according to the second embodiment shown in FIGS. 12 to 15, data corresponding to the coarse frequency set value F _DATA ′ obtained from the reference frequency fc is registered in the memory 12, been described for generating a digital setting value F _dATA of the reference frequency f _c at DDS setting data generation unit 14 reads out the data.
On the other hand, similarly to the frequency synthesizer 1 according to the first embodiment, the digital setting value F _DATA may be calculated by the DDS control unit 24.

In this case, the memory 12 stores a value corresponding to the reference frequency fc corresponding to the minimum value of the output frequency range (for example, when the minimum value f _VCO (min) = 199.900 MHz and the frequency division number N = 20, 199900 kHz / Value corresponding to / 20) is registered. Further, since the DDS setting data generation unit 14 does not need to change the coefficient according to the selected clock frequency f _clk , only four registers 141a to 141d are provided according to the four frequency division numbers N.

In these registers 141a to 141d, coefficients (1 / frequency division number N) necessary for changing the reference frequency by 1 kHz are registered, and these coefficients are selected according to the selected frequency division number N. 143a is selected. Then, the selected coefficient is multiplied by the fraction number in the multiplication unit 145, the multiplication value and the calculated reference frequency fc (min) read from the memory 12 are added, and DDS control is performed as the reference frequency fc. Is output to the unit 24. *

In the frequency synthesizers 1 and 1a according to the first and second embodiments described above, the number of clock signals that can be switched is not limited to the two examples shown in FIGS. Three or more clock signals having different clock frequencies may be used in a switchable manner. Further, the method of preparing a plurality of clock signals having different clock frequencies is not limited to the case where the operation clock of the DDS-IC 20 such as the DDS control unit 24 illustrated in FIGS. 1 and 12 is multiplied. The high-frequency signal may be frequency-divided by frequency dividers having different frequency division numbers, or the frequency multiplier frequency or the frequency divider frequency may be variable. Further, clock signals having different clock frequencies may be supplied from oscillators having different oscillation frequencies.

The frequency synthesizers 1 and 1a may divide the frequency signal supplied from the DDS 2 and use the divided frequency signal as a reference frequency. As described in Equation (8), the frequency signal divided by the frequency divider includes phase noise, but if it is at a level that does not cause a problem as an effect on the output frequency of the VCO 32, it is divided into the output side of the DDS2. There is no denying the provision of a divider.

1, 1a Frequency synthesizer 11 Control unit 12 Memory 13 Calculation unit 14 DDS setting data generation unit 2 DDS
21 DDS signal processor 22 DAC
25 First changeover switch 26 Second changeover switch 3 PLL circuit 30 PLL-IC

Claims

The frequency signal output from the voltage controlled oscillator is frequency-divided by the variable frequency divider, and the phase difference between the phase of the frequency signal thus frequency-divided and the phase of the reference frequency signal is taken out by the phase comparator, and the phase difference In a frequency synthesizer including a PLL circuit that supplies a control voltage corresponding to the above to the voltage controlled oscillator from a loop filter,
A reference frequency that operates based on a clock signal and has a reference frequency corresponding to a value obtained by dividing the set value of the output frequency of the frequency signal output from the voltage controlled oscillator by the frequency division number set in the variable frequency divider A DDS for generating a signal;
A clock signal supply unit for supplying a clock signal according to a clock frequency selected from a plurality of clock frequencies prepared in advance to the DDS;
When the DDS is operated by a clock signal having a clock frequency selected from the plurality of clock frequencies and a reference frequency signal having the reference frequency is generated from the DDS, a spurious component included in a use frequency band of the DDS The reference frequency at which the frequency of the variable frequency divider does not exist within a preset frequency range and the frequency division number of the variable frequency divider is minimum is obtained in advance, and the clock frequency, the reference frequency, and the minimum frequency division number are obtained. And a storage unit for storing
A setting unit that selects a combination of a clock frequency, a reference frequency, and a minimum frequency dividing number corresponding to the set value of the output frequency and sets the clock signal supply unit, the DDS, and the variable frequency divider. This is a frequency synthesizer.
When the DDS generates a frequency signal having a reference frequency associated with the minimum frequency division number, the clock signal supply unit does not have a spurious component frequency within a preset frequency range. When a clock signal having a different clock frequency can be supplied, the storage unit has a frequency of a spurious component generated due to the different clock frequencies in the vicinity of the spurious component closest to the frequency range. A clock signal having a clock frequency that maximizes the absolute value of the difference between the upper and lower limit values and the frequency of the neighboring spurious component, and the reference frequency and the minimum frequency division number are stored in association with each other. The frequency synthesizer according to claim 1.
The DDS includes a DDS setting unit that sets a digital setting value corresponding to a reference frequency acquired from the setting unit and operates based on an operation clock supplied from the outside.
The said clock signal supply part was equipped with the multiplier for multiplying the said operation clock by a mutually different multiplication number, and preparing the clock signal of these several clock frequency, The Claim 1 or 2 characterized by the above-mentioned. Frequency synthesizer.
In the storage unit, for each of a plurality of pre-divided frequency ranges, a reference frequency corresponding to a preset representative frequency included in each frequency range is associated with the clock frequency and the minimum frequency division number. A calculation unit that is stored and calculates whether a set value of the frequency corresponds to a value in any one of the plurality of frequency ranges; a representative frequency in the frequency range specified by the calculation unit; Based on the value obtained by dividing the difference value from the frequency setting value by the frequency division number set in the variable frequency divider and the reference frequency stored corresponding to the representative frequency, the reference of the frequency setting value The frequency synthesizer according to claim 1, further comprising: a generation unit that generates a frequency.
A digital / analog converter that converts the frequency signal output from the DDS into an analog signal and outputs the analog signal;
5. The frequency synthesizer according to claim 1, wherein the digital / analog conversion unit operates based on a clock signal supplied from the clock signal supply unit. 6.