JP2018007097A - Synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a configuration of a synthesizer circuit capable of suppressing phase noise compatibly with improvement of a frequency resolution.SOLUTION: A lock state in which a difference between an output signal frequency fo and a mixer input frequency becomes equal to a reference frequency fr is formed by a phase locked loop including a phase comparator 60, a voltage controlled oscillator 90 and a mixer 50. The mixer frequency includes a frequency (n fdds) that is an integer multiple of an output frequency fdds of a DDS 20 and of which the difference from a command frequency fo* is equal to the reference frequency fr. In accordance with the command frequency fo*, a controller 100 sets frequency setting parameters α and β for adjusting the output frequency of the DDS 20 and an integer (n) in such a manner that it becomes fdds=(fo*+fr)/n or fdds=(fo*-fr)/n.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a synthesizer circuit, and more particularly to a PLL (Phase Locked Loop) synthesizer circuit.

  A wireless device used for a radar device, a communication device, or the like is required to sequentially output a plurality of frequencies. Japanese Patent Application Laid-Open No. 11-112341 (Patent Document 1) describes a configuration of an injection-locked oscillator applicable to such a wireless device.

  Patent Document 1 discloses a configuration in which an injection signal obtained by multiplying a reference signal output from a reference signal generator by m (m: integer) and a free oscillation frequency of an output signal from an oscillation circuit are phase-synchronized by a frequency negative feedback loop. Is described. Thereby, it becomes possible to output a plurality of frequencies by causing the frequency of the output signal to follow the frequency change of the injection signal.

  Japanese Patent Laying-Open No. 2010-233078 (Patent Document 2) describes the configuration of a PLL circuit used for the above-described applications. In Patent Document 2, a signal obtained by dividing an output signal from a voltage controlled oscillator by a frequency division number M (M: integer) and a signal obtained by multiplying a reference signal by a multiplication number L (L: integer) are mixed by a mixer. In addition, a configuration is described in which a PLL is formed in which an output signal of the mixer and a signal obtained by dividing the reference signal to a predetermined phase comparison frequency are input to a phase comparator. The configuration of Patent Document 2 describes that deterioration of phase noise is suppressed by variably adjusting the multiplication number L and the frequency division number M from the frequency of the reference signal and the oscillation frequency of the output signal.

JP-A-11-112341 JP 2010-233078 A

  In the configuration of Patent Document 1, in the frequency negative feedback loop, a signal having a frequency (1 / n) times (n: integer) times the output frequency and a signal obtained by multiplying the reference signal by m are input to the mixer. Further, the output signal is output by taking out the nth harmonic of the frequency of the oscillation signal. Therefore, the output signal frequency fout is fout = f × m × n with respect to the frequency f of the reference signal. For this reason, in an application in which a plurality of frequencies are sequentially output, it is difficult to ensure frequency resolution because the settable output frequency width is increased.

  In the configuration of Patent Document 2, while the phase noise can be reduced by reducing the frequency division number M, it is necessary to increase the multiplication number L in order to maintain the same (L × M). Therefore, it is understood that phase noise and frequency resolution are in a trade-off relationship to obtain an output signal having a specific frequency under a common reference signal frequency.

  Thus, in the configurations of Patent Documents 1 and 2, it is difficult to achieve both suppression of phase noise and improvement of frequency resolution.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a configuration of a synthesizer circuit capable of achieving both suppression of phase noise and improvement of frequency resolution.

  The synthesizer circuit according to the present invention generates an output signal (So) according to a command frequency (fo *). The synthesizer circuit includes a voltage controlled oscillator, a reference signal generator, a direct digital synthesizer, a control unit, a multiplied signal generation unit, a frequency mixer, a phase comparison unit, and an oscillation frequency selection unit. The voltage controlled oscillator outputs a signal having an oscillation frequency corresponding to the control voltage (Vco) as an output signal. The reference signal generator generates a reference signal having a determined reference frequency (fr). The direct digital synthesizer outputs a first signal having a variable frequency based on a reference signal. The control unit includes a first frequency (fdds) that is the frequency of the first signal and the first signal so that a frequency difference between the frequency obtained by multiplying the frequency of the first signal and the command frequency is equal to the reference frequency. The direct digital synthesizer is controlled so as to obtain a multiplication number (n) for multiplying the frequency and output a first signal having the first frequency. The multiplication signal generating means outputs a multiplication signal on which a plurality of signals obtained by multiplying the first signal are superimposed, including a second signal obtained by multiplying the first signal by the multiplication number (n). The frequency mixer outputs a mixer signal (Smx) having a frequency corresponding to the frequency difference between the output signal and the multiplied signal. The phase comparison unit outputs a voltage signal corresponding to the phase difference between the reference signal and the mixer signal to the control voltage of the voltage controlled oscillator. The oscillation frequency selection means is controlled by the control unit so that the frequency difference between the oscillation frequency of the voltage controlled oscillator and the second frequency (n · fdds) which is the frequency of the second signal becomes equal to the reference frequency (fr). To control.

  A synthesizer circuit according to another aspect of the present invention generates an output signal (So) according to a command frequency (fo *). The synthesizer circuit includes a voltage controlled oscillator, a reference signal generator, a direct digital synthesizer, a control unit, a variable multiplier, a frequency mixer, and a phase comparison unit. The voltage controlled oscillator outputs a signal having an oscillation frequency corresponding to the control voltage (Vco) as an output signal. The reference signal generator generates a reference signal having a determined reference frequency (fr). The direct digital synthesizer outputs a first signal having a variable frequency based on a reference signal. The control unit includes a first frequency (fdds) that is the frequency of the first signal and the first signal so that a frequency difference between the frequency obtained by multiplying the frequency of the first signal and the command frequency is equal to the reference frequency. The direct digital synthesizer is controlled so as to obtain a multiplication number (n) that multiplies and outputs a first signal having the first frequency. The variable multiplier outputs a second signal obtained by multiplying the first signal by the multiplication number. The frequency mixer receives the output signal and the second signal, and outputs a mixer signal having a frequency corresponding to the frequency difference between the output signal and the second signal. The phase comparison unit outputs a voltage signal corresponding to the phase difference between the reference signal and the mixer signal to the control voltage of the voltage controlled oscillator.

  According to the present invention, it is possible to provide a configuration of a synthesizer circuit that can simultaneously suppress phase noise and improve frequency resolution.

1 is a block diagram illustrating an overall configuration of a synthesizer circuit according to a first embodiment. It is a conceptual diagram which shows the frequency spectrum of the output signal of the comb generator in FIG. It is a conceptual diagram explaining the input / output frequency of the mixer in the locked state in the PLL in FIG. It is a conceptual graph for demonstrating the phase noise of a digital synthesizer circuit. 6 is a block diagram illustrating an overall configuration of a synthesizer circuit according to a first modification of the first embodiment. FIG. FIG. 10 is a block diagram illustrating an overall configuration of a synthesizer circuit according to a second modification of the first embodiment. FIG. 10 is a block diagram illustrating an overall configuration of a synthesizer circuit according to a second embodiment. It is a block diagram explaining the structural example of the variable multiplier circuit shown by FIG.

  Embodiments of the present invention will be described below in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

[Embodiment 1]
Referring to FIG. 1, synthesizer circuit 5a according to the first embodiment includes reference signal oscillator 10, direct digital synthesizer 20 (hereinafter also simply referred to as “DDS 20”), comb generator 30, mixer 50, and phase comparison. Unit 60, frequency setting auxiliary unit 70, changeover switch 80, voltage-controlled oscillator 90, and controller 100.

  The synthesizer circuit 5a outputs an output signal So according to the given command frequency fo *. By sequentially changing the command frequency fo *, the synthesizer circuit 5a can sequentially output a plurality of frequencies. Hereinafter, the actual frequency of the output signal So is also referred to as “output frequency fo”. First, each component of the synthesizer circuit 5a will be described.

  The reference signal oscillator 10 generates a reference signal Sr having a predetermined reference frequency fr. The reference signal oscillator 10 can be configured by an oscillator having a fixed oscillation frequency such as a crystal oscillator, or a combination of such an oscillator and a frequency divider having a fixed frequency division ratio.

  The DDS 20 generates a DDS signal Sdds having a frequency fdds according to a setting parameter β of k bits (k: a natural number of 2 or more) from the controller 100. Hereinafter, the frequency fdds is also referred to as a DDS frequency fdds. The DDS frequency (fdds) is expressed by the following equation (1).

fdds = fr × α × (β * / 2 ^k ) (1)
In the formula (1), α is a multiplication number by a variable multiplier (not shown) built in the DDS 20, and β * is 2 ⁰ to 2 ^k indicated by a decimal notation of the k-bit parameter β. Is a natural number. That is, it is understood that fdds follows the product of the coefficient α × (β * / 2 ^k ) that is variable by the parameters α and β and the reference frequency fr. Thus, the DDS frequency is changed by changing the parameters α and β input from the controller 100. In particular, fdds can be finely changed in 2 ^k steps by a k-bit parameter β. Thus, the DDS frequency (fdds) corresponds to the “first frequency”, and the DDS signal Sdds corresponds to the “first signal”.

  The comb generator 30 outputs a multiplied signal in which signals of a plurality of frequencies obtained by multiplying the DDS frequency fdds are superimposed as a mixer input signal Smxi.

  FIG. 2 is a conceptual diagram showing the frequency spectrum of the output signal of the comb generator 30.

  Referring to FIG. 2, comb generator 30 generates a plurality of harmonic signals from DDS frequency fdds serving as a fundamental wave signal, and multiplies the fundamental wave signal and the harmonic signal, that is, DDS frequency fdds. The multiplied signal with the superimposed signal is output. Therefore, the frequency spectrum of the multiplied signal from the comb generator 30 shows a mode in which frequency components of integer multiples (× 1, × 2,..., × n,...) Of the DDS frequency fdds are arranged in a comb-like shape over a wide band. . The comb generator 30 corresponds to an example of “multiplication signal generation means”.

  Referring to FIG. 1 again, the voltage controlled oscillator 90 outputs an output signal So having an oscillation frequency according to the input control voltage Vco. Since the oscillation frequency corresponds to the output frequency fo, the output frequency fo is determined by the control voltage Vco.

  The mixer 50 receives the mixer input signal Smxi and the output signal So as input signals, multiplies the two input signals, and outputs a mixer signal Smx. As a result, the frequency fmx of the mixer signal Smx corresponds to the frequency difference between the two input signals.

  In the synthesizer circuit 5a, the output signal So is input to the mixer 50 through a signal transmission path 51 that does not pass through a frequency divider. The output signal of the comb generator 30 is the mixer input signal Smxi.

  The phase comparison unit 60 includes a phase comparator 62 and a loop filter 65. The phase comparator 62 outputs a voltage pulse corresponding to the phase difference between the reference signal Sr and the mixer signal Smx. The loop filter 65 is composed of a low-pass filter, and smoothes the voltage pulse output from the phase comparator 62. Thereby, the output voltage V1 (DC voltage) of the phase comparison unit 60 is obtained.

  The frequency setting auxiliary unit 70 and the changeover switch 80 include a signal having a specific frequency (n · fdds described later) among a plurality of signals obtained by multiplying the DDS frequency fdds included in the multiplied signal generated by the comb generator 30. Arranged to temporarily set the oscillation frequency (control voltage Vco) of the voltage controlled oscillator 90 so that the output frequency fo can be locked in accordance with the command frequency fo *. That is, in the configuration example of FIG. 1, the function of “oscillation frequency selection means” is realized by the frequency setting auxiliary unit 70 and the changeover switch 80.

  The frequency setting auxiliary unit 70 includes a variable frequency divider 71, a phase comparator 72, and a loop filter 75. The variable frequency divider 71 divides the output signal So by the frequency division number M (M: integer) variably controlled by the controller 100. Therefore, the frequency of the output signal of the variable frequency divider 71 is indicated by fo / M using the output frequency fo.

  The phase comparator 72 outputs a voltage pulse corresponding to the phase difference between the output signal of the variable frequency divider 71 and the reference signal Sr. The loop filter 75 is composed of a low-pass filter, and smoothes the voltage pulse output from the phase comparator 72. As a result, the output voltage V2 (DC voltage) of the frequency setting auxiliary unit 70 is obtained. That is, in the configuration example of FIG. 1, the frequency setting auxiliary unit 70 corresponds to an “auxiliary phase comparison unit”.

  The changeover switch 80 is disposed between the phase comparison unit 60 and the frequency setting auxiliary unit 70 and the voltage controlled oscillator 90. The changeover switch 80 includes a first path for inputting the output voltage V1 of the phase comparison unit 60 to the voltage controlled oscillator 90 as the control voltage Vco according to the PLL switching signal Sch from the controller 100, and an output voltage of the frequency setting auxiliary unit 70. The second path for inputting V2 to the voltage controlled oscillator 90 as the control voltage Vco is switched.

  Therefore, when the changeover switch 80 selects the first path, a PLL is formed by the mixer 50, the phase comparison unit 60, and the voltage controlled oscillator 90. On the other hand, when the changeover switch 80 selects the second path, a PLL is formed by the mixer 50, the frequency setting auxiliary unit 70, and the voltage controlled oscillator 90.

  In the PLL using the phase comparison unit 60, the output frequency fo is locked so that the state where the frequency fmx of the mixer signal Smx is equal to the reference frequency fr (fmx = fr) is maintained.

  On the other hand, in the PLL using the frequency setting auxiliary unit 70 (hereinafter referred to as pre-PLL), the output frequency fo is locked so that the divided fo / M is equal to the reference frequency fr. The That is, the pre-PLL is locked with fo = fr · M.

  The controller 100 adjusts the parameters α and β (DDS20) for adjusting the DDS frequency fdds according to the given command frequency fo *, the frequency dividing number M (variable frequency divider 71), and the PLL switching signal Sch ( Changeover switch 80). The controller 100 variably sets the parameters α and β and the frequency division number M according to the given command frequency fo * so that the output frequency fo according to the command frequency fo * is obtained.

  Next, the operation of the synthesizer circuit 5a will be described in detail.

  When the command frequency fo * is given, the controller 100 generates the PLL switching signal Sch so as to form a pre-PLL using the frequency setting auxiliary unit 70, and also changes the frequency division number M of the variable frequency divider 71. Of the number of divisions (integer) that can be set by the frequency divider 71, an integer value closest to (fo * / fr) is set. As a result, the output frequency fo is locked to fo = M · fr by the pre-PLL, and thus becomes close to the command frequency fo *.

  After the oscillating frequency (control voltage Vco) of the voltage controlled oscillator 90 is provisionally set by the formation of the lock state by the pre-PLL, the controller 100 outputs the PLL switching signal Sch so as to form the PLL using the phase comparison unit 60. change. Thereby, when the mixer input signal Smxi corresponding to the multiplied signal from the comb generator 30 has the frequency spectrum shown in FIG. 2, the specific multiplication numbers n and fdds among a plurality of frequencies that are integer multiples of fdds are obtained. A lock state as shown in FIG. 3 is formed using n · fdds corresponding to the product. n · fdds corresponds to the “second frequency”, and among the multiplied signals from the comb generator 30, the signal of the frequency of n · fdds corresponds to the “second signal”.

  Referring to FIG. 3, in the locked state, the frequency fmx = fr of mixer signal Smx is obtained. Here, from the output frequency fo and the n · fdds, fmx is (fo−n · fdds) when fo> n · dds, while (n · fdds−fo) when fo <n · dds. It becomes. That is, the PLL is locked in the state of fr = | fo−n · fdds |. At this time, the synthesizer circuit 5a is controlled so that the frequency difference between the output frequency fo, which is the oscillation frequency of the voltage controlled oscillator 90, and n · fdds according to the multiplication number n is equal to the reference frequency fr.

  The controller 100 determines the DDS frequency fdds and the multiplication number n so that the DDS frequency fdds satisfies the following formula (2) or formula (3). The parameters α and β are set by back-calculating so that the determined DDS frequency is generated by the DDS 20. For example, the controller 100 can previously create a table or the like in which a set of fdds and n is determined in advance for each of the assumed command frequencies fo *.

fdds = (fo * + fr) / n (2)
fdds = (fo * −fr) / n (3)

  When the pre-PLL is formed by the frequency setting auxiliary unit 70 and the changeover switch 80 under the DDS frequency fdds and the multiplication number n set according to the equation (2) or (3), the control voltage Vco of the voltage controlled oscillator 90 is Temporarily set according to the output voltage V2 of the frequency setting auxiliary unit 70. At this time, by being locked near fo = fo *, the output voltage V2 has a plurality of frequencies (fdds, 2 · fdds,..., N · fdds,...) Included in the multiplied signal generated by the comb generator 30. Of these, n · fdds is set such that the frequency difference from the oscillation frequency (output frequency fo) of the voltage controlled oscillator 90 is closest to the reference frequency fr. That is, the output voltage V2 of the frequency setting auxiliary unit 70 when the pre-PLL is formed corresponds to the “setting auxiliary voltage signal”. Further, after forming the pre-PLL, by changing the path by the changeover switch 80, by forming the PLL by the phase comparison unit 60, among the multiple signals (integer multiples of fdds) included in the multiplied signal from the comb generator 30 By using a signal having a frequency of n · fdds, the locked state in the frequency relationship shown in FIG. 3 can be realized.

  At this time, it is understood that the PLL locks in a state of fo = fo * obtained by substituting the above formula (2) or (3) into fr = ± (fo−n · fdds). As a result, the output frequency fo can be controlled according to the command frequency fo *.

  Whenever the command frequency fo * changes, the controller 100 adjusts the multiplier n and the DDS frequency fdds according to the equation (2) or (3) so that fo = fo *. The frequency division number M is changed. Thereby, the synthesizer circuit 5a can sequentially output the output frequency fo according to the command frequency fo *.

  Next, phase noise of the synthesizer circuit 5a will be described with reference to FIG.

  Referring to FIG. 4, (a) shows phase noise in a comparative example in which an output signal is input to mixer 50 via a variable frequency divider as in Patent Document 2, while (b) Shows the phase noise of synthesizer circuit 5a according to the first embodiment.

  4A and 4B, the horizontal axis indicates the offset frequency, and the vertical axis indicates the phase noise level at each frequency. Furthermore, the phase noise characteristic 201 of the voltage controlled oscillator 90, the phase noise characteristic 202 of the phase comparator 62 alone, the phase noise characteristic 203 of the reference signal oscillator 10, and the total phase noise characteristic 200 in the output signal So of the synthesizer circuit 5a. It is shown.

  4A further shows a phase noise characteristic 204 in the phase comparator 62 when the output signal So is divided (frequency division number M) and input to the mixer 50. FIG. In the phase noise characteristic 204, the phase noise level is increased by 20 · log (1 / M) as compared with the phase noise characteristic 202 of the phase comparator 62 alone.

  In the PLL, the phase noise of the voltage controlled oscillator 90 is dominant in a region having a frequency higher than the cut-off frequency fc of the loop filter 65, while the phase generated by the phase comparison is in a region having a frequency lower than the cut-off frequency fc. Noise becomes dominant. Therefore, in the comparative example of FIG. 4A, the cut-off frequency fc is set to a frequency at which the phase noise of the voltage-controlled oscillator 90 is equivalent to the phase noise of the divided phase comparator. Phase noise can be suppressed.

  However, in the frequency region lower than the cutoff frequency fc, the total phase noise characteristic 200 is equivalent to the phase noise characteristic 204 after the frequency division, and is larger than the phase noise of the phase comparator 62 alone. That is, it is understood that the phase noise in the low frequency region is deteriorated by forming the PLL obtained by dividing the output signal So.

  On the other hand, in the configuration of the synthesizer circuit 5a shown in FIG. 4B, since the influence of frequency division is eliminated, the phase noise generated by the phase comparison is the phase noise characteristic of the phase comparator 62 alone. 202.

  As a result, it is possible to suppress phase noise in a lower frequency region than the cutoff frequency fc. In particular, as shown in FIG. 4B, the cut-off frequency fc of the loop filter 65 is designed so that the phase noise of the voltage controlled oscillator 90 is equivalent to the phase noise of the phase comparator 62 alone. The total phase noise characteristic 200 can be appropriately improved.

  As described above, according to the synthesizer circuit 5a according to the first embodiment, the output signal So is input to the mixer 50 without passing through the frequency divider, so that the PLL of the output signal So can be performed without going through the frequency divider. By forming, phase noise can be suppressed.

  Further, the frequency of the mixer input signal Smxi, which is the other input signal of the mixer 50, can be set finely by changing the DDS frequency fdds by the DDS 20. As a result, the frequency fmx (fmx = ± (fo−n · fdds)) of the mixer signal Smx to be compared with the reference frequency fr can be finely set according to the command frequency fo *. Therefore, it is possible to ensure the frequency resolution of the output frequency fo.

  Thus, according to the configuration of synthesizer circuit 5a according to the first embodiment, it is possible to achieve both suppression of phase noise and improvement of frequency resolution.

[Variation 1 of Embodiment 1]
FIG. 5 is a block diagram illustrating an overall configuration of synthesizer circuit 5b according to the first modification of the first embodiment.

  Referring to FIG. 5, synthesizer circuit 5b according to the first modification of the first embodiment is different from frequency synthesizer circuit 5a (FIG. 1) according to the first embodiment in place of frequency setting auxiliary unit 70. It differs in the point provided with the part 110. The frequency setting auxiliary unit 110 includes a voltage generator 112 that generates the output voltage V <b> 2 and a voltage table 114. The voltage table 114 reflects the temperature dependence of the oscillation frequency of the voltage controlled oscillator 90 acquired in advance, and controls the voltage controlled oscillator 90 to oscillate at the frequency f according to the input of the frequency f and the temperature T. A voltage value corresponding to the voltage Vco is output.

  The voltage generator 112 refers to the voltage table 114 using the command frequency fo * transmitted from the controller 100 and a temperature detection value by a temperature sensor (not shown). Thus, the voltage generator 112 generates an output voltage V2 corresponding to a preset value of the control voltage Vco for setting the oscillation frequency (output frequency fo) of the voltage controlled oscillator 90 to the command frequency fo * under the current temperature environment. Generate.

  The change-over switch 80 includes a first path for inputting the output voltage V1 of the phase comparison unit 60 to the voltage-controlled oscillator 90 as the control voltage Vco in accordance with the PLL switching signal Sch similar to FIG. The second path for inputting V2 to the voltage controlled oscillator 90 as the control voltage Vco is switched.

  Since the configuration of other parts of synthesizer circuit 5b is the same as that of synthesizer circuit 5a (FIG. 1) according to the first embodiment, detailed description will not be repeated. That is, the parameters α and β and the multiplication number n are set in the same manner as in the first embodiment, corresponding to the command frequency fo *.

  Also in synthesizer circuit 5b according to the first modification of the first embodiment, when command frequency fo * is given, controller 100 first inputs output voltage V2 from frequency setting auxiliary unit 110 to voltage controlled oscillator 90 as control voltage Vco. Thus, the changeover switch 80 is controlled. Thus, the oscillation frequency (control voltage Vco) of the voltage controlled oscillator 90 can be temporarily set so that the output frequency fo is close to the command frequency fo * without forming a pre-PLL as in the synthesizer circuit 5a. it can. That is, in the configuration example of FIG. 5, the function of “oscillation frequency selection means” is realized by the frequency setting auxiliary unit 110 and the changeover switch 80.

  By this temporary setting, as in the first embodiment, for the output voltage V2, among the multiple frequencies (fdds, 2 · fdds,..., N · fdds,...) Included in the multiplied signal generated by the comb generator 30. In n · fdds, the frequency difference with the oscillation frequency (output frequency fo) of the voltage controlled oscillator 90 can be set so as to be closest to the reference frequency fr. That is, the output voltage V2 of the frequency setting auxiliary unit 110 corresponds to the “setting auxiliary voltage signal”.

  After the oscillation frequency (control voltage Vco) of the voltage controlled oscillator 90 is temporarily set as described above, the controller 100 controls the changeover switch 80 so as to form a PLL by the phase comparison unit 60. Thereby, similarly to the first embodiment, among the plurality of signals (integer multiple of fdds) included in the multiplied signal from the comb generator 30, a signal having a frequency of n · fdds according to the multiplication number n is used. The locked state in the frequency relationship shown in FIG. 3 can be realized. As a result, when the PLL is locked in a state of fo = fo *, the output frequency fo can be controlled according to the command frequency fo *.

  Similarly to the first embodiment, the controller 100 adjusts the multiplication number n and the DDS frequency fdds according to the formula (2) or (3) so that fo = fo * every time the command frequency fo * changes. Thus, the parameterers α and β are changed. As a result, the synthesizer circuit 5b according to the first modification of the first embodiment suppresses the phase noise and ensures the frequency resolution in the same manner as the synthesizer circuit 5a, and then sequentially outputs the output frequency fo according to the command frequency fo *. Can be output. In particular, in the synthesizer circuit 5b according to the first modification of the first embodiment, the oscillation frequency (control voltage Vco) of the voltage controlled oscillator 90 can be temporarily set without forming a pre-PLL. Thus, the circuit configuration can be simplified.

[Modification 2 of Embodiment 1]
FIG. 6 is a block diagram illustrating an overall configuration of synthesizer circuit 5c according to the second modification of the first embodiment.

  Referring to FIG. 6, synthesizer circuit 5c according to the second modification of the first embodiment is replaced with frequency setting auxiliary unit 70 and changeover switch 80 as compared to synthesizer circuit 5a according to the first embodiment (FIG. 1). The difference is that a frequency selection unit 120 is provided. The frequency selection unit 120 is disposed between the comb generator 30 and the mixer 50. Further, since the changeover switch 80 is not disposed, the output voltage V1 of the phase comparison unit 60 is fixedly input to the voltage controlled oscillator 90 as the control voltage Vco.

  The frequency selection unit 120 includes switches 121 and 122 and m (m: a natural number of 2 or more) filters 125-1 to 125-m. The filters 125-1 to 125-m can be configured by band-pass filters having different frequency ranges that transmit each other. The switch 121 is connected between the comb generator 30 and the filters 125-1 to 125-m. The switch 122 is connected between the filters 125-1 to 125-m and the mixer 50.

  The switches 121 and 122 are controlled in accordance with a control signal P from the controller 100 for selecting one of the filters 125-1 to 125-m. Thereby, in the frequency selection unit 120, one filter selected by the control signal P among the filters 125-1 to 125-m is connected between the comb generator 30 and the mixer 50.

  As a result, among the plurality of frequencies (fdds, 2 · fdds,..., N · fdds,...) Included in the multiplied signal from the comb generator 30, only a signal within a frequency range that passes through the selected filter is mixed. The input signal Smxi is transmitted to the mixer 50. Since the configuration of other parts of synthesizer circuit 5c is the same as that of synthesizer circuit 5a (FIG. 1) according to the first embodiment, detailed description will not be repeated. That is, the controller 100 determines the multiplication factor n and the DDS frequency fdds according to the equation (2) or (3) and sets the parameters α and β corresponding to the command frequency fo * as in the first embodiment. To do.

  In the synthesizer circuit 5c, the controller 100 generates the control signal P so that a filter having a frequency range in which a signal having a frequency of n · fdds according to the multiplication number n can be transmitted is selected. For example, according to the respective transmission frequency ranges of the filters 125-1 to 125-m, a correspondence map between the calculated value of n · fdds and the selection of the filters 125-1 to 125-m is created in advance, whereby the command frequency fo The control signal P can be generated corresponding to *.

  As a result, in the synthesizer circuit 5c, the frequency selection unit 120 causes the frequency difference between the output signal So and the signal having a frequency of n · fdds according to the multiplication number n among the multiplied signals generated by the comb generator 30 to be the reference frequency. A state equal to fr is formed. Thus, as in the formation of the PLL by the phase comparison unit 60 in the synthesizer circuit 5a according to the first embodiment, the PLL is set in the frequency relationship shown in FIG. 3, that is, in the state of fr = | fo−n · fdds |. Lock it.

  Similarly to the first embodiment, the controller 100 calculates the multiplication number n, the DDS frequency fdds, and the parameters α and β so that fo = fo * every time the command frequency fo * changes, and fdds and The control signal P can be generated according to the multiplication number n.

  Thereby, the synthesizer circuit 5c according to the second modification of the first embodiment suppresses the phase noise and secures the frequency resolution in the same manner as the synthesizer circuit 5a, and sequentially outputs the output frequency fo according to the command frequency fo *. Can be output. In particular, in the synthesizer circuit 5c according to the second modification of the first embodiment, provisional setting of the oscillation frequency (control voltage Vco) of the voltage controlled oscillator 90 is unnecessary, and therefore, compared with the first embodiment and the first modification thereof. The circuit configuration and / or control processing can be simplified. The synthesizer circuit 5c according to the second modification of the first embodiment has a relatively narrow change range of the command frequency fo *, and the transmission frequency bandwidth of each of the filters 125-1 to 125-m is set to the DDS frequency fdds. It is possible to apply to applications that can be narrower than the lower limit.

[Embodiment 2]
FIG. 7 is a block diagram showing a configuration of synthesizer circuit 5d according to the second embodiment of the present invention.

  Referring to FIG. 7, synthesizer circuit 5d according to the second embodiment includes variable multiplier circuit 130 instead of comb generator 30 as compared to synthesizer circuit 5a shown in FIG. The difference is that the disposition of the changeover switch 80 becomes unnecessary. Since the other configuration of synthesizer circuit 5d is similar to that of synthesizer circuit 5a, detailed description will not be repeated.

  The variable multiplication circuit 130 multiplies the DDS signal Sdds from the DDS 20 according to the multiplication number command value L to generate a mixer input signal Smxi. That is, the multiplication number of the variable multiplication circuit 130 can be variably set by the multiplication number command value L from the controller 100.

  FIG. 8 is a block diagram illustrating a configuration example of the variable multiplier circuit 130 illustrated in FIG. 7.

  Referring to FIG. 8, variable multiplier circuit 130 has i (i: natural number of 2 or more) multiplication stages 131-1 to 131-i connected in series. Each of the multiplication stages 131-1 to 131-i includes a multiplier 135 and a changeover switch 136. FIG. 8 illustrates a multiplier 135-1 and a changeover switch 136-1 constituting the multiplication stage 131-1, and a multiplier 135-2 and a changeover switch 136-2 constituting the multiplication stage 131-2. .

  The multiplication number of the multiplier 135-1 is k1, and the multiplication number of the multiplier 135-2 is k2. The multiplication numbers in each of the multiplication stages 131-1 to 131-i are k1 to ki. Further, control commands S1 to Si of the changeover switch 136 are input to the multiplication stages 131-1 to 131-i, respectively.

  In each of the multiplication stages 131-1 to 131-i, the changeover switch 136 controls the control path from the controller 100 between a signal path passing through the multiplier 135 and a signal path bypassing the multiplier 135 in the multiplication stage. Control according to S1 to Si.

  Therefore, the multiplication number by the variable multiplication circuit 130 can be variably controlled by a combination of passing and detouring of the multipliers 135-1 to 135-i in the multiplication stages 131-1 to 131-i. Specifically, the multiplication number is indicated by multiplication of the multiplication number in the multiplier through which the signal has passed, which is at least a part of k1 to ki. That is, by setting the control commands S1 to Si, the multiplication number of the variable multiplication circuit 130 can be variably controlled by using an integer that can be realized by the product of at least a part of k1 to ki.

  Note that the variable multiplier circuit 130 may have a configuration different from that illustrated in FIG. For example, instead of the multiplier, it is also possible to obtain a signal multiplied by the nonlinear characteristic of the harmonic amplifier. As long as the multiplication number can be variably controlled according to the multiplication number command value L from the controller 100, the configuration of the variable multiplication circuit 130 can be arbitrary.

  Referring to FIG. 7 again, controller 100 sets multiplication factor command value L to multiplication factor n in equation (2) or (3) (L = n). Therefore, the frequency of the mixer input signal Smxi is n · fdds as in the first embodiment. Therefore, the frequency of the mixer signal Smx output from the mixer 50 is a frequency difference between the mixer input signal Smxi and the output signal So, that is, | fo−n · fdds |.

  In the synthesizer circuit 5d, the changeover switch 80 is not disposed, and the output voltage V1 of the phase comparison unit 60 is fixedly input to the voltage controlled oscillator 90 as the control voltage Vco. As a result, the PLL formed by the mixer 50, the phase comparison unit 60, and the voltage controlled oscillator 90 described in the first embodiment is fixedly formed.

  As a result, in the PLL, a locked state in which | fo−n · fdds | = fr is formed. As described above, by setting n and fdds according to the formula (2) or (3), the output frequency fo of the output signal So can be controlled to the command frequency fo * as in the first embodiment. (Fo = fo *).

  Similarly to the synthesizer circuits 5a to 5c according to the first embodiment and the modification thereof, the synthesizer circuit 5d according to the second embodiment forms a PLL of the output signal So without going through the frequency divider, and outputs the frequency fo The mixer input signal Smxi to be mixed with can be set with a fine frequency width by the DDS 20. As a result, both the suppression of phase noise and the improvement of frequency resolution can be achieved by the configuration of the synthesizer circuit 5d.

  For the synthesizer circuits 5a to 5d, by sequentially generating output signals of a plurality of frequencies in accordance with an external command frequency fo *, a mobile phone, a radar device, or The present invention can be applied to a secret communication device for defense.

  As described above, in synthesizer circuits 5a to 5d, a signal having a frequency of n · fdds according to the equation (2) or (3) is used as the mixer input signal Smxi. As a result, it is possible to form the PLL of the output signal So satisfying fr = | fo−n · fdds | without passing through the frequency divider through the synthesizer circuits 5a to 5d.

  As described above, in the first embodiment (synthesizer circuit 5a) and the modifications 1 and 2 (synthesizer circuits 5b and 5c), since the comb generator 30 can generate signals of a large number of frequencies, the command frequency fo * On the other hand, the degree of freedom of fdds and n for realizing the formula (2) or (3) is improved. As a result, a wide applicable range of the command frequency fo * can be secured. Furthermore, it is easy to ensure the frequency resolution.

  On the other hand, in the first embodiment (synthesizer circuit 5a) and its modification 1 (synthesizer circuit 5b), the mixer input signal Smxi includes a signal having a frequency different from n · dds (integer multiple of DDDS frequency). As a result of temporarily setting the oscillation frequency of the voltage-controlled oscillator 90, the circuit configuration and / or control processing becomes complicated. Further, in the second modification (synthesizer circuit 5c) of the first embodiment, the configuration and the control process for the temporary setting are not necessary, but it is difficult to widen the change range of the command frequency fo *.

  On the other hand, in the second embodiment (synthesizer circuit 5d), the frequency setting auxiliary unit 70 and the changeover switch 80 for the pre-PLL are not required, and the variable multiplier circuit 130 is disposed instead of the comb generator 30. It tends to be advantageous in terms of cost. On the other hand, in order to increase the degree of freedom of the multiplication number by the variable multiplier circuit 130, there is a concern that the variable multiplier circuit 130 is increased in size.

  As described above, each of the synthesizer circuits 5a to 5d can achieve both the suppression of the phase noise and the improvement of the frequency resolution, but each has advantages and disadvantages. For example, in applications in which signals having a plurality of frequencies are sequentially output, the configurations of the synthesizer circuits 5a to 5d can be properly used according to the required range of the command frequency fo *.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  5a to 5d synthesizer circuit, 10 reference signal oscillator, 20 direct digital synthesizer (DDS), 30 comb generator, 50 mixer, 51 signal transmission path, 60 phase comparison unit, 62, 72 phase comparator, 65, 75 loop filter, 70 110 frequency setting auxiliary unit, 71 variable frequency divider, 80 selector switch, 90 voltage controlled oscillator, 100 controller, 112 voltage generator, 114 voltage table, 120 frequency selection unit, 121, 122 switch, 125-1 to m filter , 130 variable multiplier circuit, 131-1 to 131, 131-i multiplier stage (variable multiplier circuit), 135-1, multiplier (variable multiplier circuit), 136-1, 2 selector switch (variable multiplier circuit), 200 Total phase noise characteristics, 201-204 phase noise characteristics (each element , L multiplication command value (variable multiplication circuit), M division number (variable frequency divider), n multiplication number, S1 to Si control command (variable multiplication circuit), Sch switching signal (switch), Sdds DDS signal, Smx mixer signal, Smxi mixer input signal, So output signal, Sr reference signal, V1, V2 output voltage, Vco control voltage (voltage controlled oscillator), fdds DDS frequency, fmx frequency (mixer signal), fc cutoff frequency (loop filter) ), Fo output frequency, fo * command frequency, fr reference frequency (reference signal oscillator).

Claims (6)

A synthesizer circuit that generates an output signal according to a command frequency,
A voltage controlled oscillator that outputs a signal having an oscillation frequency corresponding to the control voltage as the output signal;
A reference signal generator for generating a reference signal having a determined reference frequency;
A direct digital synthesizer that outputs a first signal having a variable frequency based on the reference signal;
The first frequency, which is the frequency of the first signal, is multiplied by the first signal so that the frequency difference between the frequency obtained by multiplying the frequency of the first signal and the command frequency is equal to the reference frequency. A control unit for controlling the direct digital synthesizer so as to output a first signal having the first frequency;
A multiplied signal generating means for outputting a multiplied signal in which a plurality of signals obtained by multiplying the first signal are superimposed, including a second signal obtained by multiplying the first signal by the multiplication number;
A frequency mixer that outputs a mixer signal having a frequency corresponding to a frequency difference between the output signal and the multiplied signal;
A phase comparator that outputs a voltage signal corresponding to a phase difference between the reference signal and the mixer signal to the control voltage of the voltage controlled oscillator;
Oscillation frequency selection means controlled by the control unit to control the frequency difference between the oscillation frequency of the voltage controlled oscillator and the second frequency that is the frequency of the second signal to be equal to the reference frequency. A synthesizer circuit. The oscillation frequency selection means includes
The difference between the oscillation frequency of the corresponding voltage-controlled oscillator and the frequency of each of the plurality of signals constituting the multiplied signal corresponds to the control voltage that is closest to the reference frequency in the second signal. A frequency setting auxiliary unit that generates a setting auxiliary voltage signal in response to control from the control unit;
The voltage signal from the phase comparator is input as the control voltage of the voltage controlled oscillator between the phase comparator and the frequency setting auxiliary unit and the voltage controlled oscillator according to the control from the controller. And a selector switch configured to selectively form a first path for inputting and a second path for inputting the setting auxiliary voltage signal from the frequency setting auxiliary unit as the control voltage of the voltage controlled oscillator; With
The synthesizer circuit according to claim 1, wherein the control unit controls the changeover switch so that the first path is selected after controlling the changeover switch so that the second path is selected. . The frequency setting auxiliary unit is
A variable frequency divider configured to output a frequency-divided output signal obtained by dividing the output signal by a frequency division number determined based on a value obtained by dividing the command frequency by the reference frequency, which is set in the control unit;
The synthesizer circuit according to claim 2, further comprising: an auxiliary phase comparison unit that outputs a voltage signal corresponding to a phase difference between the reference signal and the divided output signal as the setting auxiliary voltage signal.   The oscillating frequency selecting means is between the multiplied signal generating means and the frequency mixer, and is controlled by the control unit so that the first of the multiplied signals input from the multiplied signal generating means. The synthesizer circuit according to claim 1, wherein the synthesizer circuit is a frequency selection unit that selectively transmits two signals. A synthesizer circuit that generates an output signal according to a command frequency,
A voltage controlled oscillator that outputs a signal having an oscillation frequency corresponding to the control voltage as the output signal;
A reference signal generator for generating a reference signal having a determined reference frequency;
A direct digital synthesizer that outputs a first signal having a variable frequency based on the reference signal;
The first frequency, which is the frequency of the first signal, is multiplied by the first signal so that the frequency difference between the frequency obtained by multiplying the frequency of the first signal and the command frequency is equal to the reference frequency. A control unit for controlling the direct digital synthesizer so as to output a first signal having the first frequency;
A variable multiplier that outputs a second signal obtained by multiplying the first signal by the multiplication number;
A frequency mixer that receives the output signal and the second signal and outputs a mixer signal having a frequency corresponding to a frequency difference between the output signal and the second signal;
A synthesizer circuit comprising: a phase comparator that outputs a voltage signal corresponding to a phase difference between the reference signal and the mixer signal to the control voltage of the voltage controlled oscillator. The phase comparison unit includes:
A phase comparator that outputs a voltage pulse corresponding to a phase difference between the reference signal and the mixer signal;
A loop filter that smoothes the voltage pulse and generates the control voltage,
The cut-off frequency of the loop filter is designed to cut off a frequency region in which the phase noise of the voltage controlled oscillator is higher than the phase noise of the phase comparator. Synthesizer circuit.

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