JP4348225B2 - PLL frequency synthesizer - Google Patents

Description

  The present invention relates to a PLL frequency synthesizer, and more particularly to a PLL frequency synthesizer suitable for use in a wireless communication apparatus.

  As a conventional PLL frequency synthesizer capable of changing the frequency in a wide band, one described in Patent Document 1 is known. The PLL frequency synthesizer shown in FIG. 23 includes a reference oscillator 11 in addition to a first oscillation means having a PLL circuit including a reference frequency divider 13, a phase comparator 14, a comparison frequency divider 15, a loop filter 16, and a VCO 17. A second oscillating means comprising a variable frequency divider 19 and a mixing means comprising a multiplier 18 are provided. The first oscillation means generates an arbitrary first oscillation frequency f4 within a predetermined bandwidth, and the second oscillation means generates a plurality of second oscillation frequencies f5 having a predetermined frequency interval. The first oscillation frequency and the second oscillation frequency, which are selectively generated and generated by the first and second oscillation means, are mixed with each other by the mixing means to generate a local oscillation signal. Is. According to this configuration, the output frequency f6 can be expressed by the following equation.

f6 = f4 × 3 + f5
= F4 x 3 + f1 / M

  The conventional PLL frequency synthesizer adds a frequency of f5 obtained by switching the frequency division ratio M of the variable frequency divider 19 to the variable width of the oscillation frequency f4 of the VCO 17, thereby widening the variable range of the local oscillation signal. Can be

For example, when a local oscillation signal having a frequency range of 4800 to 5200 MHz is obtained, the multiplier 18 is multiplied by 5, the oscillation frequency f1 of the reference oscillator 11 is 300 MHz, and the oscillation frequency f4 of the VCO 17 is 940 to 980 MHz (frequency variable width). 40 MHz). That is, when M = 3,
f6 = f4 × 5 + f1 / M
= (940-980 MHz) x 5 + 300 MHz / 3
= 4700-4900MHz + 100MHz
= 4800-5000MHz
It becomes. When M = 1
f6 = f4 × 5 + f1 / M
= (940-980 MHz) × 5 + 300 MHz / 1
= 4700-4900MHz + 300MHz
= 5000-5200MHz
It becomes. Therefore, a variable width of 400 MHz from 4800 MHz to 5200 MHz can be realized.

  However, in the conventional apparatus, in the triple multiplier 18, the first oscillation signal obtained by multiplying f4 by 3 and the second oscillation signal obtained by dividing f5 by M are mixed. As means for realizing the frequency mixing, there is generally a method of performing frequency mixing using a multiplier. In this case, a component of the image frequency (f4 × 3-f5) is generated in addition to the frequency of f6. A means for removing the frequency is required.

  Further, when obtaining a local oscillation signal having a frequency range of 4800 to 5200 MHz, the reference oscillation frequency f1 needs to be as high as 300 MHz, so that the C / N characteristics are deteriorated. Since the C / N characteristic of the first oscillation frequency f4 having the PLL circuit is affected by the C / N characteristic of the reference oscillation frequency f1, the C / N characteristic of f4 is also deteriorated. That is, the C / N characteristic of the local oscillation signal f6 is deteriorated.

Therefore, it is possible to obtain a local oscillation signal having a frequency range of 4800 to 5200 MHz by reducing the frequency of the reference oscillation frequency f1 and increasing the variable frequency width of the oscillation frequency f4 of the VCO 17, but in this case, the voltage of the VCO 17 Since the sensitivity is increased, the Q value of the oscillator is decreased and the C / N characteristic of f4 is deteriorated, so that the C / N characteristic of f6 is deteriorated.
JP-A-5-291977

  As described above, the conventional apparatus has a problem that it is difficult to generate a signal having a wide frequency variable and good C / N characteristics.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a PLL frequency synthesizer capable of wideband frequency variation and good C / N characteristics.

The PLL frequency synthesizer of the present invention includes a first oscillating unit that outputs a first signal having a variable first frequency , a second oscillating unit that outputs a second signal having a second frequency that interpolates a frequency variable range, Multiplying the first signal and the second signal, the signal of the first frequency, the signal of the frequency obtained by adding the first frequency and the second frequency, and subtracting the second frequency from the first frequency And an output selection means for selectively outputting any one of the frequency signals.

In the PLL frequency synthesizer of the present invention, the output selection unit passes a signal having a frequency obtained by adding the first frequency and the second frequency, and a multiplication unit that multiplies the first signal and the second signal. Any one of a first filter, a second filter that passes a signal having a frequency obtained by subtracting the second frequency from the first frequency, a signal output from the first filter, and a signal output from the second filter A first switch that selects the first switch; and a second switch that selects either the signal output from the first switch or the first signal.

  According to these configurations, a first signal having a variable frequency is oscillated, a signal having a second frequency that complements the variable range of the signal is oscillated, and the first signal and the second signal are mixed. By filtering and outputting a desired frequency from the received signal, it is possible to generate a signal variably at a wide frequency with good C / N characteristics.

  In the PLL frequency synthesizer according to the present invention, the output selection means multiplies the first switch that outputs or does not output the second signal, and the output of the first switch and the first signal. Means, a first filter for passing a signal having a frequency obtained by adding the output of the first switch and the first signal, and a first filter for passing a signal having a frequency obtained by subtracting the output of the first switch from the first frequency. The configuration includes two filters, a signal output from the first filter, a signal output from the second filter, and a second switch that selects one of the first signals.

  According to this configuration, by controlling the power supply voltage of the PLL that does not use the oscillated signal and stopping the operation, the PLL power frequency synthesizer with a wide bandwidth can be varied and the C / N characteristic is good. Can be made.

In the PLL frequency synthesizer according to the present invention, the output selection unit includes a multiplying unit that multiplies the first signal and the second signal, and the first frequency and the second frequency based on a signal after multiplication in the multiplying unit. A variable filter that passes a signal having a frequency obtained by adding or a frequency obtained by subtracting the second frequency from the first frequency, and a signal output from the variable filter or the first signal is selected. And a switch that performs the above-described operation.

  In the PLL frequency synthesizer of the present invention, the output selection means includes a switch that performs either the output or non-output of the second signal, a multiplication means that multiplies the output of the switch and the first signal, A signal of any one of the first frequency, the frequency obtained by adding the first frequency and the second frequency, or the frequency obtained by subtracting the second frequency from the first frequency is passed through the signal after multiplication in the multiplication means. A configuration including a variable filter is adopted.

  According to these configurations, one of the signals to be multiplied with each other is output to the multiplier or cut off, and a filter that passes a desired signal from the multiplied signal is passed through, with a small number of component configurations. It is possible to realize a PLL frequency synthesizer that can vary the frequency over a wide band and has good C / N characteristics.

  The PLL frequency synthesizer of the present invention includes a reference signal oscillating means for oscillating a reference signal having a frequency serving as a reference for oscillation, and the first oscillating means divides the oscillated signal and the reference signal to obtain a phase. The comparison is performed, the frequency deviation is corrected based on the comparison result, and the second oscillating means multiplies the reference signal and outputs it to the selection output means.

  According to this configuration, by multiplying the signal obtained by multiplying the reference signal by the signal generated by the PLL oscillation, a PLL frequency synthesizer capable of changing the frequency in a wide band and having good C / N characteristics can be realized with a smaller number of component configurations. be able to.

  In the PLL frequency synthesizer of the present invention, the second oscillating means corresponds to a result of the phase comparison, a phase comparing means for comparing the phases of signals obtained by dividing the frequency of the reference signal and the oscillated signal, respectively. Variable oscillation means for changing the frequency of the oscillating signal, and the PLL frequency synthesizer operates the phase comparison means and the variable oscillation means when the output selection means outputs only the signal of the first frequency. The structure which comprises the control means which stops is taken.

  According to this configuration, by controlling the power supply voltage of the PLL that does not use the oscillated signal and stopping the operation, the PLL power frequency synthesizer with a wide bandwidth can be varied and the C / N characteristic is good. Can be made.

  The PLL frequency synthesizer of the present invention adopts a configuration for generating a signal having a frequency of 1 GHz or more. The PLL frequency synthesizer of the present invention adopts a configuration for generating a signal having a frequency of 2 GHz or more. The PLL frequency synthesizer of the present invention adopts a configuration for generating a signal having a frequency of 4 GHz or more.

  According to these configurations, a PLL frequency synthesizer with better C / N characteristics can be realized.

  A radio communication apparatus according to the present invention includes the PLL frequency synthesizer, and adopts a configuration in which a baseband or intermediate frequency transmission signal is multiplied by a signal generated by the PLL frequency synthesizer and converted to a radio frequency.

  According to this configuration, the signal oscillated by the PLL frequency synthesizer of the present invention having good C / N characteristics can be used for various wireless communication devices such as mobile phones, PHS, wireless LANs, etc., so that the C / N characteristics are good. A wireless communication device can be realized.

  The frequency oscillation method of the present invention outputs a first signal having a variable frequency, outputs a second signal having a frequency for interpolating the frequency variable range, and multiplies the first signal and the second signal, Selectively output one of the signal of the first frequency, the signal of the frequency obtained by multiplying the first frequency and the second frequency, and the frequency obtained by subtracting the second frequency from the first frequency. I tried to do it.

  According to this method, a first signal having a variable frequency is oscillated, a signal having a second frequency that complements the variable range of this signal is oscillated, and the first signal and the second signal are mixed. By filtering and outputting a desired frequency from the signal, it is possible to generate a signal variably at a wide frequency with good C / N characteristics.

  As described above, according to the PLL frequency synthesizer of the present invention, it is possible to generate a signal with a wide frequency variable and good C / N characteristics.

  The gist of the present invention is obtained by oscillating a first signal having a variable frequency, oscillating a signal having a second frequency that complements the variable range of the signal, and mixing the first signal and the second signal. By filtering the desired frequency from the signal and outputting it, or by outputting the first signal as it is, it is possible to generate a signal having a wide frequency variable and good C / N characteristics.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a PLL frequency synthesizer according to Embodiment 1 of the present invention. The PLL frequency synthesizer 100 of FIG. 1 mainly includes a reference signal oscillator 101, a PLL 102, a PLL 103, an output selection unit 104, a control unit 105, and an output terminal 106.

  The PLL 102 mainly includes a frequency divider 121, a phase comparator 122, a loop filter 123, a voltage controlled oscillator 124, a multiplier 125, and a frequency divider 126.

  The PLL 103 mainly includes a frequency divider 131, a phase comparator 132, a loop filter 133, a voltage controlled oscillator 134, a multiplier 135, and a frequency divider 136.

  The output selection unit 104 mainly includes a switch (hereinafter referred to as SW) 141, SW 142, multiplier 143, SW 144, filter 145, filter 146, and SW 147.

  In FIG. 1, a reference signal oscillator 101 outputs a signal having a reference frequency f0 to a frequency divider 121 and a frequency divider 131.

  The frequency divider 121 divides the signal having the reference frequency f 0 and outputs the signal to the phase comparator 122. The phase comparator 122 compares the phase of the signal output from the frequency divider 121 and the signal output from the frequency divider 126 and outputs a phase difference signal to the loop filter 123. The loop filter 123 converts the phase difference signal into a voltage and outputs it to the voltage controlled oscillator 124.

  Based on the phase difference signal, the voltage controlled oscillator 124 generates a signal at a frequency at which the phase difference between the signal output from the frequency divider 121 and the signal output from the frequency divider 126 is eliminated, and the multiplier 125 and the frequency divider Output to the device 126. The multiplier 125 multiplies the signal output from the voltage controlled oscillator 124 to the frequency f1 and outputs it to the SW 141. The frequency divider 126 divides the signal output from the voltage controlled oscillator 124 and outputs it to the phase comparator 122.

  The PLL 103 generates and controls signals by PLL control as with the PLL 102. The frequency divider 131 divides the signal of the reference frequency f0 and outputs it to the phase comparator 132. The phase comparator 132 compares the phase of the signal output from the frequency divider 131 with that of the signal output from the frequency divider 136, and outputs a phase difference signal to the loop filter 133. The loop filter 133 converts the phase difference signal into a voltage and outputs the voltage to the voltage controlled oscillator 134.

  Based on the phase difference signal, the voltage controlled oscillator 134 generates a signal at a frequency at which the phase difference between the signal output from the frequency divider 131 and the signal output from the frequency divider 136 is eliminated, and the multiplier 135 and the frequency divider To the device 136. The multiplier 135 multiplies the signal output from the voltage controlled oscillator 134 to the frequency f2, and outputs the result to the multiplier 143. The frequency divider 136 divides the signal output from the voltage controlled oscillator 134 and outputs it to the phase comparator 132.

  When the signal of the frequency f1 generated in the PLL 102 is output from the output terminal 106, the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the SW 142, and the SW 142 outputs the signal of the frequency f1 output from the SW 141. The signal is output to the output terminal 106.

  Further, when a signal having a frequency obtained by adding or subtracting the frequency f2 to or from the frequency f1 is output from the output terminal 106, the SW 141 outputs the signal having the frequency f1 output from the multiplier 125 to the multiplier 143, and the SW 142 is set to SW 147. Is output to the output terminal 106.

  Multiplier 143 multiplies the signal of frequency f1 output from SW 141 and the signal of frequency f2 output from multiplier 135, and outputs the result to SW 144. As a result, the multiplier 143 combines the frequency signal obtained by adding or subtracting the frequency f2 to the frequency f1 and the frequency of other unnecessary components, and outputs the resultant signal to the SW 144.

  When the signal obtained by adding the frequency f2 to the frequency f1 is output from the output terminal 106, the SW 144 outputs the signal output from the multiplier 143 to the filter 145, and the filter 145 adds the frequency f2 to the frequency f1. , And the other frequency components are attenuated and output to SW 147. Then, SW 147 outputs the signal output from filter 145 to SW 142.

  When the signal obtained by subtracting the frequency f2 from the frequency f1 is output from the output terminal 106, the SW 144 outputs the signal output from the multiplier 143 to the filter 146, and the filter 146 subtracts the frequency f2 from the frequency f1. The frequency component is passed and the other frequency components are attenuated and output to SW 147. Then, SW 147 outputs the signal output from filter 146 to SW 142.

  The control unit 105 controls the SWs 141, 142, 144, and 147 according to the frequency of the signal output from the output terminal 106. FIG. 2 is a diagram illustrating an example of a control signal of the PLL frequency synthesizer according to the present embodiment.

  In FIG. 2, when the signal from the control unit 105 is H, the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the SW 142. When the signal from the control unit 105 is L, the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the multiplier 143.

  When the H signal is input from the control unit 105, the upper terminal in FIG. 1 is selected as the SW, and when the L signal is input, the lower terminal in FIG. 1 is selected as the SW. That is, when the signal from the control unit 105 is H (High), the SW 142 outputs the signal output from the SW 141 to the output terminal 106. When the signal from the control unit 105 is L (Low), the SW 142 outputs the signal output from the SW 147 to the output terminal 106.

  On the other hand, when the signal from the control unit 105 is H, the SW 144 outputs the signal output from the multiplier 143 to the filter 145. When the signal from the control unit 105 is L, the SW 144 outputs the signal output from the multiplier 143 to the filter 146.

  When the signal from the control unit 105 is H, the SW 147 outputs the signal output from the filter 145 to the SW 142. When the signal from the control unit 105 is L, the SW 147 outputs the signal output from the filter 146 to the SW 142.

  When the frequency f3 of the signal output from the output terminal 106 is set to f1, the control unit 105 outputs an H signal to the SW 141 and the SW 142.

  When the frequency f3 of the signal output from the output terminal 106 is set to f1 + f2, the control unit 105 outputs an L signal to SW141 and SW142 and outputs an H signal to SW144 and SW147.

  When the frequency f3 of the signal output from the output terminal 106 is f1-f2, the control unit 105 outputs an L signal to SW141 and SW142, and outputs an L signal to SW144 and SW147.

  Next, the operation of the PLL frequency synthesizer 100 according to the present embodiment will be described. Here, an operation for obtaining an oscillation signal having a frequency range of 4800 to 5200 MHz will be described with reference to FIGS. FIG. 3 is a diagram showing an output frequency range of the PLL frequency synthesizer of the present embodiment. The horizontal axis in FIG. 3 indicates the frequency. F1 represents the output frequency of the PLL 102, and f2 represents the output frequency of the PLL 103. Δf 1 indicates the output frequency variable range of the PLL 102, and Δf 2 indicates the variable range of the output frequency of the PLL 103.

As shown in FIG. 3, the PLL frequency synthesizer of the present embodiment has a frequency in the range of Δf1 + Δf2 centered on f1-f2, a frequency in the range of Δf1 centered on f1, and a range of Δf1 + Δf2 centered on f1 + f2. A signal can be generated at a frequency. Here, when the following conditions are satisfied, a continuous frequency band can be covered.
Δf1 + 0.5 × Δf2 ≧ f2

  For example, the oscillation frequency f1 of the first voltage controlled oscillator 124 is 986 to 1014 MHz (frequency variable width 28 MHz), the multiplication number of the first multiplier 125 is 5, and the oscillation frequency f2 of the second voltage controlled oscillator 134 is 140 MHz, the multiplication factor of the second multiplier 135 is 1, and the oscillation frequency f0 of the reference signal oscillator 101 is 10 MHz.

In this case, the output frequencies f1 and f2 of the first and second PLLs are as follows.
f1 = (986 to 1014 MHz) × 5
= 4930-5070MHz
f2 = 140MHz

Here, when the control shown in FIG.
When SW141 = H and SW142 = H,
f3 = f1
= 4930-5070MHz
When SW141 = L, SW144 = H, SW147 = H, SW142 = L, the filter 145 is selected,
f3 = f1 + f2
= 5070-5210 MHz
When SW141 = L, SW144 = L, SW147 = L, SW142 = L, the filter 146 is selected,
f3 = f1-f2
= 4790-4930MHz
It becomes. Therefore, a variable width of 420 MHz from 4790 to 5210 MHz can be realized.

  Compared with the conventional example, in the conventional example, in order to realize a variable width of 400 MHz with the same multiplication factor, a voltage controlled oscillator having a frequency variable width of 40 MHz is necessary. In the present invention, a voltage controlled oscillator having a frequency variable width of 28 MHz is used. By using this, a variable width of 420 MHz can be realized. That is, in the present invention, since the control voltage sensitivity of the voltage controlled oscillator may be low, the C / N characteristic of the voltage controlled oscillator is better than the conventional example. In addition, the frequency to be mixed with the output signal of the voltage controlled oscillator also requires a 300 MHz reference signal in the conventional example.

  A crystal oscillator or the like having a good C / N characteristic is used as the normal reference signal. For example, the C / N characteristic deteriorates at 20 * Log (frequency multiplication) [dB] with respect to a 10 MHz reference signal.

  FIG. 4 is a diagram illustrating an example of the C / N characteristic of the PLL frequency synthesizer of the present embodiment. In FIG. 4, the vertical axis represents C / N, and the horizontal axis represents the logarithm of the detuning frequency. In the conventional example, the degradation is 29.5 dB with respect to the C / N of the 10 MHz signal.

  In the present invention, a 140 MHz voltage-controlled oscillator is used, but since the second PLL 103 is provided, the C / N in the vicinity can realize a C / N comparable to that of the reference signal.

  Here, since the reference signal is 10 MHz, it is possible to realize better characteristics for the vicinity C / N than the vicinity C / N characteristics of the conventional 300 MHz signal. As for the far C / N, the C / N characteristic is advantageous because the oscillation frequency of the voltage controlled oscillator is as low as 140 MHz, and the far C / N characteristic can be improved by the filtering effect of the loop filter.

  Therefore, the C / N of the 140 MHz signal used in the present invention can realize better characteristics than the 300 MHz reference signal. Since both C1 and F2 have better C / N characteristics than the conventional example, the C / N characteristics of f1 + f2 and f1-f2 obtained by mixing these two signals are also better.

  As described above, according to the PLL frequency synthesizer of the present embodiment, the first signal having a variable frequency of 1 GHz or more is oscillated, and the second frequency signal that complements the variable range of this signal is oscillated. By mixing the 1 signal and the second signal and filtering and outputting a desired frequency from the obtained signal, it is possible to generate a signal with a good C / N characteristic and a wide frequency range.

  Note that the PLL frequency synthesizer of this embodiment is particularly effective when outputting higher frequencies. 5, FIG. 6, FIG. 7, FIG. 8, and FIG. 9 are diagrams showing examples of frequency characteristics. In these figures, the vertical axis represents C / N, and the horizontal axis represents the detuning frequency.

  FIG. 5 shows an example in which a 5 GHz signal is oscillated. In FIG. 5, a VCO (Voltage Controlled Oscillator) of a type that directly oscillates a frequency from 4780 MHz to 5356 MHz is −53 dB at a detuning frequency of 1 kHz. On the other hand, in the PLL 102 that multiplies about 600 MHz by 8, the detuning frequency of 1 kHz is −86.9 dB.

  Further, the variable width of the frequency is only half that of a direct oscillation type VCO, and in the PLL 103 of 134 MHz to 246 MHz, the detuning frequency of 1 kHz is −80.0 dB. The PLL frequency synthesizer according to the present embodiment in which the PLL 102 and the PLL 103 are combined is -79.2 dB at a detuning frequency of 1 kHz.

  Although the conventional direct oscillation VCO does not realize the C / N ratio necessary for the low noise PLL frequency synthesizer, the PLL frequency synthesizer of the present embodiment has almost the C / N ratio necessary for the low noise PLL frequency synthesizer. Clear.

  Next, an example in which a 4 GHz signal is oscillated will be described. In FIG. 6, in a VCO that directly oscillates a frequency from 3500 MHz to 4000 MHz, the detuning frequency of 1 kHz is −70 dB. On the other hand, in the PLL 102 that multiplies about 600 MHz by 6, the detuning frequency of 1 kHz is −89.4 dB.

  Similar to FIG. 5, the variable width of the frequency is only half that of a direct oscillation type VCO, and in the PLL 103 of 134 MHz to 246 MHz, the detuning frequency of 1 kHz is −80.0 dB. The PLL frequency synthesizer according to the present embodiment in which the PLL 102 and the PLL 103 are combined is -79.5 dB at a detuning frequency of 1 kHz.

  As described above, even when a 4 GHz signal is oscillated, the conventional direct oscillation VCO does not realize the C / N ratio necessary for the low noise PLL frequency synthesizer, as in the 5 GHz example. The form of the PLL frequency synthesizer substantially clears the C / N ratio required for the low noise PLL frequency synthesizer.

  Next, an example in which a 3 GHz signal is oscillated will be described. In FIG. 7, in a VCO of a type that directly oscillates a frequency from 2600 MHz to 3110 MHz, the detuning frequency of 1 kHz is −66.0 dB. On the other hand, in the PLL 102 that multiplies about 600 MHz by 5, the detuning frequency of 1 kHz is −91.0 dB.

  Similar to FIG. 5, the variable width of the frequency is only half that of a direct oscillation type VCO, and in the PLL 103 of 134 MHz to 246 MHz, the detuning frequency of 1 kHz is −80.0 dB. The PLL frequency synthesizer according to the present embodiment in which the PLL 102 and the PLL 103 are combined is -78.7 dB at a detuning frequency of 1 kHz.

  Thus, even when a 3 GHz signal is oscillated, as in the 5 GHz example, the conventional direct oscillation VCO does not realize the C / N ratio necessary for the low noise PLL frequency synthesizer. The form of the PLL frequency synthesizer substantially clears the C / N ratio required for the low noise PLL frequency synthesizer.

  Next, an example in the case of oscillating a 2 GHz signal will be described. In FIG. 8, in a VCO that directly oscillates a frequency from 1600 MHz to 2700 MHz, the detuning frequency of 1 kHz is −75.0 dB. On the other hand, in the PLL 102 that multiplies about 600 MHz by 3, the detuning frequency of 1 kHz is −95.5 dB.

  In comparison with a direct oscillation type VCO, the frequency variable width is half, and in the PLL 103 of 530 MHz to 670 MHz, the detuning frequency of 1 kHz is −82.0 dB. The PLL frequency synthesizer of the present embodiment in which the PLL 102 and the PLL 103 are combined becomes −81.8 dB at a detuning frequency of 1 kHz.

  Similar to the above example, even when a 2 GHz signal is oscillated, the conventional direct oscillation VCO does not realize the C / N ratio necessary for the low noise PLL frequency synthesizer, but the PLL frequency synthesizer of the present embodiment. Almost clears the C / N ratio required for a low noise PLL frequency synthesizer.

  Next, an example in which a 1 GHz signal is oscillated will be described. In FIG. 9, in a VCO that directly oscillates a frequency from 1295 MHz to 1385 MHz, the detuning frequency of 1 kHz is −85.0 dB. On the other hand, in the PLL 102 that doubles about 600 MHz, the detuning frequency of 1 kHz is −99.0 dB.

  Compared with a direct oscillation type VCO, the variable frequency range is half, and in the PLL 103 of 0 Hz to 50 MHz, the detuning frequency of 1 kHz is -126.9 dB. The PLL frequency synthesizer according to the present embodiment in which the PLL 102 and the PLL 103 are combined becomes -99.0 dB at a detuning frequency of 1 kHz.

  As described above, when a signal of 1 GHz is oscillated, both the conventional direct oscillation VCO and the PLL frequency synthesizer of the present embodiment almost clear the C / N ratio necessary for the low noise PLL frequency synthesizer. The PLL frequency synthesizer of the present embodiment has lower noise.

  In any case, the PLL frequency synthesizer of the present embodiment is effective when the sum of the C / N of the PLL 102 and the C / N of the PLL 103 is lower than the C / N of the direct oscillation VCO.

  As described above, in the PLL frequency synthesizer of the present embodiment, the higher the frequency, the lower the detuning frequency dB and the lower the noise than the conventional method of direct oscillation.

(Embodiment 2)
FIG. 10 is a block diagram showing a configuration of a PLL frequency synthesizer according to Embodiment 2 of the present invention. 1 identical to those in FIG. 1 are assigned the same reference numerals as in FIG. 1, and detailed descriptions thereof are omitted.

  The PLL frequency synthesizer 1000 of FIG. 10 includes a control unit 1001, a phase comparator 1002, a voltage controlled oscillator 1003, and a multiplier 1004. When only a signal oscillated by one PLL is used, the other is oscillated. 1 is different from the PLL frequency synthesizer of FIG. 1 in that the operation is stopped by controlling the power supply voltage of the PLL that does not use the signal.

  In FIG. 10, the control unit 105 controls the SWs 141, 142, 144, and 147 according to the frequency of the signal output from the output terminal 106. Further, the control unit 105 notifies the control unit 1001 of the control content of the SWs 141, 142, 144, and 147.

  When the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the SW 142, the control unit 1001 operates by controlling the power supply voltage supplied to the phase comparator 1002, the voltage controlled oscillator 1003, and the multiplier 1004. To stop.

  The phase comparator 1002 compares the phase of the signal output from the frequency divider 131 with that of the signal output from the frequency divider 136, and outputs a phase difference signal to the loop filter 133. When the power supply voltage controlled by the control unit 1001 is lowered, the phase comparator 1002 stops the phase comparison operation.

  The voltage controlled oscillator 1003 generates a signal at a frequency that eliminates the phase difference between the signal output from the frequency divider 131 and the signal output from the frequency divider 136 based on the phase difference signal, and the multiplier 135 and the frequency divider. To 136. When the power supply voltage controlled by the control unit 1001 is lowered, the voltage controlled oscillator 1003 stops the signal generation operation.

  Multiplier 1004 multiplies the signal of frequency f1 output from SW 141 and the signal of frequency f2 output from multiplier 135, and outputs the result to SW 144. When the power supply voltage controlled by the control unit 1001 is lowered, the multiplier 1004 stops the signal multiplication operation.

  Next, the operation of the PLL frequency synthesizer 1000 will be described. FIG. 11 is a diagram illustrating an example of a control signal of the PLL frequency synthesizer according to the present embodiment.

  As shown in FIG. 11, when the control unit 105 outputs an H signal to the SW 141 and SW 142, that is, only the signal of the frequency f1 output from the PLL 102 is output, and the signal of the frequency f2 output from the PLL 103 is used. If not, the control unit 1001 controls the power supply voltages of the phase comparator 1002, the voltage controlled oscillator 1003, and the multiplier 1004 to stop the operation (OFF).

  When the control unit 105 outputs an L signal to the SW 141 and the SW 142, the signal is synthesized and output using both the frequency f1 signal output from the PLL 102 and the frequency f2 signal output from the PLL 103. The control unit 1001 operates (ON) the phase comparator 1002, the voltage controlled oscillator 1003, and the multiplier 1004.

  As described above, according to the PLL frequency synthesizer of the present embodiment, by controlling the power supply voltage of the PLL that does not use the oscillated signal and stopping the operation, it is possible to vary the frequency over a wide band and C / N The power consumption of the PLL frequency synthesizer with good characteristics can be reduced.

(Embodiment 3)
FIG. 12 is a block diagram showing a configuration of a PLL frequency synthesizer according to Embodiment 3 of the present invention. 1 identical to those in FIG. 1 are assigned the same reference numerals as in FIG. 1, and detailed descriptions thereof are omitted.

  The PLL frequency synthesizer 1200 of FIG. 12 includes an output selection unit 1201 and a control unit 1202, and outputs or blocks one of the signals to be multiplied with each other to the multiplier and generates a desired signal from the multiplied signal. 1 is different from the PLL frequency synthesizer of FIG. 1 in that a signal is passed through a filter.

  The output selection unit 1201 in FIG. 12 mainly includes a SW 1211, a multiplier 1212, a switch 1213, a filter 145, a filter 146, and a SW 1214.

  In FIG. 12, the control unit 1202 controls the SW 1211, SW 1213, and SW 1214 in accordance with the frequency f3 of the output signal.

  When the signal itself of the frequency f1 generated in the PLL 102 is output from the output terminal 106, the SW 1211 blocks the signal of the frequency f2 output from the multiplier 135. When a signal having a frequency obtained by adding or subtracting the frequency f2 to or from the frequency f1 is output from the output terminal 106, the SW 1211 outputs a signal having the frequency f2 output from the multiplier 135.

  Multiplier 1212 multiplies the signal of frequency f1 output from multiplier 125 and the signal output from SW1211 and outputs the result to SW1213.

  When the signal of the frequency f1 generated in the PLL 102 is output from the output terminal 106, the SW 1213 outputs the signal output from the multiplier 1212 to the SW 1214, and the SW 1214 outputs the signal output from the SW 1213 to the output terminal 106. To do.

  When the signal obtained by adding the frequency f2 to the frequency f1 is output from the output terminal 106, the SW 1213 outputs the signal output from the multiplier 1212 to the filter 145, and the filter 145 adds the frequency f2 to the frequency f1. And the other frequency components are attenuated and output to SW1214. Then, the SW 1214 outputs the signal output from the filter 145 to the output terminal 106.

  When the signal obtained by subtracting the frequency f2 from the frequency f1 is output from the output terminal 106, the SW 1213 outputs the signal output from the multiplier 1212 to the filter 146, and the filter 146 subtracts the frequency f2 from the frequency f1. The frequency component is allowed to pass, and other frequency components are attenuated and output to the SW 1214. Then, the SW 1214 outputs the signal output from the filter 146 to the output terminal 106.

  Next, the internal configuration of the multiplier 1212 will be described. FIG. 13 is a diagram showing an example of the internal configuration of the multiplier of the PLL frequency synthesizer of the present embodiment.

  The multiplier 1212 has the configuration shown in FIG. 13, and f1 is input to the input terminal 1311 and f2 is input to the input terminal 1314.

  In FIG. 13, a multiplier 1212 according to the present embodiment includes two transistors (first transistor) 1306 and a transistor (second transistor) 1307 forming a differential pair, and a transistor (cascode-connected to the transistor 1307 ( (Third transistor) 1308, a capacitor 1320 interposed between the base of the transistor 1307 and the ground, and an input circuit (first input circuit) interposed between the base of the transistor 1306 and the input terminal 1314. 1315, a bias circuit 1318 interposed between the base of the transistor 1306 and the DC power source 1319, a bias circuit 1321 interposed between the base of the transistor 1307 and the DC power source 1322, and the base of the transistor 1308 Input inserted between the input terminal 1311 A circuit (second input circuit) 1312, a bias circuit 1316 interposed between the base of the transistor 1308 and the DC power supply 1317, and a load 1309 inserted between the collector of the transistor 1306 and the DC power supply 1323 , And a load 1310 interposed between the collector of the transistor 1307 and the DC power source 1323.

  A signal from an oscillator (not shown) (for example, a local oscillator) is input to the input circuit 1315 and the input circuit 1312. In this case, if the frequency of the signal input to the input circuit 1312 is f1, and the frequency of the signal input to the input circuit 1315 is f2, a signal of a multiplied wave of f1 + f2 is output from the collectors of both the transistor 1306 and the transistor 1307. Is done.

  Here, when impedance matching of the output terminal 1313 is set to a doubled wave, a signal of f1 + f2 is output from the output terminal 1313. The signal having the frequency f1 is amplified by the cascode-connected transistor 1307 and the transistor 1308.

  The multiplier 1212 outputs the amplified f1 from the output terminal 1313 when the input signal is only f1, and outputs the f1 + f2 and f1-f2 signals when the input signals are f1 and f2. Operate.

  SW1211 is ON when H, that is, the signal of frequency f2 output from multiplier 135 is output to SW1212. Further, SW1211 is OFF when L, that is, SW1211 blocks the signal of frequency f2 output from multiplier 135.

  The SW 1213 outputs the signal output from the multiplier 1212 to the SW 1214 when H, outputs the signal output from the multiplier 1212 to the filter 145 when M (Middle), and multiplies when the signal is L. The signal output from the unit 1212 is output to the filter 146.

  Similarly, the SW 1214 outputs a signal output from the SW 1213 to the output terminal 106 when H, outputs a signal output from the filter 145 to the output terminal 106 when M, and outputs from the filter 146 when L. The output signal is output to the output terminal 106.

  When the control shown in FIG. 14 is performed, when SW1211 = L, SW1213 = H, and SW1214 = H, f3 = f1, and when SW1211 = H, SW1213 = M, and SW1214 = M, the filter 145 is selected. F3 = f1 + f2. When SW1211 = H, SW1213 = L, and SW1214 = L, the filter 146 is selected and f3 = f1-f2.

  As a result, the same operation as in the first embodiment can be realized.

  The multiplier 1212 used here is shown as an example. When the input signal is f1, the multiplier 1212 outputs f1, and when the input signals are f1 and f2, the multiplier 1212 outputs f1 + f2 or f1-f2. If so, it is not limited to this.

  As described above, according to the PLL frequency synthesizer of the present embodiment, one of the signals to be multiplied with each other is output to the multiplier or blocked, and the filter is passed through a filter that passes the desired signal from the multiplied signal. By doing so, it is possible to realize a PLL frequency synthesizer with a wide range of frequency variable and good C / N characteristics with a small number of components.

(Embodiment 4)
FIG. 15 is a block diagram showing a configuration of a PLL frequency synthesizer according to Embodiment 4 of the present invention. However, the same components as those in FIGS. 1 and 12 are denoted by the same reference numerals as those in FIGS. 1 and 12, and detailed description thereof is omitted.

  A PLL frequency synthesizer 1500 shown in FIG. 15 includes a control unit 1501, a phase comparator 1502, and a voltage controlled oscillator 1503. When only a signal oscillated by one PLL is used, the other oscillated signal is not used. 12 is different from the PLL frequency synthesizer of FIG. 12 in that the operation is stopped by controlling the power supply voltage of the PLL.

  In FIG. 15, the control unit 1202 controls the SWs 1211, 1213, and 1214 according to the frequency of the signal output from the output terminal 106. In addition, the control unit 1202 notifies the control unit 1501 of the control content of the SWs 1211, 1213, and 1214.

  When the SW 1211 does not output the signal of the frequency f1 output from the multiplier 125 to the multiplier 1212, the control unit 1501 controls the power supply voltage supplied to the phase comparator 1502 and the voltage controlled oscillator 1503 to stop the operation.

  The phase comparator 1502 compares the phase of the signal output from the frequency divider 131 and the signal output from the frequency divider 136, and outputs a phase difference signal to the loop filter 133. When the power supply voltage controlled by the control unit 1501 is lowered, the phase comparator 1502 stops the phase comparison operation.

  Based on the phase difference signal, the voltage controlled oscillator 1503 generates a signal at a frequency at which the phase difference between the signal output from the frequency divider 131 and the signal output from the frequency divider 136 is eliminated, and the multiplier 135 and the frequency divider To the device 136. When the power supply voltage controlled by the control unit 1501 is lowered, the voltage controlled oscillator 1503 stops the signal generation operation.

  Next, the operation of the PLL frequency synthesizer 1500 will be described. FIG. 16 is a diagram illustrating an example of a control signal of the PLL frequency synthesizer according to the present embodiment.

  As shown in FIG. 16, when the control unit 1202 gives an instruction to shut off the SW 1211, the control unit 1501 controls the power supply voltage of the phase comparator 1502 and the voltage controlled oscillator 1503 in the PLL 103 to stop the operation. (OFF). Note that the power supply to the PLL 102 remains ON regardless of the operation of the SW 1211.

  That is, when f3 = f1, the phase comparator 1502 and the voltage controlled oscillator 1503 do not need to operate, so that the power can be turned off and the power consumption can be reduced. When f3 = f1 + f2 and f3 = f1-f2, the phase comparator 1502 and the voltage controlled oscillator 1503 are turned on to operate.

  As described above, according to the PLL frequency synthesizer of the present embodiment, by controlling the power supply voltage of the PLL that does not use the oscillated signal and stopping the operation, it is possible to vary the frequency over a wide band and C / N The power consumption of the PLL frequency synthesizer with good characteristics can be reduced.

(Embodiment 5)
FIG. 17 is a block diagram showing a configuration of a PLL frequency synthesizer according to the fifth embodiment of the present invention. 1 identical to those in FIG. 1 are assigned the same reference numerals as in FIG. 1, and detailed descriptions thereof are omitted.

  The PLL frequency synthesizer 1700 of FIG. 17 includes a multiplier 1701 and is different from the PLL frequency synthesizer of FIG. 1 in that a signal obtained by multiplying a reference signal is multiplied by a signal generated by PLL oscillation.

  The reference signal oscillator 101 outputs a signal having a reference frequency f0 to the frequency divider 121 and the multiplier 1701. The multiplier 1701 multiplies the signal having the reference frequency f0 and outputs the signal to the multiplier 143.

  Next, the operation will be described. When realizing the same operation as that of the first embodiment of the present invention, the multiplication number of the multiplier 1701 is 14. At this time, f2 multiplies the reference signal f0 by 14, so that 20 Log (14) = 22.9 dB is deteriorated from the C / N characteristic of f0. Here, when the C / N characteristic of f2 is better than the C / N characteristic of the output signal f2 of the second PLL in the first embodiment, only the multiplier is used without using the second PLL. Equivalent C / N characteristics can be realized.

  As described above, according to the PLL frequency synthesizer of the present embodiment, by multiplying the signal obtained by multiplying the reference signal by the signal generated by the PLL oscillation, it is possible to vary the frequency in a wide band with a smaller number of components, and C / A PLL frequency synthesizer with good N characteristics can be realized.

(Embodiment 6)
FIG. 18 is a block diagram showing a configuration of a PLL frequency synthesizer according to the sixth embodiment of the present invention. However, the same components as those in FIGS. 1 and 10 are denoted by the same reference numerals as those in FIGS. 1 and 10, and detailed description thereof is omitted.

  A PLL frequency synthesizer 1800 in FIG. 18 includes a control unit 1801, a control unit 1802, and a variable bandpass filter (BPF) 1803. The filter frequency synthesizer 1800 has a variable pass frequency band and uses a frequency signal after multiplication. It differs from the PLL frequency synthesizer of FIGS. 1 and 10 in that the desired signal is obtained by changing the pass band.

  The control unit 1801 controls the SWs 141 and 142 according to the frequency of the signal output from the output terminal 106.

  When the signal of the frequency f1 generated in the PLL 102 is output from the output terminal 106, the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the SW 142, and the SW 142 outputs the signal of the frequency f1 output from the SW 141. The signal is output to the output terminal 106.

  When a signal having a frequency obtained by adding or subtracting the frequency f2 to or from the frequency f1 is output from the output terminal 106, the SW 141 outputs the signal having the frequency f1 output from the multiplier 125 to the multiplier 1004, and the SW 142 is variable. The signal output from the bandpass filter 1803 is output to the output terminal 106.

  The control unit 1802 instructs a frequency band to be passed through the variable bandpass filter 1803. The variable bandpass filter 1803 passes the frequency band designated from the signal outputted from the multiplier 1004 and outputs it to the SW 142 in accordance with the instruction from the control unit 1802.

  Next, the operation will be described. FIG. 19 is a diagram illustrating an example of a control signal of the PLL frequency synthesizer according to the present embodiment.

  In FIG. 19, when the signal from the control unit 1801 is H, the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the SW 142. When the signal from the control unit 1801 is L, the SW 141 outputs the signal of the frequency f1 output from the multiplier 125 to the multiplier 1004.

  When the signal from the control unit 1801 is H, the SW 142 outputs the signal output from the SW 141 to the output terminal 106. When the signal from the control unit 105 is L, the SW 142 outputs the signal output from the variable bandpass filter 1803 to the output terminal 106.

  In addition, when the signal having the frequency f1 + f2 is output from the output terminal 106, the control unit 1802 performs control to set the pass frequency band of the variable bandpass filter 1803 to f1 + f2. Similarly, when the control unit 1802 outputs a signal having the frequency f1-f2 from the output terminal 106, the control unit 1802 performs control to set the pass frequency band of the variable bandpass filter 1803 to f1-f2. When outputting the signal of the frequency f1 from the output terminal 106, since the variable band pass filter 1803 is not used, the frequency band is not particularly indicated.

As shown in FIG. 19, when the control of the control unit 1801 is SW141 = H and SW142 = H,
f3 = f1
When SW141 = L and SW142 = L, when the control unit 1802 controls the pass frequency band of the variable bandpass filter 1803 to f1 + f2,
f3 = f1 + f2
When SW141 = L and SW142 = L, the control unit 1802 controls the pass frequency band of the variable bandpass filter 1803 to f1-f2,
f3 = f1-f2
It becomes.

  As described above, according to the PLL frequency synthesizer of the present embodiment, by making the pass frequency band of the filter variable, it is possible to change the frequency in a wide band with a configuration using one filter, and C / N characteristics are improved. A good PLL frequency synthesizer can be realized.

(Embodiment 7)
FIG. 20 is a block diagram showing a configuration of a PLL frequency synthesizer according to the seventh embodiment of the present invention. However, the same components as those in FIGS. 1 and 10 are denoted by the same reference numerals as those in FIGS. 1 and 10, and detailed description thereof is omitted.

  A PLL frequency synthesizer 2000 of FIG. 20 includes a control unit 2001, a SW 2002, a multiplier 2003, a control unit 2004, and a variable bandpass filter 2005, and the frequency band of the filter is variable, and a frequency signal is transmitted. It differs from the PLL frequency synthesizer of FIGS. 1 and 10 in that a desired signal is obtained by changing the passband of the filter used after multiplication.

  In FIG. 20, the control unit 2001 controls the SW 2002 corresponding to the frequency f3 of the signal to be output.

  When outputting the signal of the frequency f 1 generated in the PLL 102 from the output terminal 106, the SW 2002 blocks the signal of the frequency f 2 output from the multiplier 135 to the multiplier 2003. In addition, when a signal having a frequency obtained by adding or subtracting the frequency f2 to or from the frequency f1 is output from the output terminal 106, the SW 2002 outputs a signal having the frequency f2 output from the multiplier 135.

  Multiplier 2003 multiplies the signal of frequency f1 output from multiplier 125 and the signal output from SW2002, and outputs the result to variable bandpass filter 2005.

  The control unit 2004 instructs a frequency band to be passed through the variable bandpass filter 2005. The variable bandpass filter 2005 passes the frequency band designated from the signal outputted from the multiplier 2003 and outputs it to the output terminal 106 in accordance with the instruction from the control unit 2004.

  Next, the operation will be described. FIG. 21 is a diagram illustrating an example of a control signal of the PLL frequency synthesizer according to the present embodiment.

  The SW 2002 is ON when H, that is, the signal output from the multiplier 135 is output to the multiplier 2003. Also, SW2002 is OFF when L, that is, SW2002 cuts off the signal of frequency f2 output from multiplier 135.

  In addition, when outputting a signal having the frequency f1 + f2 from the output terminal 106, the control unit 2004 performs control to set the pass frequency band of the variable bandpass filter 2005 to f1 + f2. Similarly, when the control unit 2004 outputs a signal having the frequency f1-f2 from the output terminal 106, the control unit 2004 performs control to set the pass frequency band of the variable bandpass filter 2005 to f1-f2. When a signal having a frequency f1 is output from the output terminal 106, control is performed so that the pass frequency band of the variable bandpass filter 2005 is f1.

As shown in FIG. 21, when the control of the control unit 2001 is SW2002 = OFF,
When the control unit 2004 controls the pass frequency band of the variable bandpass filter 2005 to f1,
f3 = f1
When SW2002 = ON, the control unit 2004 controls the pass frequency band of the variable bandpass filter 2005 to f1 + f2.
f3 = f1 + f2,
When SW2002 = ON, the control unit 2004 controls the pass frequency band of the variable bandpass filter 2005 to f1-f2.
f3 = f1-f2
It becomes.

  Thus, according to the PLL frequency synthesizer of the present embodiment, the filter frequency band is made variable, and the filter is used by changing the pass band of the filter used after multiplication of the frequency signal to obtain a desired signal. By using one configuration, it is possible to realize a PLL frequency synthesizer that can vary the frequency over a wide band and has good C / N characteristics.

(Embodiment 8)
FIG. 22 is a block diagram showing a configuration of a PLL frequency synthesizer according to the eighth embodiment of the present invention. 1 identical to those in FIG. 1 are assigned the same reference numerals as in FIG. 1, and detailed descriptions thereof are omitted.

  The PLL frequency synthesizer 2200 of FIG. 22 includes a distributor 2201, a multiplier 2202, a distributor 2203, a filter 2204, a filter 2205, an output terminal 2206, an output terminal 2207, and an output terminal 2208. 1 is different from the PLL frequency synthesizer of FIG. 1 in that signals in a plurality of frequency bands are output.

  The distributor 2201 distributes the signal of the frequency f 1 output from the multiplier 125 and outputs the signal to the output terminal 2206 and the multiplier 2202. Multiplier 2202 multiplies the distributed signal of frequency f 1 and the signal of frequency f 2 output from multiplier 135 and outputs the result to distributor 2203.

  Distributor 2203 distributes the multiplied signal and outputs it to filter 2204 and filter 2205. The filter 2204 passes the frequency component obtained by adding the frequency f2 to the frequency f1, attenuates other frequency components, and outputs the result to the output terminal 2207. The filter 2205 passes the frequency component obtained by subtracting the frequency f2 from the frequency f1, attenuates other frequency components, and outputs the result to the output terminal 2208.

Next, the operation will be described with reference to FIG. The output terminal 2206 outputs the output signal of the PLL 102 distributed by the distributor 2201, so the output frequency is
f4 = f1
It becomes. As for the signal at the output terminal 2207, the output signal f 1 of the PLL 102 and the output signal f 2 of the PLL 103 are multiplied by the multiplier 2202, and then distributed by the distributor 2203 and input to the filter 2204. Since the pass frequency band of the filter 2204 is set to f1 + f2,
f5 = f1 + f2
It becomes. As for the signal at the output terminal 2208, the output signal f 1 of the PLL 102 and the output signal f 2 of the PLL 103 are multiplied by the first multiplier 2202, and then distributed by the distributor 2203 and input to the filter 2205. Since the pass frequency band of the filter 2205 is set to f1-f2.
f6 = f1-f2
It becomes.

  As described above, according to the PLL frequency synthesizer of the present embodiment, it is possible to realize a PLL frequency synthesizer that can output three frequencies at the same time, can perform a wide frequency variable, and has good C / N characteristics. it can.

  In the above-described embodiment, a plurality of wideband frequency signals can be generated by the frequency variable range of the PLL 102 and the PLL 103.

When the variable width of the output frequency of the PLL 102 is Δf1 and the variable width of the output frequency of the PLL 103 is Δf2, the output frequencies f4, f5, and f6 are as follows.
f4 = f1 + Δf1
f5 = f1 + f2 + Δf1 + Δf2
f6 = f1-f2 + Δf1-Δf2
For example, it is assumed that the center frequency f1 is 4 GHz and the channel interval f2 is 100 MHz.

Here, when the center frequency is increased by 100 MHz, the output frequency of the PLL 102 is increased by 100 MHz. That is, Δf1 is set to +100 MHz.
f4 = 4 GHz + 100 MHz = 4.1 GHz
f5 = 4 GHz + 100 MHz + 100 MHz = 4.2 GHz
f6 = 4 GHz-100 MHz + 100 MHz = 4.0 GHz
When the channel interval is increased by 10 MHz, the output frequency of the PLL 103 is increased by 10 MHz. That is, Δf2 is set to +10 MHz.
f4 = 4GHz
f5 = 4 GHz + 100 MHz + 10 MHz = 4.11 GHz
f6 = 4 GHz-100 MHz-10 MHz = 3.89 GHz
When the center frequency is lowered by 200 MHz and the channel interval is reduced by 20 MHz, the output frequency of the PLL 102 is lowered by 200 MHz, and the output frequency of the PLL 103 is lowered by 20 MHz. That is, Δf1 is set to −200 MHz, and Δf2 is set to −20 MHz.
f4 = 4 GHz-200 MHz = 3.8 GHz
f5 = 4 GHz + 100 MHz−200 MHz−20 MHz = 3.88 GHz
f6 = 4 GHz-100 MHz-200 MHz + 20 MHz = 3.72 GHz

(Embodiment 9)
The PLL frequency synthesizers of the first to eighth embodiments are suitable for use when multiplying an oscillated signal by a baseband or intermediate frequency signal and converting it to a radio frequency.

  In this embodiment, paying attention to this point, the signal generated by the PLL frequency synthesizer of the first to eighth embodiments having good C / N characteristics is used for various wireless communication devices such as mobile phones, PHS, and wireless LANs. suggest. As a result, a wireless communication device having good C / N characteristics can be realized.

  The PLL frequency synthesizer of the present invention is suitable for use in a wireless communication device.

The block diagram which shows the structure of the PLL frequency synthesizer which concerns on Embodiment 1 of this invention. The figure which shows an example of the control signal of the PLL frequency synthesizer of the said embodiment The figure which shows the output frequency range of the PLL frequency synthesizer of the said embodiment The figure which shows an example of the C / N characteristic of the PLL frequency synthesizer of the said embodiment Diagram showing an example of frequency characteristics Diagram showing an example of frequency characteristics Diagram showing an example of frequency characteristics Diagram showing an example of frequency characteristics Diagram showing an example of frequency characteristics The block diagram which shows the structure of the PLL frequency synthesizer concerning Embodiment 2 of this invention. The figure which shows an example of the control signal of the PLL frequency synthesizer of the said embodiment The block diagram which shows the structure of the PLL frequency synthesizer which concerns on Embodiment 3 of this invention. The figure which shows an example of the internal structure of the multiplier of the PLL frequency synthesizer of the said embodiment The figure which shows an example of the control signal of the PLL frequency synthesizer of the said embodiment Block diagram showing the configuration of a PLL frequency synthesizer according to Embodiment 4 of the present invention The figure which shows an example of the control signal of the PLL frequency synthesizer of the said embodiment Block diagram showing a configuration of a PLL frequency synthesizer according to a fifth embodiment of the present invention A block diagram showing a configuration of a PLL frequency synthesizer according to a sixth embodiment of the present invention. The figure which shows an example of the control signal of the PLL frequency synthesizer of the said embodiment Block diagram showing a configuration of a PLL frequency synthesizer according to a seventh embodiment of the present invention The figure which shows an example of the control signal of the PLL frequency synthesizer of the said embodiment A block diagram showing a configuration of a PLL frequency synthesizer according to an eighth embodiment of the present invention. Block diagram showing the configuration of a conventional PLL frequency synthesizer

Explanation of symbols

101 Reference signal oscillator 102, 103 PLL
104, 1201 Output selection unit 105, 1001, 1202, 1501, 1801, 1802, 2001, 2004 Control unit 141, 142, 144, 147, 1211, 1213, 1214, 2002 Switch (SW)
143, 1004, 1212, 2003, 2202 Multiplier 145, 146, 2204, 2205 Filter 122, 132, 1002, 1502 Phase comparator 124, 134, 1003, 1503 Voltage controlled oscillator 125, 135, 1701 Multiplier 1803, 2005 Variable Bandpass filter 2201, 2203 Divider 121, 126, 131, 136 Divider 123, 133 Loop filter 2206, 2207, 2208 Output 100, 1000, 1200, 1500, 1700, 1800, 2000, 2200 PLL frequency synthesizer 1311, 1314 Input terminal 1312, 1315 Input circuit 1313 Output terminal 1306, 1307, 1308 Transistor 1309, 1310 Load 1316, 1318, 1321 Bias circuit 1317, 1319, 1322, 1323 DC power supply 1320 Capacitor

Claims (10)

First oscillating means for outputting a first signal having a variable first frequency, second oscillating means for outputting a second signal having a second frequency for interpolating a frequency variable range, the first signal and the second signal To select one of the signal of the first frequency, the signal of the frequency obtained by adding the first frequency and the second frequency, and the signal of the frequency obtained by subtracting the second frequency from the first frequency. Output selection means for outputting automatically ,
The output selection unit includes a multiplication unit that multiplies the first signal and the second signal, a first filter that passes a signal having a frequency obtained by adding the first frequency and the second frequency, and the first filter A second filter that passes a signal having a frequency obtained by subtracting the second frequency from a frequency; a first switch that selects one of a signal output from the first filter and a signal output from the second filter; A second switch for selecting one of the signal output from the first switch and the first signal;
A PLL frequency synthesizer characterized by the above. First oscillating means for outputting a first signal having a variable first frequency, second oscillating means for outputting a second signal having a second frequency for interpolating a frequency variable range, the first signal and the second signal To select one of the signal of the first frequency, the signal of the frequency obtained by adding the first frequency and the second frequency, and the signal of the frequency obtained by subtracting the second frequency from the first frequency. Output selection means for outputting automatically ,
The output selection means includes: a first switch that outputs or does not output the second signal; a multiplication means that multiplies the output of the first switch and the first signal; and A first filter that passes a signal having a frequency obtained by adding an output and the first signal; a second filter that passes a signal having a frequency obtained by subtracting the output of the first switch from the first frequency; and the first filter. A second switch that selects any one of the signal output from the second filter, the signal output from the second filter, and the first signal;
A PLL frequency synthesizer characterized by the above. First oscillating means for outputting a first signal having a variable first frequency, second oscillating means for outputting a second signal having a second frequency for interpolating a frequency variable range, the first signal and the second signal To select one of the signal of the first frequency, the signal of the frequency obtained by adding the first frequency and the second frequency, and the signal of the frequency obtained by subtracting the second frequency from the first frequency. Output selection means for outputting automatically ,
The output selection means is a multiplication means for multiplying the first signal and the second signal, and a frequency obtained by adding the first frequency and the second frequency from the signal after multiplication in the multiplication means, or the first A variable filter that passes any signal having a frequency obtained by subtracting the second frequency from one frequency; and a switch that selects either the signal output from the variable filter or the first signal.
A PLL frequency synthesizer characterized by the above. First oscillating means for outputting a first signal having a variable first frequency, second oscillating means for outputting a second signal having a second frequency for interpolating a frequency variable range, the first signal and the second signal To select one of the signal of the first frequency, the signal of the frequency obtained by adding the first frequency and the second frequency, and the signal of the frequency obtained by subtracting the second frequency from the first frequency. Output selection means for outputting automatically ,
The output selection means includes a switch that performs either the output or the non-output of the second signal, a multiplication means that multiplies the output of the switch and the first signal, and a signal after multiplication in the multiplication means. A variable filter that passes a signal of any one of the first frequency, a frequency obtained by adding the first frequency and the second frequency, or a frequency obtained by subtracting the second frequency from the first frequency;
A PLL frequency synthesizer characterized by the above. Reference signal oscillating means for oscillating a reference signal having a frequency serving as an oscillation reference is provided, and the first oscillating means divides the oscillated signal and the reference signal to compare phases, and from the comparison result, compares the frequency. deviation correcting, the second oscillating means, PLL frequency synthesizer according to any one of claims 1 to 4 by multiplying the reference signal and outputs to the selection output means. The second oscillating means changes the frequency of the oscillating signal in accordance with the phase comparison means for comparing the phase of the signal obtained by dividing the signal having the reference frequency and the oscillated signal, respectively. The PLL frequency synthesizer includes control means for stopping the operation of the phase comparison means and the variable oscillation means when the output selection means outputs only the signal of the first frequency. The PLL frequency synthesizer according to any one of claims 1 to 4 , wherein The PLL frequency synthesizer according to any one of claims 1 to 6 , wherein a signal having a frequency of 1 GHz or more is generated. The PLL frequency synthesizer according to any one of claims 1 to 6 , wherein a signal having a frequency of 2 GHz or more is generated. The PLL frequency synthesizer according to any one of claims 1 to 6 , wherein a signal having a frequency of 4 GHz or more is generated. Radio communication device that converts the claims 1 and PLL frequency synthesizer according to claim 9, the radio frequency by multiplying the generated signal in the PLL frequency synthesizer to the transmission signal of a base band or intermediate frequency.

Images