WO2016037397A1 - Structure de dispositif finfet et son procédé de fabrication - Google Patents

Structure de dispositif finfet et son procédé de fabrication Download PDF

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Publication number
WO2016037397A1
WO2016037397A1 PCT/CN2014/088602 CN2014088602W WO2016037397A1 WO 2016037397 A1 WO2016037397 A1 WO 2016037397A1 CN 2014088602 W CN2014088602 W CN 2014088602W WO 2016037397 A1 WO2016037397 A1 WO 2016037397A1
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WIPO (PCT)
Prior art keywords
fin
source
region
drain
fins
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PCT/CN2014/088602
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English (en)
Chinese (zh)
Inventor
尹海洲
刘云飞
李睿
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中国科学院微电子研究所
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Publication of WO2016037397A1 publication Critical patent/WO2016037397A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
  • Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles.
  • devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced.
  • silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device.
  • the operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.
  • the invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect.
  • the structure includes:
  • first and second fins being located above the substrate and parallel to each other;
  • a gate stack covering sidewalls of the substrate and portions of the first and second fins
  • the source region being located in an area where the first fin is not covered by the gate stack;
  • the source end epitaxial region is located above one end of the first fin and has a length less than 1/2 of the length of the fin;
  • drain region being located in an area of the second fin not covered by the gate stack
  • drain extension region located above the other end of the second fin opposite to the source region epitaxial region, the length of which is less than 1/2 of the length of the fin;
  • a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.
  • first and second fins have the same height, thickness and width.
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the present invention also provides a U-shaped FinFET device manufacturing method, including:
  • first oxide layer and second oxide layer on the surface of the first and second fins not covered by the sidewalls, wherein the first and second oxide layers are located opposite to the first and second fins Both ends of the ground, the length of which is greater than 1/2 of the length of the fin;
  • the method of forming the first fin and the second fin is:
  • the channel material layer and the source/drain material layer are etched to form a first fin and a second fin.
  • the method for forming the first and second oxide layers is:
  • the first and second oxide layers are formed in regions not covered by the photoresist.
  • the method for forming the first and second oxide layers is dry oxidation; the method for forming the source-end epitaxial region and the drain-end epitaxial region is homoepitaxial; wherein the source-end epitaxial region is homoepitaxially grown And the in-situ doping of the drain extension region simultaneously, the concentration and type of doping impurities are the same as the source and drain regions.
  • first and second fins have the same height, thickness and width.
  • the method of forming the first and second fins is an anisotropic etching.
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the method of forming the gate stack is atomic layer deposition.
  • the method of removing a part of the gate stack is anisotropic selective etching.
  • the method of forming the source and drain regions is oblique ion implantation.
  • the method of forming the source and drain regions is side scatter.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. Since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current.
  • the device Since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device smaller. DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating the fabrication of source-drain contacts.
  • the present invention effectively reduces the parasitic resistance of the source and drain regions and improves the on-state current of the device.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • FIGS. 1 to 14 are schematic views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention; wherein, Figs. 10 to 13 are plan views shown from the top of the device; a projection along the length of the fin;
  • Figure 15 illustrates the final structure of a device formed in accordance with the method of the embodiments of the present invention.
  • the present invention provides a FinFET structure including: a substrate 100; a first fin 210 and a second fin 220, the first fin 210 and the second fin 220 being located on the substrate 100. Above, parallel to each other; a gate stack 300 covering the substrate and a sidewall of a portion of the first fin 210 and the second fin 220; a source region 410, the source region being located The first fin 210 is not covered by the gate stack; the source end epitaxial region 240 is located at a length less than one end of the first fin 210, and the length thereof is less than 1/2 of the length of the fin; the drain region 420, the drain region is located in a region where the second fin 220 is not covered by the gate stack; the drain extension region 250 is located at the opposite end of the second fin 220 opposite to the source region epitaxial region. Above, its length is less than 1/2 of the length of the fin.
  • the structure further includes a sidewall spacer 230 disposed on both sides of the first fin 210 and the second fin 220 for isolating the source region, the drain region, and the gate stack.
  • first fin 210 and the second fin 220 have the same height, thickness and width degree.
  • the gate stack includes an interface layer 310, a high-k dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340.
  • the height of the gate stack 300 is 1/2 to 3/4 of the height of the first and second fins 210 and 220.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. Since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current.
  • the device Since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device smaller. DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating the fabrication of source-drain contacts.
  • the present invention effectively reduces the parasitic resistance of the source and drain regions and improves the on-state current of the device.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • the semiconductor material of the substrate and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
  • the first substrate material is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like.
  • the substrate used is a silicon substrate.
  • the channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device.
  • the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used.
  • the doping impurities are five elements such as phosphorus and arsenic.
  • the channel region formed in the subsequent process has a doping concentration of 1e15 cm -3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device.
  • the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic;
  • the doping type of the channel material layer is P-type,
  • the doping impurity used is a group III element such as boron.
  • the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm -3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the structure after forming the source/drain material layer 120 is as shown in FIG. 2.
  • the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the height of the gate stack after the device is formed.
  • the thickness of the source/drain material layer 120 is H1.
  • the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching
  • the method can be dry etching or dry/wet etching.
  • the height after the etching of the first fin 210 and the second fin 220 is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench
  • the thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process
  • the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.
  • a gate stack 300 is formed over the substrate 100 and over the first fin 210 and the second fin 220, and is the same as the existing FinFET process.
  • the gate stack 300 includes an interface layer 310, a high-k dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340 in this order.
  • the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties.
  • the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO Or a combination thereof
  • the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG.
  • the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm.
  • the device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 5 .
  • the above-described process for forming a gate stack is formed by atomic layer deposition.
  • polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330.
  • a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry.
  • Mechanical polishing (CMP) the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330;
  • anisotropic selective engraving The polysilicon layer is directionally etched such that its surface is flush with the source/drain material layer 120, as shown in FIG.
  • the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove the portion above the polysilicon layer 340 to expose the fins. 7 is shown.
  • the source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.
  • a sidewall spacer 230 is formed on the exposed portion of the sidewall of the fin for separating the gate stack from the source and drain regions.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • the sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.
  • the first and second oxide layers 510, 520 are formed over the source and drain regions.
  • the source-drain region epitaxy is often used in the art to increase the source-drain region volume, thereby reducing the parasitic resistance, due to the symmetry of the device and the interconnection structure of the circuit, the extension portion
  • the source and drain regions are often connected to each other, that is, the source terminals of the plurality of devices are connected to the same potential, and the drain terminals are connected to the same potential.
  • the previous epitaxial method inevitably causes the source and drain regions of the same device to be turned on immediately without passing through the channel, and the device cannot operate.
  • the present invention proposes a novel source-drain epitaxial structure, that is, partial extension of the fins of the source and drain regions, and at the same time, the epitaxial portions thereof are staggered to each other, so that the source and drain regions are not in contact with each other. purpose. In this manner, the parasitic resistance of the U-shaped FinFET device of the present invention is effectively reduced.
  • the source-drain epitaxial region is formed by the following steps. First, as shown in FIG. 9, the device is covered with a photoresist 400. Next, the shapes of the first and second oxide layers are etched by using a mask to expose the surface of the fin surface where the oxide layer needs to be grown. , as shown in Figure 10. The specific etching process is a common means in the art, and will not be described herein.
  • the first and second oxide layers 240, 250 are formed in regions not covered by the photoresist.
  • the present invention employs dry oxygen oxidation.
  • the fin covered by the glue 400 is exposed, and the region does not form the first oxide layer 510 and the second oxide layer 520 due to the protection of the photoresist, as shown in FIG.
  • a source-drain epitaxial region 240 that is, raised-SD. Since a part of the fin is blocked by the oxide layer, epitaxial growth cannot be performed above the region, and the obtained source
  • the drain epitaxial region exists only above the region not covered by the oxide layer. Since the oxide layers on the first and second fins are located on opposite ends of the different fins, and the thickness thereof is greater than 1/2 of the length of the fins, the source-drain epitaxial regions that can be grown are also located at the first and second fins.
  • Figure 13 shows a top view of the device after epitaxially growing the source-drain epitaxial region, the front view of which is shown in Figure 14. In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.
  • a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.
  • the invention provides a novel source-drain epitaxial structure, that is, partial extension of the fins of the source region and the drain region, and at the same time, the epitaxial portions thereof are mutually staggered, thereby achieving the purpose of not contacting the source and drain regions, thereby solving the U. Since the source and drain regions are respectively located on two different fins, the FinFET device can be turned on by the existing epitaxial method, so that the source and drain regions of the same device can be turned on without passing through the channel, so that the device cannot work. The parasitic resistance of the U-shaped FinFET device in the present invention is effectively reduced.

Abstract

La présente invention concerne une structure de dispositif FinFET et son procédé de fabrication, comprenant : un substrat (100) ; des première et seconde ailettes parallèles (210, 220) situées au-dessus du substrat (100) ; une pile d'électrodes de grille (300) recouvrant le substrat (100) et la paroi latérale d'une partie des première et seconde ailettes (210, 220) ; une région de source (410) située dans la région de la première ailette (210) non recouverte par la pile d'électrodes de grille (300) ; une région épitaxiale d'extrémité de source (240) située au-dessus d'une extrémité de la première ailette (210) et présentant une longueur inférieure à la moitié de la longueur de l'ailette ; une région de drain (420) située dans la région de la seconde ailette (220) non recouverte par la pile d'électrodes de grille (300) ; et une région épitaxiale d'extrémité de drain (250) située dans la seconde ailette (220) et au-dessus d'une extrémité opposée à la région épitaxiale de région de source (410) et présentant une longueur inférieure à la moitié de la longueur de l'ailette. La conception ci-dessus résout efficacement un problème provoqué par un effet de canal court.
PCT/CN2014/088602 2014-09-10 2014-10-15 Structure de dispositif finfet et son procédé de fabrication WO2016037397A1 (fr)

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CN201410459154.7 2014-09-10
CN201410459154.7A CN105470298B (zh) 2014-09-10 2014-09-10 一种FinFET器件结构及其制造方法

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Publication number Priority date Publication date Assignee Title
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CN110890279B (zh) * 2018-09-11 2023-09-15 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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