WO2016037396A1 - Structure de finfet et son procédé de fabrication - Google Patents

Structure de finfet et son procédé de fabrication Download PDF

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Publication number
WO2016037396A1
WO2016037396A1 PCT/CN2014/088596 CN2014088596W WO2016037396A1 WO 2016037396 A1 WO2016037396 A1 WO 2016037396A1 CN 2014088596 W CN2014088596 W CN 2014088596W WO 2016037396 A1 WO2016037396 A1 WO 2016037396A1
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WO
WIPO (PCT)
Prior art keywords
fin
gate stack
manufacturing
fins
region
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PCT/CN2014/088596
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English (en)
Chinese (zh)
Inventor
尹海洲
刘云飞
李睿
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中国科学院微电子研究所
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Publication of WO2016037396A1 publication Critical patent/WO2016037396A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
  • Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles.
  • devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced.
  • silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device.
  • the operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.
  • the invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect.
  • the structure includes:
  • the substrate structure being an SOI substrate
  • first and second fins being located above the substrate structure and parallel to each other;
  • a gate stack covering the substrate structure and portions of the first and second fins wall;
  • the source region being located in an area where the first fin is not covered by the gate stack;
  • drain region being located in a region where the second fin is not covered by the gate stack
  • a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.
  • first and second fins have the same height, thickness and width.
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the present invention also provides a U-shaped FinFET device manufacturing method, including:
  • the substrate structure being an SOI substrate
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • step b the method of forming the first fin and the second fin is:
  • the method of forming the first fin and the second fin is an anisotropic etching.
  • first fin and the second fin have the same height, thickness and width.
  • the distance between the first fin and the second fin is 5 to 50 nm.
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the method of forming the gate stack is atomic layer deposition.
  • the method of removing a part of the gate stack is anisotropic selective etching.
  • the method of forming the source and drain regions is oblique ion implantation.
  • the method of forming the source and drain regions is side scatter.
  • the silicon of the surface not covered by the sidewall spacer is epitaxially grown to form a source-drain epitaxial region.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect.
  • the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current.
  • the device since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Has a smaller DIBL.
  • the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts.
  • the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages.
  • the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • FIG. 1 to 10 are schematic cross-sectional views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention
  • Figure 11 is a schematic cross-sectional view showing the formation of a U-shaped FinFET device in accordance with the method of Embodiment 2 of the present invention.
  • the present invention provides a FinFET structure including: a substrate structure, the substrate structure is an SOI substrate; a first fin and a second fin, the first and second fins Located above the substrate structure, parallel to each other; a gate stack covering the substrate structure and sidewalls of a portion of the first and second fins; a source region, the source region being located a region where the first fin is not covered by the gate stack; a drain region located in a region where the second fin is not covered by the gate stack; a sidewall, the sidewall is located at The first and second fins are on both sides for isolating the source region, the drain region and the gate stack.
  • the SOI substrate includes a top substrate 150, a buried oxide layer 101, and a support substrate 100.
  • first and second fins have the same height, thickness and width.
  • the gate stack 300 includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect.
  • the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current.
  • the device since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Have Smaller DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts.
  • the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages.
  • the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • the semiconductor material of the substrate structure and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
  • a support substrate 100 in the present invention is illustrated.
  • the material of the support substrate 100 is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like.
  • the material of the support substrate 100 used is silicon, and the thickness thereof is 100-500 nm.
  • a buried oxide layer is formed over the support substrate 100.
  • the buried oxide layer 101 may be formed by chemical vapor deposition or atomic layer deposition, and the buried oxide layer has a thickness of 20 to 50 nm.
  • a top substrate 150 is formed over the buried oxide layer 101, that is, an effective substrate region when the device is in operation; in order to ensure film quality, preferably, the top substrate 150 is formed by atomic layer deposition. Its thickness is 20 to 50 nm.
  • the gate structure is divided into two parts, except for the regions covered by the gate stack on the first and second fins, respectively, and the top substrate between the fins.
  • the area covered by gate stack 300 on 150 is also part of the device channel. Since the thickness of the substrate structure is much larger than the thickness of the fin, the control ability of the gate to the channel region on the substrate structure is relatively weak, which imposes certain constraints on the operating current of the device. In order to improve this situation, we have improved the invention by combining SOI technology, using SOI substrate instead of bulk silicon substrate, so that the top layer silicon 150 of the substrate region has a very thin thickness, and the medium of components in the integrated circuit can be further realized.
  • the SOI substrate in the present invention can further reduce leakage current and enhance the gate control capability of the device, thereby greatly improving the device. performance.
  • a channel material layer 110 and a source/drain material layer 120 are epitaxially grown on the top substrate 150 in this order.
  • the channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device.
  • the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used.
  • the doping impurities are five elements such as phosphorus and arsenic.
  • the channel region formed in the subsequent process has a doping concentration of 1e15 cm -3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device.
  • the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic;
  • the doping type of the channel material layer is P-type,
  • the doping impurity used is a group III element such as boron.
  • the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm -3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the structure after forming the source/drain material layer 120 is as shown in FIG. 4, and the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the gate stack height after device formation.
  • the thickness of the source/drain material layer 120 is H1.
  • the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching
  • the method can be dry etching or dry/wet etching.
  • the height after the first fin 210 and the second fin 220 are etched is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench
  • the thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process
  • the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.
  • a gate stack 300 is formed over the top substrate 150 and the first fins 210 and the second fins 220, which is the same as the existing FinFET process, and the gate stack 300 includes interfaces in sequence.
  • Layer 310, high K dielectric layer 320, metal gate work function adjustment layer 330, and polysilicon 340 are formed over the top substrate 150 and the first fins 210 and the second fins 220, which is the same as the existing FinFET process, and the gate stack 300 includes interfaces in sequence.
  • Layer 310, high K dielectric layer 320, metal gate work function adjustment layer 330, and polysilicon 340 are examples of the gate stack 300.
  • the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties.
  • the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO Or a combination thereof
  • the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG.
  • the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm.
  • the device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 7 .
  • polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330.
  • a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry. Mechanical polishing (CMP), the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330; Next, the polysilicon layer is etched using anisotropic selective etching to have its surface flush with the bottom of the source/drain material layer 120, as shown in FIG.
  • CMP Mechanical polishing
  • the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove a portion thereof above the polysilicon layer 340 to expose a portion of the fin, such as Figure 9 shows.
  • the source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.
  • a sidewall spacer 230 is formed on the exposed portion of the fin sidewall to separate the gate stack from the source and drain regions.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • the sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm, as shown in FIG.
  • silicon in a region where the surface of the fin is not covered by the sidewall spacer 230 is epitaxially grown to form a source drain.
  • the epitaxial region 240 that is, raised-SD, is as shown in FIG. In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.
  • a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne une structure de FinFET et son procédé de fabrication, comprenant : une structure de substrat qui est un substrat en SOI ; une première ailette (210) et seconde ailette (220) parallèles situées au-dessus de la structure de substrat ; un empilement d'électrode de grille (300) recouvrant la structure de substrat et la paroi latérale d'une partie de la première ailette (210) et de la seconde ailette (220) ; une région de source (410) située dans la région de la première ailette (210) non recouverte par l'empilement d'électrode de grille ; une région de drain (420) située dans la région de la seconde ailette (220) non recouverte par l'empilement d'électrode de grille ; une paroi latérale (230) située des deux côtés de la première ailette (210) et de la seconde ailette (220) et au-dessus de l'empilement d'électrode de grille (300) de façon à isoler la région de source, la région de drain et l'empilement d'électrode de grille ; et une région de canal de structure de substrat située dans une région de la structure de substrat adjacente à une surface supérieure. L'invention fournit une nouvelle structure de dispositif sur la base d'un traitement de FinFET existant, ce qui permet d'exempter la longueur de grille du dispositif de limites de taille d'encombrement et de résoudre efficacement un problème provoqué par un effet de canal court.
PCT/CN2014/088596 2014-09-10 2014-10-15 Structure de finfet et son procédé de fabrication WO2016037396A1 (fr)

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CN201410459571.1A CN105405886B (zh) 2014-09-10 2014-09-10 一种FinFET结构及其制造方法

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US10103147B1 (en) 2017-05-01 2018-10-16 International Business Machines Corporation Vertical transport transistors with equal gate stack thicknesses
CN111403386A (zh) * 2020-03-24 2020-07-10 上海华力集成电路制造有限公司 一种结合鳍式电晶管与soi电晶管的器件结构及制造方法

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US20130109152A1 (en) * 2010-02-09 2013-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making lower parasitic capacitance finfet
JP2013162076A (ja) * 2012-02-08 2013-08-19 Toshiba Corp 半導体装置およびその製造方法

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Publication number Priority date Publication date Assignee Title
US20130109152A1 (en) * 2010-02-09 2013-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making lower parasitic capacitance finfet
CN102270661A (zh) * 2010-06-02 2011-12-07 南亚科技股份有限公司 单边栅极鳍状场效晶体管及其制造方法
CN102651313A (zh) * 2011-02-25 2012-08-29 中国科学院微电子研究所 Pmos器件叠层结构的制备和栅功函数调节方法
JP2013162076A (ja) * 2012-02-08 2013-08-19 Toshiba Corp 半導体装置およびその製造方法

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CN105405886A (zh) 2016-03-16

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