WO2016037395A1 - Structure finfet et son procédé de fabrication - Google Patents

Structure finfet et son procédé de fabrication Download PDF

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Publication number
WO2016037395A1
WO2016037395A1 PCT/CN2014/088595 CN2014088595W WO2016037395A1 WO 2016037395 A1 WO2016037395 A1 WO 2016037395A1 CN 2014088595 W CN2014088595 W CN 2014088595W WO 2016037395 A1 WO2016037395 A1 WO 2016037395A1
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WO
WIPO (PCT)
Prior art keywords
fin
substrate
region
source
gate stack
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PCT/CN2014/088595
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English (en)
Chinese (zh)
Inventor
尹海洲
刘云飞
李睿
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中国科学院微电子研究所
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Publication of WO2016037395A1 publication Critical patent/WO2016037395A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
  • Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles.
  • devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced.
  • silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device.
  • the operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.
  • the invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect.
  • the structure includes:
  • first and second fins being located above the substrate and parallel to each other;
  • a gate stack covering sidewalls of the substrate and portions of the first and second fins
  • the source region being located in an area where the first fin is not covered by the gate stack;
  • drain region being located in a region where the second fin is not covered by the gate stack
  • the side wall is located at two sides of the first and second fins, for isolating the source region, the drain region and the gate stack;
  • first and second fins have the same height, thickness and width.
  • the doping type and the doping concentration of the substrate channel region are the same as the source and drain regions.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the present invention also provides a U-shaped FinFET device manufacturing method, including:
  • the doping type and doping concentration of the substrate channel region (150) are the same as the source and drain regions.
  • step b the method of forming the first fin (210) and the second fin (220) is:
  • the method of forming the first fin (210) and the second fin (220) is an anisotropic etch.
  • first fin (210) and the second fin (220) have the same height, thickness and width.
  • the distance between the first fin (210) and the second fin (220) is 5 to 50 nm.
  • the doping type and doping concentration of the substrate channel region (150) are the same as the source and drain regions.
  • the height of the gate stack (300) is the first and second fins (210, 220) The height is 1/2 to 3/4.
  • the method of forming the gate stack is atomic layer deposition.
  • the method of removing a part of the gate stack is anisotropic selective etching.
  • the method of forming the source and drain regions is oblique ion implantation.
  • the method of forming the source and drain regions is side scatter.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect.
  • the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current. .
  • the device since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device, so that the device has Smaller DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating fabrication of source-drain contacts.
  • the substrate channel region of the present invention is heavily doped, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • FIG. 1 to 10 are schematic cross-sectional views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention
  • Figure 11 shows the final structure of a device formed in accordance with the method of embodiment 2 of the present invention.
  • the present invention provides a FinFET structure comprising: a substrate; a first fin and a second fin, the first and second fins being located above the substrate, parallel to each other; a gate stack, the a gate stack covering sidewalls of the substrate and portions of the first and second fins; a source region, the source region being located in a region where the first fin is not covered by the gate stack; a drain region, The drain region is located in a region where the second fin is not covered by the gate stack; the sidewall is located on both sides of the first and second fins for isolating the source region and the drain region And a gate stack; a substrate channel region, the substrate channel region being located in a region of the substrate near the upper surface.
  • first and second fins have the same height, thickness and width.
  • the doping type and the doping concentration of the substrate channel region are the same as the source and drain regions.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect.
  • the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current. .
  • the device since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device, so that the device has Smaller DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating fabrication of source-drain contacts.
  • the substrate channel region of the present invention is heavily doped, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • the semiconductor material of the substrate and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
  • the first substrate material is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like.
  • the substrate used is a silicon substrate.
  • a mask layer 101 is then deposited on the surface of the substrate as a substrate protection film in the subsequent ion implantation process, and the material of the mask layer 101 may be silicon nitride and/or silicon oxide;
  • ion implantation is performed on the substrate 100 to form a channel doping region 150.
  • the implanted impurity type is the same as the source and drain regions, and a certain doping profile is formed in the depth of the substrate 100 at a depth of 5 to 10 nm; the ion implantation process is one of the basic processes in the art, and the specific implantation process will not be described herein.
  • the device structure after forming the channel doping region 150 is as shown in FIG.
  • the substrate doping region 150 may be formed by epitaxial growth on the substrate by in-situ doping; the in-situ doping method is a common technical means in the art, and the specific process steps are here. No longer.
  • a channel material layer 110 and a source/drain material layer 120 are epitaxially grown on the substrate 100 in this order.
  • the channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device.
  • the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used.
  • the doping impurities are five elements such as phosphorus and arsenic.
  • the channel region formed in the subsequent process has a doping concentration of 1e15 cm-3, and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy,
  • the process steps of the body are the same as those of the prior art, and will not be described here.
  • the source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device.
  • the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic;
  • the doping type of the channel material layer is P-type,
  • the doping impurity used is a group III element such as boron.
  • the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm -3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the structure after forming the source/drain material layer 120 is as shown in FIG. 4, and the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the gate stack height after device formation.
  • the thickness of the source/drain material layer 120 is H1.
  • the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching
  • the method can be dry etching or dry/wet etching.
  • the height after the first fin 210 and the second fin 220 are etched is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench
  • the thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process
  • the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.
  • a gate stack 300 is formed over the substrate 100 and the first fin 210 and the second fin 220, which is the same as the existing FinFET process.
  • the pole stack 300 includes an interface layer 310, a high K dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340 in this order.
  • the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties.
  • the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO Or a combination thereof
  • the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG.
  • the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm.
  • the device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 7 .
  • the above-described process for forming a gate stack is formed by atomic layer deposition.
  • polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330.
  • a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry. Mechanical polishing (CMP), the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330; Next, the polysilicon layer is directionally etched using anisotropic selective etching to have its surface flush with the source/drain material layer 120, as shown in FIG.
  • CMP Mechanical polishing
  • the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove the portion above the polysilicon layer 340 to expose the fins. 9 is shown.
  • the source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.
  • sidewalls 230 are formed on the exposed portions of the fin sidewalls for separating the gate stack from the source and drain regions.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • the sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.
  • the silicon of the surface not covered by the sidewall spacer 230 is epitaxially grown to form a source/drain epitaxial region 240, that is, raised-SD, as shown in FIG. .
  • In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.
  • a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.
  • the gate structure is divided into two parts, except for the regions covered by the gate stack on the first and second fins, respectively, between the fins and the substrate 100.
  • the area overlying the gate stack 300 is also part of the device channel. Due to substrate thickness It is much larger than the thickness of the fin, so the control ability of the gate to the channel region on the substrate is relatively weak, which imposes certain constraints on the operating current of the device. In order to improve this situation, we do the same type of doping in the channel region on the substrate as the source and drain regions, ensuring that the channel at the substrate is in an open state regardless of the range of the gate voltage, effectively making up The disadvantage of weaker gate control of the substrate increases the on-state current of the device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne une structure de transistor à effet de champ à ailettes (FinFET) et son procédé de fabrication, comprenant : un substrat ; une première ailette et une seconde ailette parallèles situées au-dessus du substrat ; un empilement d'électrode de grille recouvrant le substrat et la paroi latérale d'une partie de la première ailette et de la seconde ailette ; une zone de source située dans la zone de la première ailette qui n'est pas recouverte par l'empilement d'électrode de grille ; une zone de drain située dans la zone de la seconde ailette qui n'est pas recouverte par l'empilement d'électrode de grille ; une paroi latérale située au niveau de deux côtés de la première ailette et de la seconde ailette et au-dessus de l'empilement d'électrode de grille pour isoler la zone de source, la zone de drain et l'empilement d'électrode de grille ; et une zone de canal de substrat située dans une zone du substrat adjacente à une surface supérieure. Une nouvelle structure de dispositif obtenue sur la base d'un processus FinFET existant permet d'affranchir la longueur de grille du dispositif d'une limite de taille d'empreinte, ce qui permet de résoudre ainsi efficacement un problème causé par un effet de canal court.
PCT/CN2014/088595 2014-09-10 2014-10-15 Structure finfet et son procédé de fabrication WO2016037395A1 (fr)

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CN201410459357.6 2014-09-10
CN201410459357.6A CN105470253B (zh) 2014-09-10 2014-09-10 一种FinFET结构及其制造方法

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060130322A (ko) * 2005-06-14 2006-12-19 주식회사 하이닉스반도체 수직 채널을 갖는 전계 효과 트랜지스터 및 그 제조방법
US20090039420A1 (en) * 2007-08-08 2009-02-12 Trivedi Vishal P Finfet memory cell having a floating gate and method therefor
CN101819975A (zh) * 2010-04-28 2010-09-01 复旦大学 垂直沟道双栅隧穿晶体管及其制备方法
CN102420232A (zh) * 2010-09-28 2012-04-18 中国科学院微电子研究所 一种闪存器件及其形成方法
CN103956338A (zh) * 2014-04-29 2014-07-30 复旦大学 一种集成u形沟道器件和鳍形沟道器件的集成电路及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060130322A (ko) * 2005-06-14 2006-12-19 주식회사 하이닉스반도체 수직 채널을 갖는 전계 효과 트랜지스터 및 그 제조방법
US20090039420A1 (en) * 2007-08-08 2009-02-12 Trivedi Vishal P Finfet memory cell having a floating gate and method therefor
CN101819975A (zh) * 2010-04-28 2010-09-01 复旦大学 垂直沟道双栅隧穿晶体管及其制备方法
CN102420232A (zh) * 2010-09-28 2012-04-18 中国科学院微电子研究所 一种闪存器件及其形成方法
CN103956338A (zh) * 2014-04-29 2014-07-30 复旦大学 一种集成u形沟道器件和鳍形沟道器件的集成电路及其制备方法

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CN105470253B (zh) 2018-08-10
CN105470253A (zh) 2016-04-06

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