WO2016037396A1

WO2016037396A1 - Finfet structure and manufacturing method thereof

Info

Publication number: WO2016037396A1
Application number: PCT/CN2014/088596
Authority: WO
Inventors: 尹海洲; 刘云飞; 李睿
Original assignee: 中国科学院微电子研究所
Priority date: 2014-09-10
Filing date: 2014-10-15
Publication date: 2016-03-17
Also published as: CN105405886B; CN105405886A

Abstract

A FinFET structure and manufacturing method thereof, comprising: a substrate structure being an SOI substrate; a parallel first fin (210) and second fin (220) located above the substrate structure; a gate electrode stack (300) covering the substrate structure and the side wall of a part of the first fin (210) and the second fin (220); a source region (410) located in the region of the first fins (210) not covered by the gate electrode stack; a drain region (420) located in the region of the second fin (220) not covered by the gate electrode stack; a side wall (230) located at two sides of the first fin (210) and the second fin (220) and above the gate electrode stack (300) to isolate the source region, the drain region and the gate electrode stack; and a substrate structure channel region located in a region of the substrate structure adjacent to an upper surface. A new device structure is provided on the basis of an existing FinFET process, thus enabling the gate length of the device to be free of footprint size limitations, and effectively solving a problem caused by a short channel effect.

Description

FinFET structure and manufacturing method thereof

The present application claims the benefit of priority to the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the disclosure.

Technical field

The present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.

technical background

Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles. At present, with the development of integrated circuit technology and technology, devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced. However, since 2011, silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device. The operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.

Summary of the invention

The invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect. Specifically, the structure includes:

a substrate structure, the substrate structure being an SOI substrate;

a first fin and a second fin, the first and second fins being located above the substrate structure and parallel to each other;

a gate stack covering the substrate structure and portions of the first and second fins wall;

a source region, the source region being located in an area where the first fin is not covered by the gate stack;

a drain region, the drain region being located in a region where the second fin is not covered by the gate stack;

a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.

Wherein the first and second fins have the same height, thickness and width.

The gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.

The height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.

Correspondingly, the present invention also provides a U-shaped FinFET device manufacturing method, including:

Providing a substrate structure, the substrate structure being an SOI substrate;

b. forming a first fin and a second fin on the substrate structure;

c. forming a gate stack over the substrate structure, the first fin and the second fin;

d. removing the gate stack above and a portion of the sidewalls of the first fin and the second fin, the exposed portions of the first and second fins forming source and drain regions;

e. forming sidewalls on both sides of the first fin and the second fin that are not covered by the gate stack.

Wherein, in step b, the method of forming the first fin and the second fin is:

B1) sequentially forming a channel material layer and a source/drain material layer on the substrate structure;

B2) etching the channel material layer and the source/drain material layer to form a first fin and a second fin.

Wherein, the method of forming the first fin and the second fin is an anisotropic etching.

Wherein the first fin and the second fin have the same height, thickness and width.

The distance between the first fin and the second fin is 5 to 50 nm.

Wherein, the method of forming the gate stack is atomic layer deposition.

Among them, the method of removing a part of the gate stack is anisotropic selective etching.

Wherein, the method of forming the source and drain regions is oblique ion implantation.

Wherein, the method of forming the source and drain regions is side scatter.

Wherein, the silicon of the surface not covered by the sidewall spacer is epitaxially grown to form a source-drain epitaxial region.

The present invention proposes a new U-shaped device structure based on the existing FinFET process. Compared with the prior art, the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. First, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current. Secondly, since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Has a smaller DIBL. Again, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts. At the same time, the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages. Finally, since the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.

DRAWINGS

1 to 10 are schematic cross-sectional views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention;

Figure 11 is a schematic cross-sectional view showing the formation of a U-shaped FinFET device in accordance with the method of Embodiment 2 of the present invention.

detailed description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in detail below.

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.

As shown in FIG. 10, the present invention provides a FinFET structure including: a substrate structure, the substrate structure is an SOI substrate; a first fin and a second fin, the first and second fins Located above the substrate structure, parallel to each other; a gate stack covering the substrate structure and sidewalls of a portion of the first and second fins; a source region, the source region being located a region where the first fin is not covered by the gate stack; a drain region located in a region where the second fin is not covered by the gate stack; a sidewall, the sidewall is located at The first and second fins are on both sides for isolating the source region, the drain region and the gate stack.

The SOI substrate includes a top substrate 150, a buried oxide layer 101, and a support substrate 100.

Wherein the first and second fins have the same height, thickness and width.

The gate stack 300 includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.

The present invention proposes a new U-shaped device structure based on the existing FinFET process. Compared with the prior art, the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. First, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current. Secondly, since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Have Smaller DIBL. Again, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts. At the same time, the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages. Finally, since the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.

The present invention will be described in more detail below with reference to the accompanying drawings. Throughout the drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.

It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "above" or "above" another layer, it may mean that it is directly on another layer or another region, or Other layers or regions are also included between it and another layer. Also, if the device is flipped, the layer, one area will be located on the other layer, and the other area "below" or "below".

In the case of a description directly above another layer or another region, this document will use the expression "directly above" or "adjacent to and adjacent to".

Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. For example, the semiconductor material of the substrate structure and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.

First, the embodiment 1 of the present invention will be described in detail with reference to the accompanying drawings.

Referring to Figure 1, a support substrate 100 in the present invention is illustrated. The material of the support substrate 100 is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like. Preferably, in the embodiment, the material of the support substrate 100 used is silicon, and the thickness thereof is 100-500 nm. Next, as shown in Figure 2. A buried oxide layer is formed over the support substrate 100. Specifically, the buried oxide layer 101 may be formed by chemical vapor deposition or atomic layer deposition, and the buried oxide layer has a thickness of 20 to 50 nm. Finally, a top substrate 150 is formed over the buried oxide layer 101, that is, an effective substrate region when the device is in operation; in order to ensure film quality, preferably, the top substrate 150 is formed by atomic layer deposition. Its thickness is 20 to 50 nm.

For the U-shaped FinFET structure of the present invention, the gate structure is divided into two parts, except for the regions covered by the gate stack on the first and second fins, respectively, and the top substrate between the fins. The area covered by gate stack 300 on 150 is also part of the device channel. Since the thickness of the substrate structure is much larger than the thickness of the fin, the control ability of the gate to the channel region on the substrate structure is relatively weak, which imposes certain constraints on the operating current of the device. In order to improve this situation, we have improved the invention by combining SOI technology, using SOI substrate instead of bulk silicon substrate, so that the top layer silicon 150 of the substrate region has a very thin thickness, and the medium of components in the integrated circuit can be further realized. Isolation completely eliminates the parasitic latch-up effect in bulk silicon CMOS circuits. At the same time, compared with bulk silicon devices, the SOI substrate in the present invention can further reduce leakage current and enhance the gate control capability of the device, thereby greatly improving the device. performance.

Next, as shown in FIG. 4, a channel material layer 110 and a source/drain material layer 120 are epitaxially grown on the top substrate 150 in this order. The channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device. For the N-type device, the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used. The doping impurities are five elements such as phosphorus and arsenic. In this embodiment, the channel region formed in the subsequent process has a doping concentration of 1e15 cm ^-3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.

The source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device. For the N-type device, the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic; for the P-type device, the doping type of the channel material layer is P-type, The doping impurity used is a group III element such as boron. In this embodiment, the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm ^-3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.

The structure after forming the source/drain material layer 120 is as shown in FIG. 4, and the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the gate stack height after device formation. The thickness of the source/drain material layer 120 is H1.

Next, the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching The method can be dry etching or dry/wet etching. As shown in FIG. 5, the height after the first fin 210 and the second fin 220 are etched is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench The thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process, and the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.

Next, a gate stack 300 is formed over the top substrate 150 and the first fins 210 and the second fins 220, which is the same as the existing FinFET process, and the gate stack 300 includes interfaces in sequence. Layer 310, high K dielectric layer 320, metal gate work function adjustment layer 330, and polysilicon 340.

Wherein, the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties. 0.5 to 1 nm; the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al ₂ O ₃ , La ₂ O ₃ , ZrO ₂ , LaAlO Or a combination thereof, the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG. 6; the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm. The device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 7 .

In order to provide the gate stack 300 with good step coverage characteristics, a film of excellent quality is obtained, The above processes for forming the gate stack are all formed by atomic layer deposition.

Next, polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330. First, a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry. Mechanical polishing (CMP), the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330; Next, the polysilicon layer is etched using anisotropic selective etching to have its surface flush with the bottom of the source/drain material layer 120, as shown in FIG.

Next, the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove a portion thereof above the polysilicon layer 340 to expose a portion of the fin, such as Figure 9 shows. The source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.

Next, a sidewall spacer 230 is formed on the exposed portion of the fin sidewall to separate the gate stack from the source and drain regions. Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials. The side wall 230 may have a multi-layered structure. The sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm, as shown in FIG.

In the second embodiment of the present invention, as shown in FIG. 11 , optionally, after the sidewall spacer 230 is formed, silicon in a region where the surface of the fin is not covered by the sidewall spacer 230 is epitaxially grown to form a source drain. The epitaxial region 240, that is, raised-SD, is as shown in FIG. In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.

Next, as in the prior art, a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.

While the invention has been described with respect to the preferred embodiments and the embodiments of the present invention, it is understood that various changes, substitutions and modifications may be made to the embodiments without departing from the spirit and scope of the invention. For other examples, those of ordinary skill in the art will readily appreciate that the order of process steps may vary while remaining within the scope of the invention.

Further, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition of matter, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be readily understood by those skilled in the art that the processes, mechanisms, manufactures, compositions, means, methods, or steps that are presently present or will be developed in the The corresponding embodiments described have substantially the same function or substantially the same results, which can be applied in accordance with the invention. Therefore, the appended claims are intended to cover such modifications, such structures, structures,

Claims

A U-shaped FinFET device structure comprising:

a substrate structure, the substrate structure being an SOI substrate;

a first fin (210) and a second fin (220), the first fin (210) and the second fin (220) being located above the substrate structure, parallel to each other;

a gate stack (300), the gate stack covering sidewalls of the substrate structure and portions of the first fins (210) and the second fins (220);

a source region (410), the source region being located in a region where the first fin (210) is not covered by the gate stack;

a drain region (420), the drain region being located in a region where the second fin (220) is not covered by the gate stack;

a side wall (230), the side wall (230) is located on both sides of the first fin (210) and the second fin (220), above the gate stack (300), for isolating the source region and the drain Zone and gate stack.
The FinFET device structure of claim 1 wherein the first fins (210) and the second fins (220) have the same height, thickness, and width.
The FinFET device structure of claim 1 wherein the distance between the first fin (210) and the second fin (220) is between 5 and 50 nm.
The FinFET device structure according to claim 1, wherein the height of the gate stack (300) is 1/2 to 3/4 of the height of the first and second fins (210, 220). .
The FinFET device structure according to claim 1, wherein the gate stack (300) comprises: an interface layer (310), a high-k dielectric layer (320), a metal gate work function adjustment layer (330), and Polysilicon (340).
A U-shaped FinFET device manufacturing method includes:

Providing a substrate structure, the substrate structure being an SOI substrate;

b. forming a first fin (210) and a second fin (220) on the substrate structure;

c. forming a gate stack over the substrate structure, the first fin (210) and the second fin (220);

d. removing the gate stack above and a portion of the sidewalls of the first fin (210) and the second fin (220), the exposed portions of the first and second fins forming source and drain regions;

e. Forming sidewalls (230) on both sides of the first fin (210) and the second fin (220) that are not covered by the gate stack.
The manufacturing method according to claim 6, wherein the gate stack (300) comprises: an interface layer (310), a high-k dielectric layer (320), a metal gate work function adjusting layer (330), and polysilicon. (340).
The manufacturing method according to claim 6, wherein in the step b, the method of forming the first fin (210) and the second fin (220) is:

B1) sequentially forming a channel material layer (110) and a source/drain material layer (120) on the substrate structure;

B2) etching the channel material layer (110) and the source/drain material layer (120) to form a first fin (210) and a second fin (220).
The manufacturing method according to claim 6, wherein the method of forming the first fins (210) and the second fins (220) is anisotropic etching.
The manufacturing method according to claim 6, wherein the first fins (210) and the second fins (220) have the same height, thickness, and width.
The manufacturing method according to claim 6, wherein a distance between the first fin (210) and the second fin (220) is 5 to 50 nm.
The manufacturing method according to claim 6, wherein the gate stack (300) comprises: an interface layer (310), a high-k dielectric layer (320), a metal gate work function adjusting layer (330), and polysilicon. (340).
The manufacturing method according to claim 6, wherein the height of the gate stack (300) is 1/2 to 3/4 of the height of the first and second fins (210, 220).
The method of manufacturing according to claim 6, wherein the method of forming the gate stack is atomic layer deposition.
The method of manufacturing according to claim 6, wherein the method of removing a portion of the gate stack is anisotropic selective etching.
The manufacturing method according to claim 6, wherein the method of forming the source/drain regions is oblique ion implantation.
The manufacturing method according to claim 6, wherein the method of forming the source and drain regions is side scatter.
The manufacturing method according to claim 6, wherein the surface of the surface not covered by the sidewall spacer is epitaxially grown to form a source/drain epitaxial region.