WO2016037396A1 - Finfet structure and manufacturing method thereof - Google Patents
Finfet structure and manufacturing method thereof Download PDFInfo
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- WO2016037396A1 WO2016037396A1 PCT/CN2014/088596 CN2014088596W WO2016037396A1 WO 2016037396 A1 WO2016037396 A1 WO 2016037396A1 CN 2014088596 W CN2014088596 W CN 2014088596W WO 2016037396 A1 WO2016037396 A1 WO 2016037396A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 22
- 230000000694 effects Effects 0.000 abstract description 9
- 230000008901 benefit Effects 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N ZrO Inorganic materials [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
- Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles.
- devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced.
- silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device.
- the operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.
- the invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect.
- the structure includes:
- the substrate structure being an SOI substrate
- first and second fins being located above the substrate structure and parallel to each other;
- a gate stack covering the substrate structure and portions of the first and second fins wall;
- the source region being located in an area where the first fin is not covered by the gate stack;
- drain region being located in a region where the second fin is not covered by the gate stack
- a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.
- first and second fins have the same height, thickness and width.
- the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
- the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
- the present invention also provides a U-shaped FinFET device manufacturing method, including:
- the substrate structure being an SOI substrate
- the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
- step b the method of forming the first fin and the second fin is:
- the method of forming the first fin and the second fin is an anisotropic etching.
- first fin and the second fin have the same height, thickness and width.
- the distance between the first fin and the second fin is 5 to 50 nm.
- the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
- the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
- the method of forming the gate stack is atomic layer deposition.
- the method of removing a part of the gate stack is anisotropic selective etching.
- the method of forming the source and drain regions is oblique ion implantation.
- the method of forming the source and drain regions is side scatter.
- the silicon of the surface not covered by the sidewall spacer is epitaxially grown to form a source-drain epitaxial region.
- the present invention proposes a new U-shaped device structure based on the existing FinFET process.
- the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect.
- the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current.
- the device since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Has a smaller DIBL.
- the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts.
- the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages.
- the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current.
- the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
- FIG. 1 to 10 are schematic cross-sectional views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention
- Figure 11 is a schematic cross-sectional view showing the formation of a U-shaped FinFET device in accordance with the method of Embodiment 2 of the present invention.
- the present invention provides a FinFET structure including: a substrate structure, the substrate structure is an SOI substrate; a first fin and a second fin, the first and second fins Located above the substrate structure, parallel to each other; a gate stack covering the substrate structure and sidewalls of a portion of the first and second fins; a source region, the source region being located a region where the first fin is not covered by the gate stack; a drain region located in a region where the second fin is not covered by the gate stack; a sidewall, the sidewall is located at The first and second fins are on both sides for isolating the source region, the drain region and the gate stack.
- the SOI substrate includes a top substrate 150, a buried oxide layer 101, and a support substrate 100.
- first and second fins have the same height, thickness and width.
- the gate stack 300 includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
- the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
- the present invention proposes a new U-shaped device structure based on the existing FinFET process.
- the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect.
- the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current.
- the device since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Have Smaller DIBL.
- the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts.
- the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages.
- the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current.
- the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
- the semiconductor material of the substrate structure and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
- a support substrate 100 in the present invention is illustrated.
- the material of the support substrate 100 is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like.
- the material of the support substrate 100 used is silicon, and the thickness thereof is 100-500 nm.
- a buried oxide layer is formed over the support substrate 100.
- the buried oxide layer 101 may be formed by chemical vapor deposition or atomic layer deposition, and the buried oxide layer has a thickness of 20 to 50 nm.
- a top substrate 150 is formed over the buried oxide layer 101, that is, an effective substrate region when the device is in operation; in order to ensure film quality, preferably, the top substrate 150 is formed by atomic layer deposition. Its thickness is 20 to 50 nm.
- the gate structure is divided into two parts, except for the regions covered by the gate stack on the first and second fins, respectively, and the top substrate between the fins.
- the area covered by gate stack 300 on 150 is also part of the device channel. Since the thickness of the substrate structure is much larger than the thickness of the fin, the control ability of the gate to the channel region on the substrate structure is relatively weak, which imposes certain constraints on the operating current of the device. In order to improve this situation, we have improved the invention by combining SOI technology, using SOI substrate instead of bulk silicon substrate, so that the top layer silicon 150 of the substrate region has a very thin thickness, and the medium of components in the integrated circuit can be further realized.
- the SOI substrate in the present invention can further reduce leakage current and enhance the gate control capability of the device, thereby greatly improving the device. performance.
- a channel material layer 110 and a source/drain material layer 120 are epitaxially grown on the top substrate 150 in this order.
- the channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device.
- the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used.
- the doping impurities are five elements such as phosphorus and arsenic.
- the channel region formed in the subsequent process has a doping concentration of 1e15 cm -3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
- the source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device.
- the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic;
- the doping type of the channel material layer is P-type,
- the doping impurity used is a group III element such as boron.
- the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm -3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
- the structure after forming the source/drain material layer 120 is as shown in FIG. 4, and the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the gate stack height after device formation.
- the thickness of the source/drain material layer 120 is H1.
- the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching
- the method can be dry etching or dry/wet etching.
- the height after the first fin 210 and the second fin 220 are etched is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench
- the thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process
- the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.
- a gate stack 300 is formed over the top substrate 150 and the first fins 210 and the second fins 220, which is the same as the existing FinFET process, and the gate stack 300 includes interfaces in sequence.
- Layer 310, high K dielectric layer 320, metal gate work function adjustment layer 330, and polysilicon 340 are formed over the top substrate 150 and the first fins 210 and the second fins 220, which is the same as the existing FinFET process, and the gate stack 300 includes interfaces in sequence.
- Layer 310, high K dielectric layer 320, metal gate work function adjustment layer 330, and polysilicon 340 are examples of the gate stack 300.
- the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties.
- the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO Or a combination thereof
- the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG.
- the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm.
- the device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 7 .
- polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330.
- a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry. Mechanical polishing (CMP), the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330; Next, the polysilicon layer is etched using anisotropic selective etching to have its surface flush with the bottom of the source/drain material layer 120, as shown in FIG.
- CMP Mechanical polishing
- the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove a portion thereof above the polysilicon layer 340 to expose a portion of the fin, such as Figure 9 shows.
- the source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.
- a sidewall spacer 230 is formed on the exposed portion of the fin sidewall to separate the gate stack from the source and drain regions.
- Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
- the side wall 230 may have a multi-layered structure.
- the sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm, as shown in FIG.
- silicon in a region where the surface of the fin is not covered by the sidewall spacer 230 is epitaxially grown to form a source drain.
- the epitaxial region 240 that is, raised-SD, is as shown in FIG. In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.
- a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.
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Abstract
A FinFET structure and manufacturing method thereof, comprising: a substrate structure being an SOI substrate; a parallel first fin (210) and second fin (220) located above the substrate structure; a gate electrode stack (300) covering the substrate structure and the side wall of a part of the first fin (210) and the second fin (220); a source region (410) located in the region of the first fins (210) not covered by the gate electrode stack; a drain region (420) located in the region of the second fin (220) not covered by the gate electrode stack; a side wall (230) located at two sides of the first fin (210) and the second fin (220) and above the gate electrode stack (300) to isolate the source region, the drain region and the gate electrode stack; and a substrate structure channel region located in a region of the substrate structure adjacent to an upper surface. A new device structure is provided on the basis of an existing FinFET process, thus enabling the gate length of the device to be free of footprint size limitations, and effectively solving a problem caused by a short channel effect.
Description
本申请要求了2014年9月10日提交的、申请号为201410459571.1、发明名称为“一种FinFET结构及其制造方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。The present application claims the benefit of priority to the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the disclosure.
本发明涉及一种半导体器件制造方法,具体地,涉及一种FinFET制造方法。The present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
摩尔定律指出:集成电路上可容纳的晶体管数目每隔18个月增加一倍,性能也同时提升一倍。目前,随着集成电路工艺和技术的发展,先后出现了二极管、MOSFET、FinFET等器件,节点尺寸不断减小。然而,2011年以来,硅晶体管已接近了原子等级,达到了物理极限,由于这种物质的自然属性,除了短沟道效应以外,器件的量子效应也对器件的性能产生了很大的影响,硅晶体管的运行速度和性能难有突破性发展。因此,如何在在无法减小特征尺寸的情况下,大幅度的提升硅晶体管的性能已成为当前亟待解决的技术难点。Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles. At present, with the development of integrated circuit technology and technology, devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced. However, since 2011, silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device. The operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.
发明内容Summary of the invention
本发明提供了一种U型FinFET结构及其制造方法,在现有FinFET工艺的基础上提出了一种新的器件结构,使器件的栅长不受footprint尺寸限制,有效地解决了短沟道效应所带来的问题。具体的,该结构包括:The invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect. Specifically, the structure includes:
衬底结构,所述衬底结构为SOI衬底;a substrate structure, the substrate structure being an SOI substrate;
第一鳍片和第二鳍片,所述第一、第二鳍片位于所述衬底结构上方,彼此平行;a first fin and a second fin, the first and second fins being located above the substrate structure and parallel to each other;
栅极叠层,所述栅极叠层覆盖所述衬底结构和部分第一、第二鳍片的侧
壁;a gate stack covering the substrate structure and portions of the first and second fins
wall;
源区,所述源区位于所述第一鳍片未被栅极叠层所覆盖的区域;a source region, the source region being located in an area where the first fin is not covered by the gate stack;
漏区,所述漏区位于所述第二鳍片未被栅极叠层所覆盖的区域;a drain region, the drain region being located in a region where the second fin is not covered by the gate stack;
侧墙,所述侧墙位于所述第一、第二鳍片两侧,用于隔离源区、漏区和栅极叠层。a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.
其中,所述第一、第二鳍片具有相同的高度、厚度和宽度。Wherein the first and second fins have the same height, thickness and width.
其中,所述栅极叠层包括:界面层、高K介质层、金属栅功函数调节层以及多晶硅。The gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
其中,所述栅极叠层的高度为所述第一、第二鳍片高度的1/2~3/4。The height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
相应的,本发明还提供了一种U型FinFET器件制造方法,包括:Correspondingly, the present invention also provides a U-shaped FinFET device manufacturing method, including:
a.提供衬底结构,所述衬底结构为SOI衬底;Providing a substrate structure, the substrate structure being an SOI substrate;
b.在所述衬底结构上形成第一鳍片和第二鳍片;b. forming a first fin and a second fin on the substrate structure;
c.在所述衬底结构、所述第一鳍片和第二鳍片上方形成栅极叠层;c. forming a gate stack over the substrate structure, the first fin and the second fin;
d.去除所述第一鳍片和第二鳍片上方和部分侧壁的栅极叠层,露出的部分第一和第二鳍片形成源漏区;d. removing the gate stack above and a portion of the sidewalls of the first fin and the second fin, the exposed portions of the first and second fins forming source and drain regions;
e.在未被所述栅极叠层覆盖的第一鳍片和第二鳍片两侧形成侧墙。e. forming sidewalls on both sides of the first fin and the second fin that are not covered by the gate stack.
其中,所述栅极叠层包括:界面层、高K介质层、金属栅功函数调节层以及多晶硅。The gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
其中,在步骤b中,形成所述第一鳍片和第二鳍片的方法为:Wherein, in step b, the method of forming the first fin and the second fin is:
b1)在所述衬底结构上依次形成沟道材料层和源漏材料层;B1) sequentially forming a channel material layer and a source/drain material layer on the substrate structure;
b2)对所述沟道材料层和源漏材料层进行刻蚀,形成第一鳍片和第二鳍片。B2) etching the channel material layer and the source/drain material layer to form a first fin and a second fin.
其中,形成所述第一鳍片和第二鳍片的方法为各向异性刻蚀。Wherein, the method of forming the first fin and the second fin is an anisotropic etching.
其中,所述第一鳍片和第二鳍片具有相同的高度、厚度和宽度。Wherein the first fin and the second fin have the same height, thickness and width.
其中,所述第一鳍片和第二鳍片之间的距离为5~50nm。The distance between the first fin and the second fin is 5 to 50 nm.
其中,所述栅极叠层包括:界面层、高K介质层、金属栅功函数调节层以及多晶硅。The gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
其中,所述栅极叠层的高度为所述第一、第二鳍片高度的1/2~3/4。
The height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
其中,形成所述栅极叠层的方法为原子层淀积。Wherein, the method of forming the gate stack is atomic layer deposition.
其中,去除部分栅极叠层的方法为各向异性选择性刻蚀。Among them, the method of removing a part of the gate stack is anisotropic selective etching.
其中,形成所述源漏区的方法为倾斜的离子注入。Wherein, the method of forming the source and drain regions is oblique ion implantation.
其中,形成所述源漏区的方法为侧向散射。Wherein, the method of forming the source and drain regions is side scatter.
其中,以未被侧墙覆盖的表面的硅为籽晶进行外延生长,形成源漏外延区。Wherein, the silicon of the surface not covered by the sidewall spacer is epitaxially grown to form a source-drain epitaxial region.
本发明在现有FinFET工艺的基础上提出了一种新的U型器件结构,与现有技术中相比,该结构使器件具有垂直的沟道,因而在footprint尺寸不变的情况下,器件可以通过改变Fin的高度来调节栅长,改善短沟道效应。首先,由于器件具有U型垂直沟道结构,器件源漏悬于衬底结构上方,与衬底结构天然分离,因而使得该器件的无法发生源漏穿通,从而具有较低的亚阈态斜率及漏电流。其次,由于器件具有U型垂直沟道结构,器件源漏相互平行且悬于衬底结构上方,有效隔离了器件漏端电场对源端的影响,因而进一步改善了器件的短沟道效应,使器件具有较小的DIBL。再次,由于器件具有U型垂直沟道结构,器件源漏悬于衬底结构上方且位于同一平面内,因而便于制作源漏接触。同时,本发明具有SOI结构,位于衬底区域被栅极叠层覆盖的沟道区具有SOI器件的优良特性,具有良好的栅控能力以,克服了体硅器件中该区域栅控能力差的缺点。最后,由于本发明中衬底结构沟道区被重掺杂,完全处于开启的状态,不受栅极电压控制,因此器件具有更高的工作电流。本发明提出的器件结构在制作工艺上与现有FinFET工艺完全兼容,极大地提高了器件性能。The present invention proposes a new U-shaped device structure based on the existing FinFET process. Compared with the prior art, the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. First, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current. Secondly, since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Has a smaller DIBL. Again, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts. At the same time, the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages. Finally, since the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
图1~图10示意性地示出了根据本发明中实施例1中的方法形成U型FinFET器件各阶段的剖面图;1 to 10 are schematic cross-sectional views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention;
图11示意性地示出了根据本发明中实施例2中的方法形成U型FinFET器件的剖面图。
Figure 11 is a schematic cross-sectional view showing the formation of a U-shaped FinFET device in accordance with the method of Embodiment 2 of the present invention.
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明的实施例作详细描述。In order to make the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in detail below.
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.
如图10所示,本发明提供了一种FinFET结构,包括:衬底结构,所述衬底结构为SOI衬底;第一鳍片和第二鳍片,所述第一、第二鳍片位于所述衬底结构上方,彼此平行;栅极叠层,所述栅极叠层覆盖所述衬底结构和部分第一、第二鳍片的侧壁;源区,所述源区位于所述第一鳍片未被栅极叠层所覆盖的区域;漏区,所述漏区位于所述第二鳍片未被栅极叠层所覆盖的区域;侧墙,所述侧墙位于所述第一、第二鳍片两侧,用于隔离源区、漏区和栅极叠层。As shown in FIG. 10, the present invention provides a FinFET structure including: a substrate structure, the substrate structure is an SOI substrate; a first fin and a second fin, the first and second fins Located above the substrate structure, parallel to each other; a gate stack covering the substrate structure and sidewalls of a portion of the first and second fins; a source region, the source region being located a region where the first fin is not covered by the gate stack; a drain region located in a region where the second fin is not covered by the gate stack; a sidewall, the sidewall is located at The first and second fins are on both sides for isolating the source region, the drain region and the gate stack.
其中,所述SOI衬底包括顶层衬底150、埋氧层101以及支撑衬底100。The SOI substrate includes a top substrate 150, a buried oxide layer 101, and a support substrate 100.
其中,所述第一、第二鳍片具有相同的高度、厚度和宽度。Wherein the first and second fins have the same height, thickness and width.
其中,所述栅极叠层300包括:界面层、高K介质层、金属栅功函数调节层以及多晶硅。The gate stack 300 includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
其中,所述栅极叠层的高度为所述第一、第二鳍片高度的1/2~3/4。The height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
本发明在现有FinFET工艺的基础上提出了一种新的U型器件结构,与现有技术中相比,该结构使器件具有垂直的沟道,因而在footprint尺寸不变的情况下,器件可以通过改变Fin的高度来调节栅长,改善短沟道效应。首先,由于器件具有U型垂直沟道结构,器件源漏悬于衬底结构上方,与衬底结构天然分离,因而使得该器件的无法发生源漏穿通,从而具有较低的亚阈态斜率及漏电流。其次,由于器件具有U型垂直沟道结构,器件源漏相互平行且悬于衬底结构上方,有效隔离了器件漏端电场对源端的影响,因而进一步改善了器件的短沟道效应,使器件具有
较小的DIBL。再次,由于器件具有U型垂直沟道结构,器件源漏悬于衬底结构上方且位于同一平面内,因而便于制作源漏接触。同时,本发明具有SOI结构,位于衬底区域被栅极叠层覆盖的沟道区具有SOI器件的优良特性,具有良好的栅控能力以,克服了体硅器件中该区域栅控能力差的缺点。最后,由于本发明中衬底结构沟道区被重掺杂,完全处于开启的状态,不受栅极电压控制,因此器件具有更高的工作电流。本发明提出的器件结构在制作工艺上与现有FinFET工艺完全兼容,极大地提高了器件性能。The present invention proposes a new U-shaped device structure based on the existing FinFET process. Compared with the prior art, the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. First, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and is naturally separated from the substrate structure, thereby making the device unable to pass through the source and the drain, thereby having a low sub-threshold slope and Leakage current. Secondly, since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate structure, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device Have
Smaller DIBL. Again, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate structure and in the same plane, thereby facilitating fabrication of source-drain contacts. At the same time, the present invention has an SOI structure, and the channel region covered by the gate stack in the substrate region has excellent characteristics of the SOI device, and has good gate control capability, thereby overcoming the poor gate control capability of the region in the bulk silicon device. Disadvantages. Finally, since the channel region of the substrate structure is heavily doped in the present invention, it is completely turned on, and is not controlled by the gate voltage, so the device has a higher operating current. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
以下将参照附图更详细地描述本实发明。在各个附图中,相同的元件采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。The present invention will be described in more detail below with reference to the accompanying drawings. Throughout the drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.
应当理解,在描述器件的结构时,当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时,可以指直接位于另一层、另一个区域上面,或者在其与另一层、另一个区域之间还包含其它的层或区域。并且,如果将器件翻转,该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "above" or "above" another layer, it may mean that it is directly on another layer or another region, or Other layers or regions are also included between it and another layer. Also, if the device is flipped, the layer, one area will be located on the other layer, and the other area "below" or "below".
如果为了描述直接位于另一层、另一个区域上面的情形,本文将采用“直接在……上面”或“在……上面并与之邻接”的表述方式。In the case of a description directly above another layer or another region, this document will use the expression "directly above" or "adjacent to and adjacent to".
在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。例如,衬底结构和鳍片的半导体材料可以选自IV族半导体,如Si或Ge,或III-V族半导体,如GaAs、InP、GaN、SiC,或上述半导体材料的叠层。Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. For example, the semiconductor material of the substrate structure and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
首先结合附图对本发明的实施例1进行详细描述。First, the embodiment 1 of the present invention will be described in detail with reference to the accompanying drawings.
参见图1,示出了本发明中的支撑衬底100。所述支撑衬底100材料为半导体材料,可以是硅,锗,砷化镓等,优选的,在本实施例中,所用支撑衬底100的材料为硅,其厚度为100~500nm。接下来,如图2所
示,在所述支撑衬底100上方形成埋氧层。具体的,可以采用化学汽相淀积或原子层淀积的方法形成所述埋氧层101,所述埋氧层的厚度为20~50nm。最后,在所述埋氧层101上方形成顶层衬底150,也就是器件工作时的有效衬底区域;为了保证薄膜质量,优选的,采用原子层淀积的方法形成所述顶层衬底150,其厚度为20~50nm。Referring to Figure 1, a support substrate 100 in the present invention is illustrated. The material of the support substrate 100 is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like. Preferably, in the embodiment, the material of the support substrate 100 used is silicon, and the thickness thereof is 100-500 nm. Next, as shown in Figure 2.
A buried oxide layer is formed over the support substrate 100. Specifically, the buried oxide layer 101 may be formed by chemical vapor deposition or atomic layer deposition, and the buried oxide layer has a thickness of 20 to 50 nm. Finally, a top substrate 150 is formed over the buried oxide layer 101, that is, an effective substrate region when the device is in operation; in order to ensure film quality, preferably, the top substrate 150 is formed by atomic layer deposition. Its thickness is 20 to 50 nm.
对于本发明中的U型FinFET结构,其栅极结构分为两个部分,除了分别位于第一、第二鳍片上的被栅极叠层覆盖的区域之外,位于鳍片之间顶层衬底150上被栅极叠层300覆盖的区域也是器件沟道的一部分。由于衬底结构厚度远大于鳍片的厚度,因此栅极对于位于衬底结构上的沟道区域的控制能力相对较弱,对器件的工作电流形成一定的制约。为了改善这种情况,我们结合SOI技术对本发明进行了改进,采用SOI衬底代替体硅衬底,使得衬底区域的顶层硅150具有很薄的厚度,可以进一步实现集成电路中元器件的介质隔离,彻底消除了体硅CMOS电路中的寄生闩锁效应;同时相比于体硅器件,本发明中采用SOI衬底可以进一步减小漏电流,增强器件的栅控能力,从而大幅度提升器件性能。For the U-shaped FinFET structure of the present invention, the gate structure is divided into two parts, except for the regions covered by the gate stack on the first and second fins, respectively, and the top substrate between the fins. The area covered by gate stack 300 on 150 is also part of the device channel. Since the thickness of the substrate structure is much larger than the thickness of the fin, the control ability of the gate to the channel region on the substrate structure is relatively weak, which imposes certain constraints on the operating current of the device. In order to improve this situation, we have improved the invention by combining SOI technology, using SOI substrate instead of bulk silicon substrate, so that the top layer silicon 150 of the substrate region has a very thin thickness, and the medium of components in the integrated circuit can be further realized. Isolation completely eliminates the parasitic latch-up effect in bulk silicon CMOS circuits. At the same time, compared with bulk silicon devices, the SOI substrate in the present invention can further reduce leakage current and enhance the gate control capability of the device, thereby greatly improving the device. performance.
接下来,如图4所示,在所述顶层衬底150上依次外延生长沟道材料层110和源漏材料层120。所述沟道材料层110在经过后续工艺的处理后为器件沟道区的主要部分,可以轻掺杂或者不掺杂;掺杂类型根据器件的类型而定。对于N型器件,沟道材料层的掺杂类型为P型,可采用的掺杂杂质为硼等三族元素;对于P型器件,沟道材料层的掺杂类型为N型,可采用的掺杂杂质为磷、砷等五族元素。在本实施例中,后续工艺中形成的沟道区具有1e15cm-3的掺杂浓度,所采用的掺杂元素为硼,该掺杂通过外延时原位掺杂形成,具体的工艺步骤与现有工艺相同,在此不再赘述。Next, as shown in FIG. 4, a channel material layer 110 and a source/drain material layer 120 are epitaxially grown on the top substrate 150 in this order. The channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device. For the N-type device, the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used. The doping impurities are five elements such as phosphorus and arsenic. In this embodiment, the channel region formed in the subsequent process has a doping concentration of 1e15 cm -3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
所述源漏材料层120在经过后续工艺的处理后,将成为器件源漏区的主要部分,其掺杂浓度与源漏区所需浓度相等;掺杂类型根据器件的类型而定。对于N型器件,沟道材料层的掺杂类型为N型,可采用的掺杂杂质为磷、砷等五族元素;对于P型器件,沟道材料层的掺杂类型为P
型,可采用的掺杂杂质为硼等三族元素。在本实施例中,后续工艺中形成的源漏区具有1e19cm-3的掺杂浓度,所采用的掺杂元素为砷,该掺杂通过外延时原位掺杂形成,具体的工艺步骤与现有工艺相同,在此不再赘述。The source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device. For the N-type device, the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic; for the P-type device, the doping type of the channel material layer is P-type, The doping impurity used is a group III element such as boron. In this embodiment, the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm -3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
形成源漏材料层120之后的结构如图4所示,图中所示沟道材料层110的厚度为H2,等于器件形成之后栅极叠层高度。源漏材料层120的厚度为H1。The structure after forming the source/drain material layer 120 is as shown in FIG. 4, and the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the gate stack height after device formation. The thickness of the source/drain material layer 120 is H1.
接下来,经过投影,曝光,显影,刻蚀等常规工艺对所述沟道材料层110和源漏材料层120进行刻蚀,形成第一鳍片210和第二鳍片220,所述刻蚀方法可以是干法刻蚀或干法/湿法刻蚀。如图5所示,所述第一鳍片210和第二鳍片220刻蚀完成之后的高度等于所述沟道材料层110和源漏材料层120的厚度H2+H1,其中,所述沟道材料层110的厚度H2即为后续工艺中形成的栅极叠层的高度,所述源漏材料层120的厚度H1即为后续工艺中形成的源漏区的高度。Next, the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching The method can be dry etching or dry/wet etching. As shown in FIG. 5, the height after the first fin 210 and the second fin 220 are etched is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench The thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process, and the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.
接下来,在所述顶层衬底150和所述第一鳍片210和第二鳍片220上方形成栅极叠层300,与现有的FinFET工艺相同,所述栅极叠层300依次包括界面层310、高K介质层320、金属栅功函数调节层330以及多晶硅340。Next, a gate stack 300 is formed over the top substrate 150 and the first fins 210 and the second fins 220, which is the same as the existing FinFET process, and the gate stack 300 includes interfaces in sequence. Layer 310, high K dielectric layer 320, metal gate work function adjustment layer 330, and polysilicon 340.
其中,所述界面层310的材料为二氧化硅,用于消除第一、第二鳍片表面的缺陷和界面态,考虑到器件的栅控能力以及其他性能,所述界面层310的厚度一般为0.5~1nm;所述高K介质层320一般为高K介质,如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,栅介质层的厚度可以为1nm-10nm,例如3nm、5nm或8nm,形成高K介质层之后的器件结构如图6所示;所述金属栅功函数调节层330可以采用TiN、TaN等材料制成,其厚度范围为3nm~15nm,形成金属栅功函数调节层330之后的器件结构如图7所示。Wherein, the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties. 0.5 to 1 nm; the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO Or a combination thereof, the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG. 6; the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm. The device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 7 .
为了使栅极叠层300具有良好的台阶覆盖特性,获得质量优良的薄膜,
上述形成栅极叠层的工艺均采用原子层淀积的方法形成。In order to provide the gate stack 300 with good step coverage characteristics, a film of excellent quality is obtained,
The above processes for forming the gate stack are all formed by atomic layer deposition.
接下来,在所述金属栅功函数调节层330表面形成多晶硅340。首先,采用化学汽相淀积的方法在所述器件表面淀积一层多晶硅,使其覆盖整个器件10~50nm;接下来,对所述多晶硅层进行平坦化,所述平坦化方法可以是化学机械抛光(CMP),使所述多晶硅表面高度一致,以所述金属栅功函数调节层330作为化学机械抛光的停止层,使其余区域的多晶硅与所述金属栅功函数调节层330平齐;接下来,使用各向异性选择性刻蚀对所述多晶硅层进行定向刻蚀,使其表面与所述源漏材料层120底部平齐,如图8所示。Next, polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330. First, a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry. Mechanical polishing (CMP), the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330; Next, the polysilicon layer is etched using anisotropic selective etching to have its surface flush with the bottom of the source/drain material layer 120, as shown in FIG.
接下来,对覆盖所述第一鳍片210和第二鳍片220的栅极叠层进行各向同性选择性刻蚀,去除其位于多晶硅层340上方的部分,露出部分所述鳍片,如图9所示。对露出的鳍片进行倾斜的离子注入或者侧向散射形成所述源漏区。Next, the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove a portion thereof above the polysilicon layer 340 to expose a portion of the fin, such as Figure 9 shows. The source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.
接下来,在露出的部分所述鳍片侧壁上形成侧墙230,用于将栅极叠层与源漏区隔开。侧墙230可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合,和/或其他合适的材料形成。侧墙230可以具有多层结构。侧墙可以通过包括沉积刻蚀工艺形成,其厚度范围可以是10nm-100nm,如30nm、50nm或80nm,如图10所示。Next, a sidewall spacer 230 is formed on the exposed portion of the fin sidewall to separate the gate stack from the source and drain regions. Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials. The side wall 230 may have a multi-layered structure. The sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm, as shown in FIG.
在本发明的实施例2中,如图11所示,可选的,在侧墙230形成之后,以鳍片表面未被侧墙230覆盖的区域的硅为籽晶进行外延生长,形成源漏外延区240,即raised-SD,如图11所示。在外延生长的同时进行原位掺杂,使外延区具有与源漏区相同的掺杂浓度。In the second embodiment of the present invention, as shown in FIG. 11 , optionally, after the sidewall spacer 230 is formed, silicon in a region where the surface of the fin is not covered by the sidewall spacer 230 is epitaxially grown to form a source drain. The epitaxial region 240, that is, raised-SD, is as shown in FIG. In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.
接下来,与现有技术相同,在所述源漏区和栅极上方形成硅化物以及金属电极,具体工艺步骤在此不再赘述。Next, as in the prior art, a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
While the invention has been described with respect to the preferred embodiments and the embodiments of the present invention, it is understood that various changes, substitutions and modifications may be made to the embodiments without departing from the spirit and scope of the invention. For other examples, those of ordinary skill in the art will readily appreciate that the order of process steps may vary while remaining within the scope of the invention.
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Further, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition of matter, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be readily understood by those skilled in the art that the processes, mechanisms, manufactures, compositions, means, methods, or steps that are presently present or will be developed in the The corresponding embodiments described have substantially the same function or substantially the same results, which can be applied in accordance with the invention. Therefore, the appended claims are intended to cover such modifications, such structures, structures,
Claims (18)
- 一种U型FinFET器件结构,包括:A U-shaped FinFET device structure comprising:衬底结构,所述衬底结构为SOI衬底;a substrate structure, the substrate structure being an SOI substrate;第一鳍片(210)和第二鳍片(220),所述第一鳍片(210)和第二鳍片(220)位于所述衬底结构上方,彼此平行;a first fin (210) and a second fin (220), the first fin (210) and the second fin (220) being located above the substrate structure, parallel to each other;栅极叠层(300),所述栅极叠层覆盖所述衬底结构和部分第一鳍片(210)和第二鳍片(220)的侧壁;a gate stack (300), the gate stack covering sidewalls of the substrate structure and portions of the first fins (210) and the second fins (220);源区(410),所述源区位于所述第一鳍片(210)未被栅极叠层所覆盖的区域;a source region (410), the source region being located in a region where the first fin (210) is not covered by the gate stack;漏区(420),所述漏区位于所述第二鳍片(220)未被栅极叠层所覆盖的区域;a drain region (420), the drain region being located in a region where the second fin (220) is not covered by the gate stack;侧墙(230),所述侧墙(230)位于所述第一鳍片(210)和第二鳍片(220)两侧,栅极叠层(300)上方,用于隔离源区、漏区和栅极叠层。a side wall (230), the side wall (230) is located on both sides of the first fin (210) and the second fin (220), above the gate stack (300), for isolating the source region and the drain Zone and gate stack.
- 根据权利要求1所述的FinFET器件结构,其特征在于,所述第一鳍片(210)和第二鳍片(220)具有相同的高度、厚度和宽度。The FinFET device structure of claim 1 wherein the first fins (210) and the second fins (220) have the same height, thickness, and width.
- 根据权利要求1所述的FinFET器件结构,其特征在于,所述第一鳍片(210)和第二鳍片(220)之间的距离为5~50nm。The FinFET device structure of claim 1 wherein the distance between the first fin (210) and the second fin (220) is between 5 and 50 nm.
- 根据权利要求1所述的FinFET器件结构,其特征在于,所述栅极叠层(300)的高度为所述第一、第二鳍片(210、220)高度的1/2~3/4。The FinFET device structure according to claim 1, wherein the height of the gate stack (300) is 1/2 to 3/4 of the height of the first and second fins (210, 220). .
- 根据权利要求1所述的FinFET器件结构,其特征在于,所述栅极叠层(300)包括:界面层(310)、高K介质层(320)、金属栅功函数调节层(330)以及多晶硅(340)。 The FinFET device structure according to claim 1, wherein the gate stack (300) comprises: an interface layer (310), a high-k dielectric layer (320), a metal gate work function adjustment layer (330), and Polysilicon (340).
- 一种U型FinFET器件制造方法,包括:A U-shaped FinFET device manufacturing method includes:a.提供衬底结构,所述衬底结构为SOI衬底;Providing a substrate structure, the substrate structure being an SOI substrate;b.在所述衬底结构上形成第一鳍片(210)和第二鳍片(220);b. forming a first fin (210) and a second fin (220) on the substrate structure;c.在所述衬底结构、所述第一鳍片(210)和第二鳍片(220)上方形成栅极叠层;c. forming a gate stack over the substrate structure, the first fin (210) and the second fin (220);d.去除所述第一鳍片(210)和第二鳍片(220)上方和部分侧壁的栅极叠层,露出的部分第一和第二鳍片形成源漏区;d. removing the gate stack above and a portion of the sidewalls of the first fin (210) and the second fin (220), the exposed portions of the first and second fins forming source and drain regions;e.在未被所述栅极叠层覆盖的第一鳍片(210)和第二鳍片(220)两侧形成侧墙(230)。e. Forming sidewalls (230) on both sides of the first fin (210) and the second fin (220) that are not covered by the gate stack.
- 根据权利要求6所述的制造方法,其特征在于,所述栅极叠层(300)包括:界面层(310)、高K介质层(320)、金属栅功函数调节层(330)以及多晶硅(340)。The manufacturing method according to claim 6, wherein the gate stack (300) comprises: an interface layer (310), a high-k dielectric layer (320), a metal gate work function adjusting layer (330), and polysilicon. (340).
- 根据权利要求6所述的制造方法,其特征在于,在步骤b中,形成所述第一鳍片(210)和第二鳍片(220)的方法为:The manufacturing method according to claim 6, wherein in the step b, the method of forming the first fin (210) and the second fin (220) is:b1)在所述衬底结构上依次形成沟道材料层(110)和源漏材料层(120);B1) sequentially forming a channel material layer (110) and a source/drain material layer (120) on the substrate structure;b2)对所述沟道材料层(110)和源漏材料层(120)进行刻蚀,形成第一鳍片(210)和第二鳍片(220)。B2) etching the channel material layer (110) and the source/drain material layer (120) to form a first fin (210) and a second fin (220).
- 根据权利要求6所述的制造方法,其特征在于,形成所述第一鳍片(210)和第二鳍片(220)的方法为各向异性刻蚀。The manufacturing method according to claim 6, wherein the method of forming the first fins (210) and the second fins (220) is anisotropic etching.
- 根据权利要求6所述的制造方法,其特征在于,所述第一鳍片(210)和第二鳍片(220)具有相同的高度、厚度和宽度。The manufacturing method according to claim 6, wherein the first fins (210) and the second fins (220) have the same height, thickness, and width.
- 根据权利要求6所述的制造方法,其特征在于,所述第一鳍片(210)和第二鳍片(220)之间的距离为5~50nm。 The manufacturing method according to claim 6, wherein a distance between the first fin (210) and the second fin (220) is 5 to 50 nm.
- 根据权利要求6所述的制造方法,其特征在于,所述栅极叠层(300)包括:界面层(310)、高K介质层(320)、金属栅功函数调节层(330)以及多晶硅(340)。The manufacturing method according to claim 6, wherein the gate stack (300) comprises: an interface layer (310), a high-k dielectric layer (320), a metal gate work function adjusting layer (330), and polysilicon. (340).
- 根据权利要求6所述的制造方法,其特征在于,所述栅极叠层(300)的高度为所述第一、第二鳍片(210、220)高度的1/2~3/4。The manufacturing method according to claim 6, wherein the height of the gate stack (300) is 1/2 to 3/4 of the height of the first and second fins (210, 220).
- 根据权利要求6所述的制造方法,其特征在于,形成所述栅极叠层的方法为原子层淀积。The method of manufacturing according to claim 6, wherein the method of forming the gate stack is atomic layer deposition.
- 根据权利要求6所述的制造方法,其特征在于,去除部分栅极叠层的方法为各向异性选择性刻蚀。The method of manufacturing according to claim 6, wherein the method of removing a portion of the gate stack is anisotropic selective etching.
- 根据权利要求6所述的制造方法,其特征在于,形成所述源漏区的方法为倾斜的离子注入。The manufacturing method according to claim 6, wherein the method of forming the source/drain regions is oblique ion implantation.
- 根据权利要求6所述的制造方法,其特征在于,形成所述源漏区的方法为侧向散射。The manufacturing method according to claim 6, wherein the method of forming the source and drain regions is side scatter.
- 根据权利要求6所述的制造方法,其特征在于,以未被侧墙覆盖的表面的硅为籽晶进行外延生长,形成源漏外延区。 The manufacturing method according to claim 6, wherein the surface of the surface not covered by the sidewall spacer is epitaxially grown to form a source/drain epitaxial region.
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