WO2016037398A1

WO2016037398A1 - Finfet structure and manufacturing method therefor

Info

Publication number: WO2016037398A1
Application number: PCT/CN2014/088603
Authority: WO
Inventors: 刘云飞; 尹海洲; 李睿
Original assignee: 中国科学院微电子研究所
Priority date: 2014-09-10
Filing date: 2014-10-15
Publication date: 2016-03-17
Also published as: CN105405884A; CN105405884B

Abstract

A FinFET structure and a manufacturing method therefor. The FinFET structure comprises: a substrate; a first fin and a second fin, located above the substrate and parallel to each other; a device separation region, enclosing the substrate and aligned with the first fin and the second fin; a gate stacked layer, covering the substrate and parts of side walls of the first fin and the second fin; a source region, located in a region of the first fin not covered by the gate stacked layer; a drain region, located in a region of the second fin not covered by the gate stacked layer; and a side wall, located on two sides of the first fin and the second fin and located above the gate stacked layer, and used for separating the source region, the drain region and the gate stacked layer. A new device structure is provided on the basis of an existing FinFET process, so that the gate length of a device is not limited by the size of a footprint, and therefore the problem resulting from a short-channel effect is effectively solved.

Description

FinFET structure and manufacturing method thereof

The present application claims priority to Chinese Patent Application Serial No. No. No. No. No. No. No. No. No. No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No

Technical field

The present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.

technical background

Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles. At present, with the development of integrated circuit technology and technology, devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced. However, since 2011, silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device. The operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.

Summary of the invention

The invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect. Specifically, the structure includes:

Substrate

a first fin and a second fin, the first and second fins being located above the substrate and parallel to each other;

a device isolation region, the device isolation region surrounding the substrate, and the first and second fins Flush

a gate stack, the gate stack covering sidewalls of the substrate and portions of the first and second fins;

a source region, the source region being located in an area where the first fin is not covered by the gate stack;

The source end epitaxial region is located above one end of the first fin and has a length less than 1/2 of the length of the fin;

a drain region, the drain region being located in an area of the second fin not covered by the gate stack;

a drain extension region, located above the other end of the second fin opposite to the source region, the length of which is less than 1/2 of the length of the fin;

a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.

Wherein the first and second fins have the same height, thickness and width.

Wherein, the material of the device isolation region is silicon dioxide.

The gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.

The height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.

Correspondingly, the present invention also provides a U-shaped FinFET device manufacturing method, including:

Providing a substrate, forming a device isolation region around the substrate;

b. forming a first fin and a second fin on the substrate;

c. forming a gate stack over the substrate, the first fin and the second fin;

d. removing a portion of the gate stack above the first and second fins, forming sidewalls on both sides of the first and second fins that are not covered by the gate stack.

Wherein, in step a, the method for forming the device isolation region is:

1) sequentially forming a channel material layer and a source/drain material layer on the substrate;

2) forming a deep hole on the substrate, the channel material layer, and the source/drain material layer, the deep hole surrounding the substrate;

3) depositing an isolation medium in the deep hole to form a device isolation region.

Wherein, in step b, the method of forming the first fin and the second fin is:

4) etching the channel material layer and the source/drain material layer to form a first fin and a second fin sheet.

Wherein, the material forming the isolation region of the device is silicon dioxide.

Wherein, the method of forming the gate stack is atomic layer deposition.

Among them, the method of removing a part of the gate stack is anisotropic selective etching.

Wherein, the method of forming the source and drain regions is oblique ion implantation.

Wherein, the method of forming the source and drain regions is side scatter.

The present invention proposes a new U-shaped device structure based on the existing FinFET process. Compared with the prior art, the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. Since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current. Since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device smaller. DIBL. At the same time, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating the fabrication of source-drain contacts. At the same time, since the structure of the U-shaped device along the width direction of the fin is asymmetric, the present invention proposes a device isolation method based on the existing process, which effectively avoids the interconnection between the source and the drain of different devices. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.

DRAWINGS

1 through 11 schematically illustrate schematic views of stages in forming a U-shaped FinFET device in accordance with a method in an embodiment of the present invention.

The same or similar figures in the figures represent the same components.

detailed description

In order to make the objects, technical solutions and advantages of the present invention more clear, the following will be described in conjunction with the accompanying drawings. The embodiments of the invention are described in detail.

The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.

As shown in FIGS. 10-11, the present invention provides a FinFET structure including: a substrate 100; a first fin 210 and a second fin 220, the first fin 210 and the second fin 220 being located at Above the substrate 100, parallel to each other; a device isolation region 200, the device isolation region surrounding the substrate, flush with the first and second fins; a gate stack 300, the gate stack overlay a sidewall of the substrate and a portion of the first fin 210 and the second fin 220; a source region 410, the source region being located in an area where the first fin 210 is not covered by the gate stack; a drain region 420. The drain region is located in a region where the second fin 220 is not covered by the gate stack.

The structure further includes a sidewall spacer 230 disposed on both sides of the first fin 210 and the second fin 220 for isolating the source region, the drain region, and the gate stack.

Wherein, the first fin 210 and the second fin 220 have the same height, thickness and width.

Wherein, the material of the device isolation region 200 is silicon dioxide.

The gate stack includes an interface layer 310, a high-k dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340.

The height of the gate stack 300 is 1/2 to 3/4 of the height of the first and

second fins

210 and 220.

The present invention proposes a new U-shaped device structure based on the existing FinFET process. Compared with the prior art, the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. Since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current. Since the device has a U-shaped vertical channel structure, the source and drain of the device are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device. One step improves the short channel effect of the device, allowing the device to have a smaller DIBL. At the same time, since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating the fabrication of source-drain contacts. At the same time, since the structure of the U-shaped device along the width direction of the fin is asymmetric, the present invention proposes a device isolation method based on the existing process, which effectively avoids the interconnection between the source and the drain of different devices. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.

The present invention will be described in more detail below with reference to the accompanying drawings. Throughout the drawings, the same elements are denoted by like reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.

It should be understood that when describing a structure of a device, when a layer or a region is referred to as being "above" or "above" another layer, it may mean that it is directly on another layer or another region, or Other layers or regions are also included between it and another layer. Also, if the device is flipped, the layer, one area will be located on the other layer, and the other area "below" or "below".

In the case of a description directly above another layer or another region, this document will use the expression "directly above" or "adjacent to and adjacent to".

Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. For example, the semiconductor material of the substrate and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.

First, the embodiment 1 of the present invention will be described in detail with reference to the accompanying drawings.

Referring to Figure 1, a first substrate 100 in the present invention is illustrated. The first substrate material is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like. Preferably, in the embodiment, the substrate used is a silicon substrate.

Next, a channel material layer 110 and a source/drain material layer 120 are epitaxially grown on the substrate 100 in this order. The channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device. For the N-type device, the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used. The doping impurities are five elements such as phosphorus and arsenic. In this embodiment, the channel region formed in the subsequent process has a doping concentration of 1e15 cm ^-3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.

The source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device. For the N-type device, the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic; for the P-type device, the doping type of the channel material layer is P-type, The doping impurity used is a group III element such as boron. In this embodiment, the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm ^-3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.

The structure after forming the source/drain material layer 120 is as shown in FIG. 2. The thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the height of the gate stack after the device is formed. The thickness of the source/drain material layer 120 is H1.

Since the source-drain region of the U-shaped FinFET device of the present invention is located on two adjacent fins instead of being located at the opposite ends of the same fin as in the conventional device structure, how to implement the phase in mass production The isolation of adjacent devices becomes a new difficulty. To this end, the present invention proposes an isolation method in which adjacent devices are separated by a method of forming an isolation region around each period.

Specifically, first, a deep hole 101 is formed on the substrate 100, the channel material layer 110, and the source/drain material layer 120, and the deep hole 101 surrounds the substrate. Specifically, the source/drain material layer 120 is covered with a photoresist, and the annular region to be etched on the source/drain material layer 120 is exposed through a conventional process step such as exposure and development; A deep hole 101 is formed on the exposed substrate region as shown in FIG. The deep holes penetrate the source/drain material layer 120, the channel material layer 110, and the substrate 100. Finally, the isolation medium is filled in the deep hole to complete isolation. The material of the isolation medium may be silicon oxide, and the filling method may be Learn to vapor phase deposition. The structure of the completed device is shown in Figure 4.

Next, the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching The method can be dry etching or dry/wet etching. As shown in FIG. 5, the height after the first fin 210 and the second fin 220 are etched is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench The thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process, and the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.

Next, as shown in FIGS. 6-8, a gate stack 300 is formed over the substrate 100 and the first fin 210 and the second fin 220, which is the same as the existing FinFET process. The pole stack 300 includes an interface layer 310, a high K dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340 at a time.

Wherein, the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties. 0.5 to 1 nm; the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al ₂ O ₃ , La ₂ O ₃ , ZrO ₂ , LaAlO Or a combination thereof, the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG. 6; the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm. The device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 7 .

In order to obtain a good step coverage characteristic of the gate stack 300 and obtain a film of excellent quality, the above-described process for forming a gate stack is formed by atomic layer deposition.

Next, polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330. First, a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry. Mechanical polishing (CMP) to make the surface of the polysilicon highly uniform, with the metal gate work function adjusting layer 330 as a stop layer for chemical mechanical polishing, so that the remaining regions are polycrystalline Silicon is flush with the metal gate work function adjusting layer 330; next, the polysilicon layer is etched using anisotropic selective etching to make the surface flush with the source/drain material layer 120, such as Figure 8 shows.

Next, the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove the portion above the polysilicon layer 340 to expose the fins. 9 is shown.

Next, as shown in FIG. 10, sidewall spacers 230 are formed on the sidewalls of the gate stack for separating the gate stack from the source and drain regions. Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials. The side wall 230 may have a multi-layered structure. The sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.

Next, as shown in FIG. 11, epitaxial growth is performed by using silicon as a seed crystal whose fin surface is not covered by the sidewall spacer 230, and source-drain

epitaxial regions

240 and 250, ie, raised-SD, are formed in situ while epitaxial growth. Doping allows the epitaxial region to have the same doping concentration as the source and drain regions.

Next, as in the prior art, a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.

The invention proposes an isolation method for U-type FinFET devices based on the existing technology, and effectively avoids the formation of interconnection between source and drain of different devices. The device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance. While the invention has been described with respect to the preferred embodiments and the embodiments of the present invention, it is understood that various changes, substitutions and modifications may be made to the embodiments without departing from the spirit and scope of the invention. For other examples, those of ordinary skill in the art will readily appreciate that the order of process steps may vary while remaining within the scope of the invention.

Further, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition of matter, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be readily understood by those skilled in the art that the processes, mechanisms, manufactures, compositions, means, methods, or steps that are presently present or will be developed in the The corresponding embodiments described are substantially identical in function or obtained substantially the same As a result, they can be applied in accordance with the present invention. Therefore, the appended claims are intended to cover such processes, mechanisms, manufacture, compositions, methods, methods or steps.

Claims

A U-shaped FinFET device structure comprising:

Substrate (100);

a first fin (210) and a second fin (220), the first fin (210) and the second fin (220) being located above the substrate (100), parallel to each other;

a device isolation region (200), the device isolation region surrounding the substrate, flush with the first and second fins;

a gate stack (300), the gate stack covering sidewalls of the substrate and portions of the first fins (210) and the second fins (220);

a source region (410), the source region being located in an area where the first fin (210) is not covered by the gate stack;

a drain region (420), the drain region being located in a region where the second fin (220) is not covered by the gate stack;

a side wall (230), the side wall (230) is located on both sides of the first fin (210) and the second fin (220), above the gate stack (300), for isolating the source region and the drain Zone and gate stack.
The FinFET device structure of claim 1 wherein the first fins (210) and the second fins (220) have the same height, thickness, and width.
The FinFET device structure of claim 1 wherein the distance between the first fin (210) and the second fin (220) is between 5 and 50 nm.
The FinFET device structure of claim 1 wherein the material of the device isolation region (200) is silicon dioxide.
The FinFET device structure according to claim 1, wherein the height of the gate stack (300) is 1/2 to 3/4 of the height of the first and second fins (210, 220). .
A U-shaped FinFET device manufacturing method includes:

Providing a substrate (100), forming a device isolation region (200) around the substrate (100);

b. forming a first fin (210) and a second fin (220) on the substrate (100);

c. forming a gate stack (300) over the substrate (100), the first fin (210) and the second fin (220);

d. removing a portion of the gate stack above the first and second fins, forming sidewall spacers (230) on both sides of the first and second fins not covered by the gate stack.
The manufacturing method according to claim 6, wherein in the step a, the method of forming the device isolation region is:

Forming a channel material layer (110) and a source/drain material layer (120) on the substrate (100);

Forming a deep hole (101) on the substrate (100), the channel material layer (110), and the source/drain material layer (120), the deep hole (101) surrounding the substrate;

An isolation dielectric is deposited in the deep via to form a device isolation region (200).
The manufacturing method according to claim 6, wherein in the step b, the method of forming the first fin (210) and the second fin (220) is:

The channel material layer (110) and the source/drain material layer (120) are etched to form a first fin (210) and a second fin (220).
The method of manufacturing according to claim 8, wherein the material forming the device isolation region (200) is silicon dioxide.
The manufacturing method according to claim 6, wherein a distance between the first fin (210) and the second fin (220) is 5 to 50 nm.
The manufacturing method according to claim 6, wherein the first fin is formed The method of (210) and the second fin (220) is an anisotropic etch.
The manufacturing method according to claim 6, wherein the height of the gate stack (300) is 1/2 to 3/4 of the height of the first and second fins (210, 220).
The method of manufacturing according to claim 6, wherein the method of forming the gate stack is atomic layer deposition.
The method of manufacturing according to claim 6, wherein the method of removing a portion of the gate stack is anisotropic selective etching.
The manufacturing method according to claim 6, wherein the method of forming the source/drain regions is oblique ion implantation.
The manufacturing method according to claim 6, wherein the method of forming the source and drain regions is side scatter.