CN105405886B - A kind of FinFET structure and its manufacturing method - Google Patents
A kind of FinFET structure and its manufacturing method Download PDFInfo
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- CN105405886B CN105405886B CN201410459571.1A CN201410459571A CN105405886B CN 105405886 B CN105405886 B CN 105405886B CN 201410459571 A CN201410459571 A CN 201410459571A CN 105405886 B CN105405886 B CN 105405886B
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- 239000000463 material Substances 0.000 claims description 36
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
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- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
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- 230000008859 change Effects 0.000 description 4
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- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
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- 229910004143 HfON Inorganic materials 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 235000013399 edible fruits Nutrition 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention provides a kind of FinFET structure and its manufacturing methods, including：Substrat structure, the structure that sinks to the bottom is SOI substrate；First fin and the second fin, first, second fin is located above the substrat structure, parallel to each other；Gate stack covers the side wall of the first, second fin of the substrat structure and part；Source region, positioned at the region that first fin is not covered by gate stack；Drain region, positioned at the region that second fin is not covered by gate stack；Side wall is located at first, second fin both sides, gate stack top, for source region, drain region and gate stack to be isolated；Substrat structure channel region, the substrat structure channel region are located in the substrat structure in the region of upper surface.The present invention proposes a kind of new device architecture on the basis of existing FinFET techniques, so that the grid length of device is not limited by footprint sizes, efficiently solves the problems, such as caused by short-channel effect.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing methods, and in particular, to a kind of FinFET manufacturing methods.
Technical background
Moore's Law is pointed out：Open ended transistor size was doubled every 18 months on integrated circuit, and performance is also same
Mono- times of Shi Tisheng.Currently, with the development of integrated circuit technology and technology, successively there is diode, MOSFET, FinFET etc.
Device, node size constantly reduce.However, since 2011, silicon transistor has had been approached atomic level, has reached physics pole
Limit, due to the natural quality of this substance, other than short-channel effect, the quantum effect of device also generates the performance of device
Prodigious influence, the speed of service and performance difficulty of silicon transistor have breakthrough development.Therefore, how can not reduce feature
In the case of size, the performance for significantly promoting silicon transistor has become current technological difficulties urgently to be resolved hurrily.
Invention content
The present invention provides a kind of U-shaped FinFET structure and its manufacturing methods, are carried on the basis of existing FinFET techniques
A kind of new device architecture is gone out, so that the grid length of device is not limited by footprint sizes, efficiently solve short-channel effect
Caused problem.Specifically, the structure includes：
Substrat structure, the substrat structure are SOI substrate；
First fin and the second fin, first, second fin is located above the substrat structure, parallel to each other；
Gate stack, the gate stack cover the side wall of the first, second fin of the substrat structure and part；
Source region, the source region are located at the region that first fin is not covered by gate stack；
Drain region, the drain region are located at the region that second fin is not covered by gate stack；
Side wall, the side wall is located at first, second fin both sides, for source region, drain region and gate stack to be isolated.
Wherein, first, second fin height having the same, thickness and width.
Wherein, the gate stack includes：Boundary layer, high-K dielectric layer, metal gate work function regulating course and polysilicon.
Wherein, the height of the gate stack is the 1/2~3/4 of first, second fin height.
Correspondingly, the present invention also provides a kind of U-shaped FinFET manufacturing methods, including：
A. substrat structure is provided, the substrat structure is SOI substrate；
B. the first fin and the second fin are formed on the substrat structure；
C. gate stack is formed above the substrat structure, first fin and the second fin；
D. the gate stack with partial sidewall, the first He of part of exposing above first fin and the second fin are removed
Second fin forms source-drain area；
E. side wall is formed in the first fin not covered by the gate stack and the second fin both sides.
Wherein, the gate stack includes：Boundary layer, high-K dielectric layer, metal gate work function regulating course and polysilicon.
Wherein, in stepb, it forms first fin and the method for the second fin is：
B1 layer of channel material and source and drain material layer) are sequentially formed on the substrat structure；
B2) layer of channel material and source and drain material layer are performed etching, form the first fin and the second fin.
Wherein, the method for forming first fin and the second fin is anisotropic etching.
Wherein, first fin and the second fin height having the same, thickness and width.
Wherein, the distance between first fin and the second fin are 5~50nm.
Wherein, the gate stack includes：Boundary layer, high-K dielectric layer, metal gate work function regulating course and polysilicon.
Wherein, the height of the gate stack is the 1/2~3/4 of first, second fin height.
Wherein, the method for forming the gate stack is atomic layer deposition.
Wherein, the method for removal part of grid pole lamination etches for anisotropic selective.
Wherein, the method for forming the source-drain area is inclined ion implanting.
Wherein, the method for forming the source-drain area is lateral scattering.
Wherein, not carry out epitaxial growth as seed crystal by the silicon on the surface of side wall covering, source and drain epitaxial region is formed.
The present invention proposes a kind of new U-shaped device architecture on the basis of existing FinFET techniques, and in the prior art
It compares, which makes device have vertical raceway groove, thus in the case of footprint size constancies, device can pass through
Change the height of Fin to adjust grid length, improves short-channel effect.Firstly, since device has U-shaped vertical channel structure, device
Source and drain is suspended from above substrat structure, naturally isolated with substrat structure, so that Punchthrough can not occur for the device, to
With lower subthreshold state slope and leakage current.Secondly as device has U-shaped vertical channel structure, device source and drain mutually flat
It goes and is suspended from above substrat structure, be effectively isolated influence of the device drain terminal electric field to source, thus further improve device
Short-channel effect, make device have smaller DIBL.Again, since device has U-shaped vertical channel structure, device source and drain outstanding
Above substrat structure and in being generally aligned in the same plane, thus convenient for making source and drain contact.Meanwhile the present invention has soi structure, position
In the channel region that substrate area is covered by gate stack have SOI device good characteristic, have good grid-control ability with, gram
The shortcomings that having taken the region grid-control energy force difference in body silicon device.Finally, due to substrat structure channel region is heavily doped in the present invention,
It is completely in the state of unlatching, is not controlled by grid voltage, therefore device has higher operating current.Device proposed by the present invention
Part structure is completely compatible with existing FinFET techniques in manufacture craft, greatly improves device performance.
Description of the drawings
Fig. 1~Figure 10 schematically shows that form U-shaped FinFET according to the method in embodiment in the present invention 1 each
The sectional view in stage；
Figure 11 schematically shows the section that U-shaped FinFET is formed according to the method in embodiment in the present invention 2
Figure.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, the implementation below in conjunction with attached drawing to the present invention
Example is described in detail.
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not construed as limiting the claims.
As shown in Figure 10, the present invention provides a kind of FinFET structures, including：Substrat structure, the substrat structure are SOI
Substrate；First fin and the second fin, first, second fin is located above the substrat structure, parallel to each other；Grid is folded
Layer, the gate stack cover the side wall of the first, second fin of the substrat structure and part；Source region, the source region are located at institute
State the region that the first fin is not covered by gate stack；Drain region, the drain region are located at second fin not by gate stack
The region covered；Side wall, the side wall are located at first, second fin both sides, folded for source region, drain region and grid to be isolated
Layer.
Wherein, the SOI substrate includes top layer substrate 150, oxygen buried layer 101 and support substrate 100.
Wherein, first, second fin height having the same, thickness and width.
Wherein, the gate stack 300 includes：Boundary layer, high-K dielectric layer, metal gate work function regulating course and polycrystalline
Silicon.
Wherein, the height of the gate stack is the 1/2~3/4 of first, second fin height.
The present invention proposes a kind of new U-shaped device architecture on the basis of existing FinFET techniques, and in the prior art
It compares, which makes device have vertical raceway groove, thus in the case of footprint size constancies, device can pass through
Change the height of Fin to adjust grid length, improves short-channel effect.Firstly, since device has U-shaped vertical channel structure, device
Source and drain is suspended from above substrat structure, naturally isolated with substrat structure, so that Punchthrough can not occur for the device, to
With lower subthreshold state slope and leakage current.Secondly as device has U-shaped vertical channel structure, device source and drain mutually flat
It goes and is suspended from above substrat structure, be effectively isolated influence of the device drain terminal electric field to source, thus further improve device
Short-channel effect, make device have smaller DIBL.Again, since device has U-shaped vertical channel structure, device source and drain outstanding
Above substrat structure and in being generally aligned in the same plane, thus convenient for making source and drain contact.Meanwhile the present invention has soi structure, position
In the channel region that substrate area is covered by gate stack have SOI device good characteristic, have good grid-control ability with, gram
The shortcomings that having taken the region grid-control energy force difference in body silicon device.Finally, due to substrat structure channel region is heavily doped in the present invention,
It is completely in the state of unlatching, is not controlled by grid voltage, therefore device has higher operating current.Device proposed by the present invention
Part structure is completely compatible with existing FinFET techniques in manufacture craft, greatly improves device performance.
Hereinafter reference will be made to the drawings is more fully described the invention of this reality.In various figures, identical element is using similar
Reference numeral indicates.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If in order to describe located immediately at another layer, another region above scenario, will use herein " directly
... above " or " ... abut above and therewith " form of presentation.
Many specific details of the present invention, such as the structure of device, material, size, processing work is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.For example, the semi-conducting material of substrat structure and fin can partly be led selected from IV races
Body, such as Si or Ge or Group III-V semiconductor, such as the lamination of GaAs, InP, GaN, SiC or above-mentioned semi-conducting material.
The embodiment of the present invention 1 is described in detail in conjunction with attached drawing first.
Referring to Fig. 1, the support substrate 100 in the present invention is shown.100 material of the support substrate is semi-conducting material,
Can be silicon, germanium, GaAs etc., it is preferred that in the present embodiment, the material of support substrate 100 used is silicon, and thickness is
100~500nm.Next, as shown in Fig. 2, forming oxygen buried layer above the support substrate 100.Specifically, may be used
The method of chemical vapor deposition or atomic layer deposition forms the oxygen buried layer 101, and the thickness of the oxygen buried layer is 20~50nm.Most
Afterwards, top layer substrate 150, that is, effective substrate area when device work are formed above the oxygen buried layer 101；In order to ensure
Film quality, it is preferred that the top layer substrate 150 is formed using the method for atomic layer deposition, thickness is 20~50nm.
For the U-shaped FinFET structure in the present invention, gate structure is divided into two parts, in addition to being located at first,
Except the region covered by gate stack on second fin, covered by gate stack 300 on top layer substrate 150 between fin
The region of lid is also a part for device channel.Since substrat structure thickness is much larger than the thickness of fin, grid is for position
It is relatively weak in the control ability of the channel region on substrat structure, certain restriction is formed to the operating current of device.In order to
Improve such case, we improve the present invention in conjunction with SOI technology, replace body silicon substrate using SOI substrate so that lining
The top layer silicon 150 in bottom region has very thin thickness, can further realize the medium isolation of component in integrated circuit, thoroughly
Eliminate the parasitic latch-up in Bulk CMOS circuit；Simultaneously compared to body silicon device, use SOI substrate can be in the present invention
Leakage current is further decreased, the grid-control ability of device is enhanced, to significantly promote device performance.
Next, as shown in figure 4, on the top layer substrate 150 epitaxial growth layer of channel material 110 and source and drain material successively
The bed of material 120.The layer of channel material 110 is the major part of device channel region after the processing by subsequent technique, can be light
It is doped or undoped；Doping type is depending on the type of device.For N-type device, the doping type of layer of channel material is P
Type, adoptable impurity are the group iii elements such as boron；For P-type device, the doping type of layer of channel material is N-type, can be adopted
Impurity is the group-v elements such as phosphorus, arsenic.In the present embodiment, the channel region formed in subsequent technique has 1e15cm-3
Doping concentration, used doped chemical be boron, the doping by outer delay in situ doping formed, specific processing step and
Prior art is identical, and details are not described herein.
The source and drain material layer 120 is after the processing by subsequent technique, by as the major part of device source-drain area,
Doping concentration is equal with concentration needed for source-drain area；Doping type is depending on the type of device.For N-type device, channel material
The doping type of layer is N-type, and adoptable impurity is the group-v elements such as phosphorus, arsenic；For P-type device, layer of channel material
Doping type is p-type, and adoptable impurity is the group iii elements such as boron.In the present embodiment, the source formed in subsequent technique
Drain region has 1e19cm-3Doping concentration, used doped chemical be arsenic, the doping by outer delay in situ doping formation,
Specific processing step is identical as prior art, and details are not described herein.
The structure after source and drain material layer 120 is formed as shown in figure 4, the thickness of layer of channel material 110 as shown in the figure is H2,
Gate stack heights after being formed equal to device.The thickness of source and drain material layer 120 is H1.
Next, by projection, expose, development, the common process such as etching are to the layer of channel material 110 and source and drain material
Layer 120 performs etching, and forms the first fin 210 and the second fin 220, the lithographic method can be dry etching or dry method/
Wet etching.As shown in figure 5, the height after first fin, 210 and second fin 220 etching is completed is equal to the raceway groove
The thickness H2+H1 of material layer 110 and source and drain material layer 120, wherein the thickness H2 of the layer of channel material 110 is follow-up work
The thickness H1 of the height of the gate stack formed in skill, the source and drain material layer 120 is the source-drain area formed in subsequent technique
Height.
Next, it is folded to form grid above 210 and second fin 220 of the top layer substrate 150 and first fin
Layer 300, identical as existing FinFET techniques, the gate stack 300 includes boundary layer 310, high-K dielectric layer 320, gold successively
Belong to gate work function regulating course 330 and polysilicon 340.
Wherein, the material of the boundary layer 310 is silica, for eliminates the defect on the first, second fin surface with
Interfacial state, it is contemplated that the grid-control ability and other performances of device, the thickness of the boundary layer 310 are generally 0.5~1nm；Institute
State high-K dielectric layer 320 be generally high K dielectric, as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON,
HfTaON、HfTiON、Al2O3、La2O3、ZrO2, one kind or combinations thereof in LaAlO, the thickness of gate dielectric layer can be 1nm-
10nm, such as 3nm, 5nm or 8nm, formed high-K dielectric layer after device architecture it is as shown in Figure 6；The metal gate work function tune
Ganglionic layer 330 may be used the materials such as TiN, TaN and be made, and thickness range is 3nm~15nm, forms metal gate work function regulating course
Device architecture after 330 is as shown in Figure 7.
In order to make gate stack 300 that there are good step coverage characteristics, superior in quality film, above-mentioned formation grid are obtained
The method that the technique of pole lamination is all made of atomic layer deposition is formed.
Next, forming polysilicon 340 on 330 surface of metal gate work function regulating course.First, using chemical vapor
The method of deposit deposits one layer of polysilicon in the device surface, it is made to cover entire 10~50nm of device；Next, to described
Polysilicon layer is planarized, and the flattening method can be chemically mechanical polishing (CMP), make the polysilicon surface height
Unanimously, using the metal gate work function regulating course 330 as the stop-layer of chemically mechanical polishing, make the polysilicon in remaining region with
The metal gate work function regulating course 330 is concordant；Next, being carried out to the polysilicon layer using anisotropic selective etching
Orientation etching, keeps its surface concordant with 120 bottom of source and drain material layer, as shown in Figure 8.
Next, carrying out isotropism selectivity to the gate stack for covering 210 and second fin 220 of the first fin
Etching, removes its part being located above polysilicon layer 340, fin described in exposed portion, as shown in Figure 9.To the fin of exposing
It carries out inclined ion implanting or lateral scattering forms the source-drain area.
Next, form side wall 230 in the fin sidewall of the part of exposing, for by gate stack and source-drain area every
It opens.Side wall 230 can be by silicon nitride, silica, silicon oxynitride, silicon carbide and combinations thereof and/or other suitable material shapes
At.Side wall 230 can have multilayered structure.Side wall can be by including that deposition-etch technique is formed, and thickness range can be
10nm-100nm, such as 30nm, 50nm or 80nm, as shown in Figure 10.
In the embodiment of the present invention 2, as shown in figure 11, optionally, after the formation of side wall 230, not with fin surface
The silicon in the region covered by side wall 230 is that seed crystal carries out epitaxial growth, forms source and drain epitaxial region 240, i.e. raised-SD, such as schemes
Shown in 11.Doping in situ is carried out while epitaxial growth, makes epitaxial region that there is doping concentration identical with source-drain area.
Next, it is same as the prior art, silicide and metal electrode, tool are formed above the source-drain area and grid
Details are not described herein for body technology step.
Although being described in detail about example embodiment and its advantage, it should be understood that do not depart from the present invention spirit and
In the case of protection domain defined in the appended claims, various change, substitutions and modifications can be carried out to these embodiments.It is right
In other examples, those skilled in the art should be readily appreciated that while keeping in the scope of the present invention, technique
The order of step can change.
In addition, the application range of the present invention is not limited to the technique, mechanism, system of the specific embodiment described in specification
It makes, material composition, means, method and step.From the disclosure, will be easy as those skilled in the art
Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or
Step, the knot that wherein they execute the function being substantially the same with the corresponding embodiment of the invention described or acquisition is substantially the same
Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system
It makes, material composition, means, method or step are included in its protection domain.
Claims (17)
1. a kind of U-shaped FinFET structure, including：
Substrat structure, the substrat structure are SOI substrate；
First fin (210) and the second fin (220), first fin (210) and the second fin (220) are located at the substrate
Superstructure, it is parallel to each other；
Gate stack (300), the gate stack cover the substrat structure and the first fin of part (210) and the second fin
(220) side wall；
Source region (410), the source region are located at the region that first fin (210) is not covered by gate stack；
Drain region (420), the drain region are located at the region that second fin (220) is not covered by gate stack；
Side wall (230), the side wall (230) are located at first fin (210) and the second fin (220) both sides, gate stack
(300) top, for source region, drain region and gate stack to be isolated.
2. FinFET structure according to claim 1, which is characterized in that first fin (210) and the second fin
Piece (220) height having the same, thickness and width.
3. FinFET structure according to claim 1, which is characterized in that first fin (210) and the second fin
The distance between piece (220) is 5~50nm.
4. FinFET structure according to claim 1, which is characterized in that the height of the gate stack (300) is
The 1/2~3/4 of first, second fin (the 210,220) height.
5. FinFET structure according to claim 1, which is characterized in that the gate stack (300) includes：Interface
Layer (310), high-K dielectric layer (320), metal gate work function regulating course (330) and polysilicon (340).
6. a kind of U-shaped FinFET manufacturing method, includes the following steps：
A. substrat structure is provided, the substrat structure is SOI substrate；
B. the first fin (210) and the second fin (220) are formed on the substrat structure；
C. gate stack is formed above the substrat structure, first fin (210) and the second fin (220)；
D. the gate stack of partial sidewall on first fin (210) and the second fin (220), the part first of exposing are removed
Source-drain area is formed with the second fin；
E. side wall (230) is formed in the first fin (210) not covered by the gate stack and the second fin (220) both sides.
7. manufacturing method according to claim 6, which is characterized in that the gate stack (300) includes：Boundary layer
(310), high-K dielectric layer (320), metal gate work function regulating course (330) and polysilicon (340).
8. manufacturing method according to claim 6, which is characterized in that in stepb, form first fin (210)
Method with the second fin (220) is：
B1 layer of channel material (110) and source and drain material layer (120)) are sequentially formed on the substrat structure；
B2) layer of channel material (110) and source and drain material layer (120) are performed etching, form the first fin (210) and second
Fin (220).
9. manufacturing method according to claim 6, which is characterized in that form first fin (210) and the second fin
(220) method is anisotropic etching.
10. manufacturing method according to claim 6, which is characterized in that first fin (210) and the second fin
(220) height having the same, thickness and width.
11. manufacturing method according to claim 6, which is characterized in that first fin (210) and the second fin
The distance between (220) it is 5~50nm.
12. manufacturing method according to claim 6, which is characterized in that the height of the gate stack (300) is described the
One, the 1/2~3/4 of the second fin (210,220) height.
13. manufacturing method according to claim 6, which is characterized in that the method for forming the gate stack is atomic layer
Deposit.
14. manufacturing method according to claim 6, which is characterized in that the method for removal part of grid pole lamination is each to different
Property selective etch.
15. manufacturing method according to claim 6, which is characterized in that formed the source-drain area method be it is inclined from
Son injection.
16. manufacturing method according to claim 6, which is characterized in that the method for forming the source-drain area is lateral scattering.
17. manufacturing method according to claim 6, which is characterized in that using the silicon on the surface not covered by side wall as seed crystal
Epitaxial growth is carried out, source and drain epitaxial region is formed.
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| CN102651313A (en) * | 2011-02-25 | 2012-08-29 | 中国科学院微电子研究所 | Preparation for positive channel metal oxide semiconductor (PMOS) apparatus laminating structure and adjustment method for gate power function |
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| CN102651313A (en) * | 2011-02-25 | 2012-08-29 | 中国科学院微电子研究所 | Preparation for positive channel metal oxide semiconductor (PMOS) apparatus laminating structure and adjustment method for gate power function |
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