TW202117933A - 製造半導體裝置的方法及半導體裝置 - Google Patents

製造半導體裝置的方法及半導體裝置 Download PDF

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TW202117933A
TW202117933A TW109137501A TW109137501A TW202117933A TW 202117933 A TW202117933 A TW 202117933A TW 109137501 A TW109137501 A TW 109137501A TW 109137501 A TW109137501 A TW 109137501A TW 202117933 A TW202117933 A TW 202117933A
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layer
gate structure
epitaxial layer
recess
active region
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TW109137501A
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TWI799751B (zh
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陳德安
林孟漢
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例係關於一種製造一半導體裝置之方法，在該方法中，在一基板中形成界定一主動區之一隔離結構；在該隔離結構上方形成一第一閘極結構並在該主動區上方鄰近於該第一閘極結構形成一第二閘極結構；形成一覆蓋層以覆蓋該第一閘極結構及該主動區之在該第一閘極結構與該第二閘極結構之間的一部分；蝕刻在該第一閘極結構與該第二閘極結構之間不由該覆蓋層覆蓋的該主動區以形成一凹部；以及在該凹部中形成一磊晶半導體層。

Description

製造半導體裝置的方法及半導體裝置
本發明實施例係有關製造半導體裝置的方法及半導體裝置。
互補金屬-氧化物-半導體場效電晶體(CMOS FET)已由於其低功率消耗而被利用。然而，在CMOS FET中，防止閂鎖一直為裝置及製程技術中的問題之一。隨著積體電路按比例縮小的增加以及積體電路對速度的要求愈加苛刻，需要更有效的措施來防止汲極誘發障壁降低(drain induced barrier lowering，DIBL)及閂鎖。
本發明的一實施例係關於一種製造一半導體裝置之方法，其包含：在一基板中形成界定一主動區之一隔離結構；在該隔離結構上方形成一第一閘極結構並在該主動區上方鄰近於該第一閘極結構形成一第二閘極結構；形成一覆蓋層以覆蓋該第一閘極結構及該主動區之在該第一閘極結構與該第二閘極結構之間的一部分；蝕刻在該第一閘極結構與該第二閘極結構之間不由該覆蓋層覆蓋的該主動區以形成一凹部；以及在該凹部中形成一磊晶半導體層。
本發明的一實施例係關於一種製造一半導體裝置之方法，其包含：在一基板中形成圍繞一主動區之一隔離結構；在該隔離結構上方形成一第一閘極結構並在該主動區上方形成一第二閘極結構及一第三閘極結構，該等第一、第二及第三閘極結構在一第一方向上延伸並配置於與該第一方向交叉之一第二方向上；形成一覆蓋層以覆蓋在該第一方向上延伸的該主動區之邊緣並覆蓋該隔離結構；蝕刻不由該覆蓋層覆蓋的該主動區以在該隔離結構與該第二閘極結構之間形成一第一凹部並在該第二閘極結構與該第三閘極結構之間形成一第二凹部；以及在該第一凹部中形成一第一磊晶半導體層並在該第二凹部中形成一第二磊晶半導體層。
本發明的一實施例係關於一種半導體裝置，其包含：形成於一基板中並圍繞一主動區之一隔離結構；放置在該主動區上方之一第一閘極結構及一第二閘極結構，及放置在該隔離結構上方之一虛設閘極結構，該等第一、第二及虛設閘極結構在一第一方向上延伸並配置於與該第一方向交叉之一第二方向上；以及放置在該虛設閘極結構與該第一閘極結構之間的一第一源極/汲極磊晶層，及放置在該第一閘極結構與該第二閘極結構之間的一第二源極/汲極磊晶層，其中該第一磊晶層之一體積小於該第二磊晶層之一體積。
應理解，以下揭露內容提供用於實施本揭露之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實施例或實例以簡化本揭露內容。當然，此等組件以及配置僅為實例且不意欲為限制性的。舉例而言，元件的尺寸並不限於所揭露的範圍或值，但可取決於製程條件及/或元件的所要性質。此外，在以下描述中，在第一特徵上方或上形成第二特徵可包含第二特徵與第一特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第二特徵與第一特徵之間形成以使得第二特徵與第一特徵可不直接接觸的實施例。為簡單及清楚起見，各種特徵可按不同比例任意地拉伸。在隨附圖式中，為簡化起見可省略一些層/構件。
另外，為易於描述，可使用諸如「在...下方」、「在...之下」、「下部」、「在...上方」、「上部」及其類似者之空間相對術語，以描述如諸圖中所說明之一個元件或特徵相對於另一元件或特徵的關係。除圖中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用中或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地進行解釋。另外，術語「由…製成」可意謂「包含」或「由…組成」。另外，在以下製造過製程中，在所描述操作中/之間可存在一或多個額外操作，且可改變操作順序。在本揭露中，片語「A、B及C中之至少一者」意謂」意謂A、B、C、A+B、A+C、B+C或A+B+C中的一者，且不意謂來自A之一者、來自B之一者及來自C之一者，除非另有解釋。
所揭露實施例係關於半導體裝置，詳言之，係關於CMOS FET (例如平面場效電晶體、鰭式場效電晶體(fin field effect transistor，FinFET)及環繞式閘極FET)及其製造方法。
應變矽技術已廣泛用於現代Si行業中。自磊晶形成層施加之壓縮或拉伸應變修改半導體層之晶格常數，其可增大載流子遷移率。舉例而言，在源極/汲極磊晶中，在SiGe磊晶層形成於矽源極/汲極處時，p型FET之電洞遷移率可顯著升高，此係因為鍺或矽鍺具有的晶格常數比矽大。SiGe磊晶層將壓縮應力提供至p型FET之矽通道。類似地，SiP或SiCP磊晶層將拉伸應力提供至n型FET之矽通道。
磊晶層常常磊晶形成於在結晶半導體層之下形成的凹部中及其上方。然而，在凹部部分地藉由諸如絕緣層之非結晶材料形成時，磊晶層不完全生長，且磊晶體積與凹部完全藉由結晶半導體形成的情況相比較小。在源極/汲極磊晶層在絕緣層之邊緣處不充分地生長時，壓縮應力不足，其造成較低驅動電流，且可能出現非對稱裝置特性。
在本揭露中，提供用於改良諸如淺溝槽隔離(shallow trench isolation，STI)之隔離結構附近的源極/汲極磊晶層生長之方法及結構。
圖1至圖11展示根據本揭露之實施例的用於半導體裝置之依序製造操作之剖面圖。當然，可在圖1至圖11中所示的製程之前、期間及之後提供額外操作，且針對方法的額外實施例，可更換或去除下文中所描述的操作中的一些。操作/程序製程的次序可為可互換的。
如圖1中所示，諸如STI 30之隔離結構形成於基板10之表面中。基板10可為p型或n型半導體基板。在一些實施例中，基板10由以下製成：適合元素半導體，諸如矽、金剛石或鍺；適合合金或化合物半導體，諸如IV族化合物半導體(矽鍺(SiGe)、碳化矽(SiC)、碳化矽鍺(SiGeC)、GeSn、SiSn、SiGeSn)、III-V族化合物半導體(例如，砷化鎵(GaAs)、砷化銦鎵(InGaAs)、砷化銦(InAs)、磷化銦(InP)、銻化銦(InSb)、磷砷化鎵(GaAsP)或磷化鎵銦(GaInP))或其類似者。另外，基板100可包括磊晶層(epitaxial layer，epi-layer)，其可變形以用於效能增強，和/或可包括絕緣體上矽(silicon-on-insulator；SOI)結構。在一個實施例中，使用p型矽基板。
隔離結構30係藉由用一或多種絕緣材料填充形成於基板10中的溝槽，且接著執行諸如化學機械拋光(chemical mechanical polishing，CMP)製程之平坦化操作而形成。隔離結構30包括藉由低壓化學氣相沈積(low pressure chemical vapor deposition，LPCVD)、電漿CVD或可流動CVD形成的絕緣材料(例如二氧化矽、氮氧化矽及/或氮化矽)之一或多個層。在可流動CVD中，沈積可流動介電材料而非氧化矽。如其名稱表明，可流動介電材料在沈積期間可「流動」以填充具有高縱橫比的間隙或間隙。通常，將各種化學物質添加至含矽前驅物以允許沈積薄膜流動。在一些實施例中，添加有氮氫化物鍵。可流動介電前驅物(特定言之可流動氧化矽前驅物)的實例包括矽酸鹽、矽氧烷、甲基倍半氧矽烷(methyl silsesquioxane；MSQ)、三氧化矽烷(hydrogen silsesquioxane；HSQ)、MSQ/HSQ、全氫矽氮烷(perhydrosilazane；TCPS)、全氫聚矽氮烷(perhydro-polysilazane；PSZ)、正矽酸四乙酯(tetraethyl orthosilicate；TEOS)或甲矽烷基胺，諸如三矽烷基胺(trisilylamine；TSA)。此等可流動氧化矽材料形成於多操作製程中。在沈積可流動薄膜後，其經固化且隨後經退火以移除不需要的元素來形成氧化矽。當移除非所要元素時，可流動薄膜密度增加且收縮。在一些實施例中，進行多個退火製程。多於一次固化且退火可流動薄膜。可流動薄膜可能摻雜有硼及/或磷。在一些實施例中，隔離結構30可由SOG、SiO、SiON、SiOCN及/或摻氟矽酸鹽玻璃(fluorine-doped silicate glass；FSG)的一或多個層形成。隔離結構30界定主動區，其用作FET之通道區及源極/汲極區。在一些實施例中，隔離結構30在平面圖中圍繞主動區。在一些實施例中，如圖1中所示，提供用於p型FET (PMOS)之第一主動區10P及用於n型FET (NMOS)之第二主動區10N。
另外，如圖1中所示，形成犧牲閘極結構40及虛設犧牲閘極結構40D。犧牲閘極結構40放置在主動區10P及10N上方，且虛設犧牲閘極結構40D放置在隔離結構30上方。
在一些實施例中，犧牲閘極結構40中之每一者包括犧牲閘極介電層42、犧牲閘極電極44及硬式遮罩層46。在一些實施例中，虛設犧牲閘極結構40D包括犧牲閘極電極44及硬式遮罩層46。在一些實施例中，犧牲閘極電極係由多晶矽製成，且犧牲閘極介電層係由氧化矽製成。
另外，犧牲閘極結構40及虛設犧牲閘極結構40D中之每一者包括在犧牲閘極電極之對置側面上的閘極側壁間隔件48。閘極側壁間隔件48包括一或多個介電層。在一些實施例中，側壁間隔件係由氧化矽、氮化矽、SiOCN、SiCN、氧化鋁、AlCO或AlCN中之一或多者或任何其他合適介電材料製成。
在一些實施例中，犧牲閘極結構40及虛設犧牲閘極結構40D在Y方向上延伸，且在X方向上以恆定間距P1配置。接下來，如圖2中所示，覆蓋層50形成於犧牲閘極結構40、虛設犧牲閘極結構40D、主動區及隔離結構30上方。在一些實施例中，覆蓋層50由不同於閘極側壁間隔件48之材料製成。在一些實施例中，覆蓋層50由不同於硬式遮罩層46之材料製成。在一些實施例中，覆蓋層係由氧化矽、氮化矽、SiOCN、SiCN、氧化鋁、AlCO或AlCN中之一或多者或任何其他合適介電材料製成。覆蓋層50可經由諸如化學氣相沈積(chemical vapor deposition，CVD)、物理氣相沈積(physical vapor deposition，PVD)及原子層沈積(atomic layer deposition，ALD)之一或多個製程形成，但可利用任何可接受的製程。在一些實施例中，取決於半導體裝置之設計規則，覆蓋層50之厚度在約4 nm至約10 nm之範圍內。在其他實施例中，覆蓋層50之厚度在約5 nm至約8 nm之範圍內。
覆蓋層50毯覆式形成於整個結構上方，且藉由一或多個微影及蝕刻操作而圖案化，如圖2中所示。藉由圖案化操作，暴露用於p型FET之第一主動區10P，惟隔離結構附近之邊緣部分除外。如圖3中所示，覆蓋層50覆蓋第一主動區10P之邊緣部分及隔離結構30之一部分。取決於半導體裝置之設計規則，在第一主動區10P上方自隔離結構30之邊緣至覆蓋層50之邊緣的距離X1在一些實施例中在10 nm至30 nm之範圍內，且在其他實施例中在約15 nm至約25 nm之範圍內。如圖3中所示，第一主動區10P之在隔離結構30與鄰近犧牲閘極結構40之間的區在X方向上具有寬度X2，其小於在兩個鄰近犧牲閘極結構40之間的空間S1。在一些實施例中，取決於半導體裝置之設計規則，比率X1/X2在約0.2至約0.3之範圍內。若X1/X2過小，將不能獲得如下文所解釋的本發明實施例之效果，且若X1/X2過大，隨後形成的磊晶層之大小將不足。
接著，如圖4中所示，藉由使用合適蝕刻操作蝕刻(凹陷)第一主動區10P之不由犧牲閘極結構40及覆蓋層50覆蓋的源極/汲極區以形成凹部12。由於主動區10P之一部分由覆蓋層50覆蓋，因此凹部12A之開口大小小於凹部12B之開口大小。因此，如圖4中所示，鄰近於隔離結構30之凹部12A的大小小於形成於犧牲閘極結構40之間的凹部12B。在一些實施例中，凹部12A之深度D1為凹部12B之深度D2的約80%至約95%，且在其他實施例中為深度D2之約85%至約90%。在一些實施例中，凹部12A之最大寬度W1為凹部12B之最大寬度W2的約40%至約65%，且在其他實施例中為最大寬度W2的約50%至約60%。
在形成凹部之後，源極/汲極磊晶層60形成於凹部中，如圖5中所示。在一些實施例中，源極/汲極磊晶層60包括SiGe層。在一些實施例中，SiGe層摻雜有B。在一些實施例中，源極/汲極磊晶層60包括具有不同Ge含量之多個SiGe層。在某些實施例中，源極/汲極磊晶層60包括Ge層。
如圖5中所示，形成於隔離結構30與鄰近犧牲閘極結構40之間的源極/汲極磊晶層60A的體積小於形成於鄰近犧牲閘極結構40之間的源極/汲極磊晶層60B。在一些實施例中，源極/汲極磊晶層60A之深度D3為源極/汲極磊晶層60B之深度D4的約80%至約95%，且在其他實施例中為深度D4的約85%至約90%。在一些實施例中，源極/汲極磊晶層60A之最大寬度W1為源極/汲極磊晶層60B之最大寬度W2的約40%至約65%，且在其他實施例中為最大寬度W2的約50%至約60%。
在形成源極/汲極磊晶層60之後，移除覆蓋層50，如圖6中所示。
在形成用於p型FET之源極/汲極磊晶層60之後，形成用於n型FET之源極/汲極磊晶層。與對於如上文所闡述的形成用於p型FET的源極/汲極磊晶層60所解釋的相同或類似的材料、組態、尺寸、結構、條件及操作可用於形成用於n型FET的源極/汲極磊晶層，且可省略該等解釋中的一些。
如圖7中所示，覆蓋層55形成於犧牲閘極結構40、虛設犧牲閘極結構40D、用於p型FET之第一主動區及隔離結構30上方。在一些實施例中，覆蓋層55之組態為與如上文所闡述的覆蓋層50之組態相同或類似的材料。如圖7中所示，覆蓋層55包括開口，其中暴露用於n型FET之第二主動區10N，惟隔離結構附近之邊緣部分除外。如圖7中所示，覆蓋層55覆蓋第二主動區10N之邊緣部分及隔離結構30之一部分。
接著，類似於圖4，藉由使用合適蝕刻操作蝕刻(凹陷)第二主動區10N之不由犧牲閘極結構40及覆蓋層55覆蓋的源極/汲極區以形成凹部14，如圖8中所示。
另外，在形成凹部14之後，源極/汲極磊晶層65形成於凹部中，如圖9中所示。在一些實施例中，源極/汲極磊晶層50包括SiP、SiCP及SiC層中之一或多者。在一些實施例中，SiP或SiCP層進一步包括As。在一些實施例中，形成具有不同P含量之多個磊晶層。在形成磊晶層65之後，移除覆蓋層65。
在一些實施例中，在形成用於n型FET之源極/汲極磊晶層65之後，形成用於p型FET之源極/汲極磊晶層60。
隨後，執行更換閘極操作以形成金屬閘極結構。如圖10中所示，蝕刻終止層70形成於犧牲閘極結構40、40D及源極/汲極磊晶層60、65上方，且接著一或多個層間介電(interlayer dielectric，ILD)層75形成於蝕刻終止層70上方。在一些實施例中，蝕刻終止層70包括氮化矽。
在形成ILD層75之後，執行諸如回蝕製程及/或化學機械拋光(chemical mechanical polishing，CMP)製程之平坦化操作以暴露犧牲閘極電極層44之上表面。接著，移除犧牲閘極電極層44及犧牲閘極介電層42，藉此形成閘極空間。接著，包括界面層之閘極介電層82及高k閘極介電層形成於閘極空間中的通道區上。在一些實施例中，界面層為化學形成之氧化矽。高k閘極介電層包括HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、三氧化鈦、二氧化鉿-氧化鋁(HfO2 -Al2 O3 )合金或任何其他合適高k介電材料之一或多個層。
另外，一或多個導電層形成於閘極介電層82上方。導電層可包括藉由TaN、TiN、摻雜有Si之TiN或任何其他合適導電材料之一或多個層形成的障壁層。導電層進一步包括一或多個功函數調整層。功函數調整層係由諸如以下之導電材料製成：TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC之單層，或此等材料中之兩者或更多者之多層。使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi中之一或多者作為用於n通道FinFET之功函數調整層85，且使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中之一或多者作為用於p通道FinFET之功函數調整層84。
導電層進一步包括主金屬層86，其包括選自由以下組成的群組之金屬材料：W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Co、Pd、Ni、Re、Ir、Ru、Pt及Zr。用於虛設犧牲閘極結構40D之金屬閘極結構包括n型金屬閘極結構及/或p型金屬閘極結構。
在形成金屬閘極電極之後，執行進一步CMOS製程以形成各種特徵，諸如額外層間介電層、接點/通路、互連金屬層及鈍化層，等。
圖12至圖18展示根據本揭露之實施例的半導體裝置製造過程之各個階段的平面圖。與對於圖1至圖11解釋的相同或類似之材料、組態、尺寸、結構、條件及操作可用於以下實施例中，且可省略該等解釋中的一些。
圖12展示形成犧牲閘極結構40、40D之後的平面圖。如圖12中所示，第一主動區10P由隔離結構30圍繞，且具有豎直邊緣(在Y方向上延伸)及水平邊緣(在X方向上延伸)。圖13展示形成覆蓋層50之後的平面圖。如圖13中所示，覆蓋層50覆蓋第一主動區10P之豎直邊緣(及對應拐角)，而不覆蓋水平邊緣(惟拐角除外)。圖14展示形成源極/汲極磊晶層60之後的平面圖。如圖14中所示，薄主動區10P'在X方向上保持在源極/汲極磊晶層60與隔離結構之間。
圖15展示根據另一實施例的在形成覆蓋層50之後的平面圖。如圖15中所示，覆蓋層50覆蓋第一主動區10P之豎直邊緣及水平邊緣。因此，如圖16中所示，源極/汲極磊晶層60在X方向及Y方向上與隔離結構完全分離。
在圖1至圖16中，用於p型FET之第一主動區10P及用於n型FET之第二主動區10N在X方向上並排配置。在圖17及圖18中，用於p型FET之第一主動區10P及用於n型FET之第二主動區10N配置於犧牲閘極結構所延伸的Y方向上。
圖17展示形成覆蓋層50之後的平面圖，且圖18展示形成覆蓋層55之後的平面圖。類似於圖13，僅主動區之豎直邊緣由覆蓋層50、55覆蓋。
圖19A、圖19B、圖19C及圖19D說明根據本揭露之實施例的源極/汲極磊晶層之剖面圖。源極/汲極磊晶層60、65之剖面形狀取決於用於形成凹部12、14之蝕刻條件及/或其他因素而改變。在一些實施例中，如圖19A中所示，源極/汲極磊晶層之剖面具有菱形形狀。在一些實施例中，如圖19B中所示，源極/汲極磊晶層之剖面具有V形。在一些實施例中，如圖19C中所示，源極/汲極磊晶層之剖面具有U形。在一些實施例中，如圖19D中所示，源極/汲極磊晶層之剖面具有半圓或圓形形狀。
圖20至圖28展示根據本揭露之實施例的FinFET裝置製造過程之各個階段的剖面圖。與對於圖1至圖19D解釋的相同或類似之材料、組態、尺寸、結構、條件及操作可用於以下實施例中，且可省略該等解釋中的一些。
圖20為犧牲閘極結構40形成於鰭片結構20上方之後的平面圖。鰭片結構20可藉由任何合適方法圖案化。舉例而言，鰭片結構可使用一或多個光微影製程，包括雙重圖案化或多重圖案化製程經圖案化。一般而言，雙重圖案化製程或多重圖案化製程組合光微影製程與自對準製程，從而允許產生具有例如小於原本可使用單個、直接光微影製程獲得的圖案之間距的圖案。舉例而言，在一個實施例中，犧牲層形成於基底上方且使用微影製程經圖案化。間隔件使用自對準製程在經圖案化犧牲層旁邊形成。接著移除犧牲層，且可接著使用保持間隔件或心軸來圖案化鰭片結構。在一些實施例中，一或多個虛設鰭片結構鄰近於主動FinFET之鰭片結構20而形成。
在形成鰭片結構20之後，隔離絕緣層32 (例如，STI)放置在鰭片結構20及基板10上方(見圖21)。在一些實施例中，在形成隔離絕緣層32之前，一或多個襯墊層形成於基板10及鰭片結構20之底部部分的側壁上方。可經由諸如物理氣相沈積(PVD)、化學氣相沈積(CVD)或原子層沈積(ALD)之一或多個製程沈積襯墊層，但可利用任何可接受的製程。隔離絕緣層32包括藉由低壓化學氣相沈積(LPCVD)、電漿CVD或可流動CVD形成的絕緣材料(例如二氧化矽、氮氧化矽及/或氮化矽)之一或多個層。在一些實施例中，隔離絕緣層32可由SOG、SiO、SiON、SiOCN及/或摻氟矽酸鹽玻璃(FSG)的一或多個層形成。
在於鰭片結構20上方形成隔離絕緣層32之後，執行平坦化操作以便移除隔離絕緣層32及用以圖案化鰭片結構的遮罩層(例如，襯墊氧化物層及氮化矽遮罩層)之部分。平坦化操作可包括化學機械拋光(CMP)及/或回蝕製程。隨後，使用例如蝕刻製程、化學機械拋光(CMP)等移除隔離絕緣層32之在鰭片結構20之頂表面上方延伸的部分及襯墊層之在鰭片結構20之頂表面上方的部分。另外，使隔離絕緣層32凹陷以暴露鰭片結構20之上部部分。在一些實施例中，使用單一蝕刻製程或多個蝕刻製程使隔離絕緣層32凹陷。在隔離絕緣層32係由氧化矽製成的一些實施例中，蝕刻製程可例如為乾式蝕刻、化學蝕刻或濕式清潔製程。在某些實施例中，可使用濕式蝕刻製程，例如藉由將基板浸漬在氫氟酸(hydrofluoric acid，HF)中，來執行隔離絕緣層32之部分移除。在另一實施例中，可使用乾式蝕刻製程執行隔離絕緣層32之部分移除。舉例而言，可使用將CHF3 或BF3 用作蝕刻氣體之乾式蝕刻製程。在形成隔離絕緣層32之後，可執行例如退火製程之熱製程以改良隔離絕緣層32之品質。在某些實施例中，使用快速熱退火(rapid thermal annealing，RTA)在範圍約900℃至約1050℃的溫度下在惰性氣體環境(諸如N2 、Ar或He環境)中執行熱製程約1.5秒至約10秒。
在形成鰭片結構20及隔離絕緣層32之後，形成犧牲閘極結構40，如圖20中所示。犧牲閘極結構40中之每一者包括犧牲閘極介電層、犧牲閘極電極層、硬式遮罩層及閘極側壁間隔件。儘管圖20展示兩個鰭片結構20及兩個犧牲閘極結構40，但數目不限於兩個。
在形成犧牲閘極結構40之後，形成覆蓋層52以覆蓋鰭片結構20之邊緣部分，如圖21中所示。取決於半導體裝置之設計規則，覆蓋層52在鰭片結構20之頂部上方延伸的距離量X11在一些實施例中在10 nm至30 nm之範圍內，且在其他實施例中在約15 nm至約25 nm之範圍內。在形成覆蓋層52之後，蝕刻(凹陷)不由覆蓋層52及犧牲閘極結構40覆蓋的鰭片結構20以形成源極/汲極空間，且源極/汲極磊晶層60形成於該源極/汲極空間中，如圖22中所示。
形成於鰭片結構20之邊緣附近的源極/汲極磊晶層60A在體積上比形成於鄰近犧牲閘極結構40之間的源極/汲極磊晶層60B小。在一些實施例中，源極/汲極磊晶層60A之深度為源極/汲極磊晶層60B之深度的約80%至約95%，且在其他實施例中為源極/汲極磊晶層60B之深度的約85%至約90%。在一些實施例中，源極/汲極磊晶層60A之最大寬度為源極/汲極磊晶層60B之最大寬度的約40%至約65%，且在其他實施例中為源極/汲極磊晶層60B之最大寬度的約50%至約60%。
圖23為犧牲閘極結構40及虛設犧牲閘極結構40D形成於鰭片結構20上方之後的平面圖。如圖25中所示，虛設犧牲閘極結構40D並不覆蓋鰭片結構20之邊緣。類似於圖21，形成覆蓋層52以覆蓋鰭片結構20之邊緣部分，如圖24中所示。類似於圖22，形成源極/汲極磊晶層60，如圖25中所示。圖25之源極/汲極磊晶層60之組態與圖22之源極/汲極磊晶層60之組態實質上相同。
圖26為犧牲閘極結構40及虛設犧牲閘極結構40D形成於鰭片結構20上方之後的平面圖。如圖26中所示，虛設犧牲閘極結構40D分別覆蓋鰭片結構20之邊緣。如圖27中所示，形成覆蓋層52以使得覆蓋層之邊緣位於虛設犧牲閘極結構40D上，且接著形成源極/汲極磊晶層60，如圖28中所示。在此實施例中，三個源極/汲極磊晶層之大小實質上彼此相等。
圖29展示根據一實施例的在形成金屬閘極結構之後的FinFET。如圖29中所示，鰭片結構包含放置在底部鰭片結構23上方之通道鰭片結構20B及邊緣鰭片結構20A。金屬閘極結構放置在通道鰭片結構20B上方。源極/汲極磊晶層60A放置在通道鰭片結構20B與邊緣鰭片結構20A之間，且源極/汲極磊晶層60B放置在通道鰭片結構20B之間。在一些實施例中，邊緣鰭片結構20A之寬度W11在5 nm至30 nm之範圍內。在一些實施例中，邊緣鰭片結構20A之寬度W11小於通道鰭片結構20B之寬度W12。
圖30至圖34展示根據本揭露之實施例的GAA FET裝置製造過程之各個階段的剖面圖。與對於圖1至圖29解釋的相同或類似之材料、組態、尺寸、結構、條件及操作可用於以下實施例中，且可省略該等解釋中的一些。
圖30為犧牲閘極結構40形成於鰭片結構21上方之後的平面圖且圖31為犧牲閘極結構40形成於鰭片結構21上方之後的剖面圖。鰭片結構21包含交替地堆疊於鰭片底部結構23上方之第一半導體層25及第二半導體層22，如圖31中所示。在一些實施例中，第一半導體層25由SiGe製成且第二半導體層22由Si製成。
如圖32中所示，形成覆蓋層52以覆蓋鰭片結構之邊緣部分，且蝕刻(凹陷)不由覆蓋層52及犧牲閘極結構40覆蓋的鰭片結構以形成源極/汲極空間，如圖32中所示。接著，如圖33中所示，將源極/汲極磊晶層60形成於該源極/汲極空間中。
另外，用金屬閘極結構更換犧牲閘極結構40。在形成ILD層75之後，執行CMP操作以暴露犧牲閘極電極層。接著移除犧牲閘極電極層及犧牲閘極介電層，藉此暴露鰭片結構。當犧牲閘極電極層為多晶矽時，可使用諸如TMAH溶液之濕式蝕刻劑來選擇性地移除犧牲閘極電極層。此後使用電漿乾式蝕刻及/或濕式蝕刻來移除犧牲閘極介電層。
接著，藉由使用例如濕式蝕刻操作自通道區移除第一半導體層25。在一些實施例中，可使用濕式蝕刻劑選擇性地移除第一半導體層25，該濕式蝕刻劑係諸如但不限於氫氧化銨(NH4 OH)、四甲基銨氫氧化物(TMAH)、乙二胺鄰苯二酚(EDP)、氫氧化鉀(KOH)溶液、氫氯酸(HCl)溶液或熱氨溶液。亦可使用電漿乾式蝕刻或化學氣相蝕刻。
在通道區中釋放第二半導體層22之奈米線之後，形成金屬閘極結構。該等金屬閘極結構包含如上文所闡述之高k閘極介電層82、一或多個功函數調整材料層84及本體閘極電極層86，如圖34中所示。
如圖34中所示，鰭片結構包含放置在底部鰭片結構23上方之邊緣鰭片結構21A。邊緣鰭片結構21A包含交替地堆疊之第一半導體25及第二半導體層22。在一些實施例中，邊緣鰭片結構21A之寬度W21在5 nm至30 nm之範圍內。在一些實施例中，邊緣鰭片結構20A之寬度W21小於通道半導體線22之寬度W22。
在本發明實施例中，在源極/汲極區中的主動區或鰭片結構之凹部蝕刻中，調整覆蓋層以將結晶半導體(例如，Si)之一部分保持於凹部之面對隔離結構的側面處。因此，磊晶層可沿Si邊界生長並形成對稱且均一的磊晶剖面。另外，因為可獲得較大磊晶層，所以有可能達成較高驅動電流。另外，有可能達成較低漏電流，且改良DIBL性質。
應理解，本文中未必已論述所有優點，沒有特定優點對於所有實施例或實例為所需的，且其他實施例或實例可提供不同優點。
根據本揭露之一態樣，在一種用於製造半導體裝置之方法中，在基板中形成界定主動區之隔離結構，在隔離結構上方形成第一閘極結構並在主動區上方鄰近於第一閘極結構形成第二閘極結構，形成覆蓋層以覆蓋第一閘極結構及主動區之在第一閘極結構與第二閘極結構之間的部分，蝕刻在第一閘極結構與第二閘極結構之間不由覆蓋層覆蓋的主動區以形成凹部，且在凹部中形成磊晶半導體層。在前述及以下實施例中之一或多者中，第一閘極結構及第二閘極結構在第一方向上延伸並配置於與第一方向交叉之第二方向上，且磊晶層沿第二方向不觸碰隔離結構。在前述及以下實施例中之一或多者中，磊晶層不觸碰隔離結構。在前述及以下實施例中之一或多者中，第一閘極結構及第二閘極結構中之每一者包含多晶矽層、放置在多晶矽層上方之硬式遮罩層以及側壁間隔件，且覆蓋層由與硬式遮罩層及側壁間隔件不同的材料製成。在前述及以下實施例中之一或多者中，在成形磊晶半導體層之後，移除覆蓋層。在前述及以下實施例中之一或多者中，自隔離結構之邊緣至主動區上方之覆蓋層之邊緣的距離在10 nm至30 nm之範圍內。
根據本揭露之另一態樣，在一種製造半導體裝置之方法中，在基板中形成圍繞主動區之隔離結構，且在隔離結構上方形成第一閘極結構並在主動區上方形成第二閘極結構及第三閘極結構。第一、第二及第三閘極結構在第一方向上延伸並配置於與第一方向交叉之第二方向上。形成覆蓋層以覆蓋在第一方向上延伸的主動區之邊緣並覆蓋隔離結構。蝕刻不由覆蓋層覆蓋的主動區以在隔離結構與第二閘極結構之間形成第一凹部並在第二閘極結構與第三閘極結構之間形成第二凹部，且在第一凹部中形成第一磊晶半導體層並在第二凹部中形成第二磊晶半導體層。在前述及以下實施例中之一或多者中，第一磊晶層之體積小於第二磊晶層之體積。在前述及以下實施例中之一或多者中，第一凹部之深度小於第二凹部之深度。在前述及以下實施例中之一或多者中，第一凹部沿第二方向之最大寬度小於第二凹部沿第二方向之最大寬度。在前述及以下實施例中之一或多者中，覆蓋層不覆蓋在第二方向上延伸的主動區之邊緣。在前述及以下實施例中之一或多者中，第一磊晶層在第二方向上不觸碰隔離結構。在前述及以下實施例中之一或多者中，第一磊晶層及第二磊晶層在第一方向上觸碰隔離結構。在前述及以下實施例中之一或多者中，覆蓋層覆蓋在第二方向上延伸的主動區之邊緣。在前述及以下實施例中之一或多者中，第一磊晶層不觸碰隔離結構。在前述及以下實施例中之一或多者中，第一、第二及第三閘極結構中之每一者包含多晶矽層、放置在多晶矽層上方之硬式遮罩層以及側壁間隔件，且覆蓋層由與硬式遮罩層及側壁間隔件不同的材料製成。在前述及以下實施例中之一或多者中，在形成第一及第二磊晶半導體層之後，移除覆蓋層。
根據本揭露之另一態樣，在一種製造半導體裝置之方法中，形成在基板上方自隔離結構突起之鰭片結構，且在鰭片結構上方形成第一閘極結構，形成覆蓋層以覆蓋鰭片結構及隔離結構之邊緣部分，蝕刻不由第一閘極結構及覆蓋層覆蓋之鰭片結構以形成凹部，且在凹部中形成磊晶半導體層。在前述及以下實施例中之一或多者中，閘極結構包含多晶矽層、放置在多晶矽層上方之硬式遮罩層以及側壁間隔件，且覆蓋層由與硬式遮罩層及側壁間隔件不同的材料製成。在前述及以下實施例中之一或多者中，鰭片結構包含交替地堆疊於鰭片底部結構上方之第一半導體層及第二半導體層。在前述及以下實施例中之一或多者中，覆蓋層覆蓋邊緣部分，其中與鰭片結構之邊緣相隔的量為15 nm至25 nm。
根據本揭露之一個態樣，一種半導體裝置包含：形成於基板中並圍繞主動區之隔離結構；放置在主動區上方之第一閘極結構及第二閘極結構，及放置在隔離結構上方之虛設閘極結構；以及放置在虛設閘極結構與第一閘極結構之間的第一源極/汲極磊晶層，及放置在第一閘極結構與第二閘極結構之間的第二源極/汲極磊晶層。第一、第二及虛設閘極結構在第一方向上延伸並配置於與第一方向交叉之第二方向上。第一磊晶層之體積小於第二磊晶層之體積。在前述及以下實施例中之一或多者中，第一磊晶層之深度小於第二磊晶層之深度。在前述及以下實施例中之一或多者中，第一磊晶層沿第二方向之最大寬度小於第二磊晶層沿第二方向之最大寬度。在前述及以下實施例中之一或多者中，第一磊晶層在第二方向上不觸碰隔離結構。在前述及以下實施例中之一或多者中，第一磊晶層及第二磊晶層在第一方向上觸碰隔離結構。在前述及以下實施例中之一或多者中，第一磊晶層不觸碰隔離結構。在前述及以下實施例中之一或多者中，第一磊晶層與隔離結構在第二方向上被基板之一部分分離，且基板之該部分在第二方向上之寬度在15 nm至25 nm之範圍內。
根據本揭露之另一態樣，一種半導體裝置包含鰭片結構，其形成於基板上方而自隔離結構突起。鰭片結構包含放置在底部鰭片結構上方之第一通道鰭片結構及第一邊緣鰭片結構。半導體裝置進一步包含放置在第一通道鰭片結構上方之第一閘極結構，及放置在第一閘極結構與第一邊緣鰭片結構之間的第一源極/汲極磊晶層。在前述及以下實施例中之一或多者中，第一邊緣鰭片結構之寬度在5 nm至30 nm之範圍內。在前述及以下實施例中之一或多者中，第一邊緣鰭片結構之寬度小於第一通道鰭片結構之寬度。在前述及以下實施例中之一或多者中，鰭片結構進一步包含放置在鰭片底部結構上方之第二通道鰭片結構。半導體裝置進一步包含放置在第二通道鰭片結構上方之第二閘極結構，及放置在第一閘極結構與第二閘極結構之間的第二源極/汲極磊晶層。在前述及以下實施例中之一或多者中，第一源極/汲極磊晶層之體積小於第二源極/汲極磊晶層之體積。在前述及以下實施例中之一或多者中，第一源極/汲極磊晶層之深度小於第二源極/汲極磊晶層之深度。在前述及以下實施例中之一或多者中，第一源極/汲極磊晶層之最大寬度小於第二源極/汲極磊晶層之最大寬度。
根據本揭露之另一態樣，一種半導體裝置包含：第一半導體線，其放置在基板上方並豎直地配置於基板上方；第一閘極結構，其包繞第一半導體線；末端鰭片結構，其放置在基板上方；及第一源極/汲極磊晶層，其放置在第一半導體線與第一閘極結構之間；及第一邊緣鰭片結構。在前述及以下實施例中之一或多者中，邊緣鰭片結構之寬度在5 nm至30 nm之範圍內。在前述及以下實施例中之一或多者中，半導體裝置進一步包含：第二半導體線，其放置在基板上方並豎直地配置於基板上方；第二閘極結構，其包繞第二半導體線；及第二源極/汲極磊晶層，其放置在第一閘極結構與第一半導體線之間，及第二閘極結構與第二半導體線之間。在前述及以下實施例中之一或多者中，第一源極/汲極磊晶層之體積小於第二源極/汲極磊晶層之體積。在前述及以下實施例中之一或多者中，第一源極/汲極磊晶層之最大寬度小於第二源極/汲極磊晶層之最大寬度。在前述及以下實施例中之一或多者中，邊緣鰭片結構包含交替地堆疊之第一半導體層及第二半導體層。
前文概述若干實施例的特徵使得熟習此項技術者可更佳地理解本揭露的態樣。熟習此項技術者應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例或實例的相同目的及/或達成相同優點的其他程序及結構的基礎。所屬領域的技術人員亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域的技術人員可在不脫離本揭露的精神及範疇的情況下在本文中進行作出改變、替代及更改。
10:基板 10N:第二主動區 10P:第一主動區 10P':薄主動區 12:凹部 12A:凹部 12B:凹部 14:凹部 20:鰭片結構 20A:邊緣鰭片結構 20B:通道鰭片結構 21:鰭片結構 21A:邊緣鰭片結構 22:第二半導體層 23:鰭片底部結構 25:第一半導體層 30:隔離結構 32:隔離絕緣層 40:犧牲閘極結構 40D:虛設犧牲閘極結構 42:犧牲閘極介電層 44:犧牲閘極電極 46:硬式遮罩層 48:閘極側壁間隔件 50:覆蓋層 52:覆蓋層 55:覆蓋層 60:源極/汲極磊晶層 60A:源極/汲極磊晶層 60B:源極/汲極磊晶層 65:源極/汲極磊晶層 70:蝕刻終止層 75:層間介電層 82:閘極介電層 84:功函數調整層 85:功函數調整層 86:主金屬層 D1:深度 D2:深度 D3:深度 D4:深度 P1:恆定間距 S1:空間 W1:最大寬度 W2:最大寬度 W11:寬度 W12:寬度 W21:寬度 W22:寬度 X1:距離 X2:寬度 X11:距離量
當結合隨附圖式閱讀以下詳細描述時，將最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。
圖1說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖2說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖3說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖4說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖5說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖6說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖7說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖8說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖9說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖10說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖11說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖12說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖13說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖14說明根據本揭露之實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖15說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖16說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖17說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖18說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖19A、圖19B、圖19C及圖19D說明根據本揭露之實施例的源極/汲極磊晶層之剖面圖。
圖20說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖21說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖22說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖23說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖24說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖25說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖26說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖27說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖28說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖29說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖30說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之平面圖。
圖31說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖32說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖33說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
圖34說明根據本揭露之另一實施例的半導體裝置製造過程之各個階段中的一者之剖面圖。
10:基板
30:隔離結構
42:犧牲閘極介電層
44:犧牲閘極電極
46:硬式遮罩層
48:閘極側壁間隔件
50:覆蓋層
60:源極/汲極磊晶層
60A:源極/汲極磊晶層
60B:源極/汲極磊晶層
D3:深度
D4:深度
W1:最大寬度
W2:最大寬度

Claims (20)

  1. 一種製造一半導體裝置之方法，其包含： 在一基板中形成界定一主動區之一隔離結構； 在該隔離結構上方形成一第一閘極結構並在該主動區上方鄰近於該第一閘極結構形成一第二閘極結構； 形成一覆蓋層以覆蓋該第一閘極結構及該主動區之在該第一閘極結構與該第二閘極結構之間的一部分； 蝕刻在該第一閘極結構與該第二閘極結構之間不由該覆蓋層覆蓋的該主動區以形成一凹部；以及 在該凹部中形成一磊晶半導體層。
  2. 如請求項1之方法，其中： 該第一閘極結構及該第二閘極結構在一第一方向上延伸並配置於與該第一方向交叉之一第二方向上，且 該磊晶層沿該第二方向不觸碰該隔離結構。
  3. 如請求項1之方法，其中該磊晶層不觸碰該隔離結構。
  4. 如請求項1之方法，其中： 該第一閘極結構及該第二閘極結構中之每一者包含一多晶矽層、放置在該多晶矽層上方之一硬式遮罩層以及側壁間隔件，且 該覆蓋層由與該硬式遮罩層及該等側壁間隔件不同的一材料製成。
  5. 如請求項1之方法，其進一步包含：在形成該磊晶半導體層之後，移除該覆蓋層。
  6. 如請求項1之方法，其中自該隔離結構之一邊緣至該主動區上方之該覆蓋層之一邊緣的一距離在10 nm至30 nm之一範圍內。
  7. 一種製造一半導體裝置之方法，其包含： 在一基板中形成圍繞一主動區之一隔離結構； 在該隔離結構上方形成一第一閘極結構並在該主動區上方形成一第二閘極結構及一第三閘極結構，該等第一、第二及第三閘極結構在一第一方向上延伸並配置於與該第一方向交叉之一第二方向上； 形成一覆蓋層以覆蓋在該第一方向上延伸的該主動區之邊緣並覆蓋該隔離結構； 蝕刻不由該覆蓋層覆蓋的該主動區以在該隔離結構與該第二閘極結構之間形成一第一凹部並在該第二閘極結構與該第三閘極結構之間形成一第二凹部；以及 在該第一凹部中形成一第一磊晶半導體層並在該第二凹部中形成一第二磊晶半導體層。
  8. 如請求項7之方法，其中該第一磊晶層之一體積小於該第二磊晶層之一體積。
  9. 如請求項7之方法，其中該第一凹部之一深度小於該第二凹部之一深度。
  10. 如請求項7之方法，其中該第一凹部沿該第二方向之一最大寬度小於該第二凹部沿該第二方向之一最大寬度。
  11. 如請求項7之方法，其中該覆蓋層不覆蓋在該第二方向上延伸的該主動區之邊緣。
  12. 如請求項11之方法，其中該第一磊晶層在該第二方向上不觸碰該隔離結構。
  13. 如請求項12之方法，其中該第一磊晶層及該第二磊晶層在該第一方向上觸碰該隔離結構。
  14. 如請求項7之方法，其中該覆蓋層覆蓋在該第二方向上延伸的該主動區之邊緣。
  15. 如請求項14之方法，其中該第一磊晶層不觸碰該隔離結構。
  16. 如請求項7之方法，其中： 第一、第二及第三閘極結構中之每一者包含一多晶矽層、放置在該多晶矽層上方之一硬式遮罩層以及側壁間隔件，且 該覆蓋層由與該硬式遮罩層及該等側壁間隔件不同的一材料製成。
  17. 一種半導體裝置，其包含： 形成於一基板中並圍繞一主動區之一隔離結構； 放置在該主動區上方之一第一閘極結構及一第二閘極結構，及放置在該隔離結構上方之一虛設閘極結構，該等第一、第二及虛設閘極結構在一第一方向上延伸並配置於與該第一方向交叉之一第二方向上；以及 放置在該虛設閘極結構與該第一閘極結構之間的一第一源極/汲極磊晶層，及放置在該第一閘極結構與該第二閘極結構之間的一第二源極/汲極磊晶層， 其中該第一磊晶層之一體積小於該第二磊晶層之一體積。
  18. 如請求項17之半導體裝置，其中該第一磊晶層之一深度小於該第二磊晶層之一深度。
  19. 如請求項17之半導體裝置，其中該第一磊晶層沿該第二方向之一最大寬度小於該第二磊晶層沿該第二方向之一最大寬度。
  20. 如請求項17之半導體裝置，其中該第一磊晶層在該第二方向上不觸碰該隔離結構。
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