WO2016037397A1 - 一种FinFET器件结构及其制造方法 - Google Patents

一种FinFET器件结构及其制造方法 Download PDF

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WO2016037397A1
WO2016037397A1 PCT/CN2014/088602 CN2014088602W WO2016037397A1 WO 2016037397 A1 WO2016037397 A1 WO 2016037397A1 CN 2014088602 W CN2014088602 W CN 2014088602W WO 2016037397 A1 WO2016037397 A1 WO 2016037397A1
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fin
source
region
drain
fins
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尹海洲
刘云飞
李睿
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and in particular to a method of fabricating a FinFET.
  • Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months and performance doubles.
  • devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the node size has been continuously reduced.
  • silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short channel effect, the quantum effect of the device also has a great impact on the performance of the device.
  • the operating speed and performance of silicon transistors are difficult to break through. Therefore, how to greatly improve the performance of silicon transistors in the case where the feature size cannot be reduced has become a technical difficulty to be solved.
  • the invention provides a U-shaped FinFET structure and a manufacturing method thereof. Based on the existing FinFET process, a new device structure is proposed, so that the gate length of the device is not limited by the footprint size, and the short channel is effectively solved. The problem caused by the effect.
  • the structure includes:
  • first and second fins being located above the substrate and parallel to each other;
  • a gate stack covering sidewalls of the substrate and portions of the first and second fins
  • the source region being located in an area where the first fin is not covered by the gate stack;
  • the source end epitaxial region is located above one end of the first fin and has a length less than 1/2 of the length of the fin;
  • drain region being located in an area of the second fin not covered by the gate stack
  • drain extension region located above the other end of the second fin opposite to the source region epitaxial region, the length of which is less than 1/2 of the length of the fin;
  • a sidewall spacer is disposed on both sides of the first and second fins for isolating the source region, the drain region, and the gate stack.
  • first and second fins have the same height, thickness and width.
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the present invention also provides a U-shaped FinFET device manufacturing method, including:
  • first oxide layer and second oxide layer on the surface of the first and second fins not covered by the sidewalls, wherein the first and second oxide layers are located opposite to the first and second fins Both ends of the ground, the length of which is greater than 1/2 of the length of the fin;
  • the method of forming the first fin and the second fin is:
  • the channel material layer and the source/drain material layer are etched to form a first fin and a second fin.
  • the method for forming the first and second oxide layers is:
  • the first and second oxide layers are formed in regions not covered by the photoresist.
  • the method for forming the first and second oxide layers is dry oxidation; the method for forming the source-end epitaxial region and the drain-end epitaxial region is homoepitaxial; wherein the source-end epitaxial region is homoepitaxially grown And the in-situ doping of the drain extension region simultaneously, the concentration and type of doping impurities are the same as the source and drain regions.
  • first and second fins have the same height, thickness and width.
  • the method of forming the first and second fins is an anisotropic etching.
  • the gate stack includes an interface layer, a high-k dielectric layer, a metal gate work function adjustment layer, and polysilicon.
  • the height of the gate stack is 1/2 to 3/4 of the height of the first and second fins.
  • the method of forming the gate stack is atomic layer deposition.
  • the method of removing a part of the gate stack is anisotropic selective etching.
  • the method of forming the source and drain regions is oblique ion implantation.
  • the method of forming the source and drain regions is side scatter.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. Since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current.
  • the device Since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device smaller. DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating the fabrication of source-drain contacts.
  • the present invention effectively reduces the parasitic resistance of the source and drain regions and improves the on-state current of the device.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • FIGS. 1 to 14 are schematic views showing stages of forming a U-shaped FinFET device according to the method of Embodiment 1 of the present invention; wherein, Figs. 10 to 13 are plan views shown from the top of the device; a projection along the length of the fin;
  • Figure 15 illustrates the final structure of a device formed in accordance with the method of the embodiments of the present invention.
  • the present invention provides a FinFET structure including: a substrate 100; a first fin 210 and a second fin 220, the first fin 210 and the second fin 220 being located on the substrate 100. Above, parallel to each other; a gate stack 300 covering the substrate and a sidewall of a portion of the first fin 210 and the second fin 220; a source region 410, the source region being located The first fin 210 is not covered by the gate stack; the source end epitaxial region 240 is located at a length less than one end of the first fin 210, and the length thereof is less than 1/2 of the length of the fin; the drain region 420, the drain region is located in a region where the second fin 220 is not covered by the gate stack; the drain extension region 250 is located at the opposite end of the second fin 220 opposite to the source region epitaxial region. Above, its length is less than 1/2 of the length of the fin.
  • the structure further includes a sidewall spacer 230 disposed on both sides of the first fin 210 and the second fin 220 for isolating the source region, the drain region, and the gate stack.
  • first fin 210 and the second fin 220 have the same height, thickness and width degree.
  • the gate stack includes an interface layer 310, a high-k dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340.
  • the height of the gate stack 300 is 1/2 to 3/4 of the height of the first and second fins 210 and 220.
  • the present invention proposes a new U-shaped device structure based on the existing FinFET process.
  • the structure allows the device to have a vertical channel, so that the device has the same footprint size, the device The gate length can be adjusted by changing the height of the Fin to improve the short channel effect. Since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and is naturally separated from the substrate, so that the device cannot pass through the source and the drain, thereby having a low sub-threshold slope and leakage current.
  • the device Since the device has a U-shaped vertical channel structure, the device source and drain are parallel to each other and suspended above the substrate, effectively isolating the influence of the electric field on the source end of the device, thereby further improving the short channel effect of the device and making the device smaller. DIBL.
  • the device since the device has a U-shaped vertical channel structure, the device source is suspended above the substrate and in the same plane, thereby facilitating the fabrication of source-drain contacts.
  • the present invention effectively reduces the parasitic resistance of the source and drain regions and improves the on-state current of the device.
  • the device structure proposed by the present invention is fully compatible with the existing FinFET process in the fabrication process, which greatly improves device performance.
  • the semiconductor material of the substrate and the fins may be selected from a Group IV semiconductor such as Si or Ge, or a III-V semiconductor such as GaAs, InP, GaN, SiC, or a laminate of the above semiconductor materials.
  • the first substrate material is a semiconductor material, which may be silicon, germanium, gallium arsenide or the like.
  • the substrate used is a silicon substrate.
  • the channel material layer 110 is a major portion of the channel region of the device after being processed by a subsequent process, and may be lightly doped or undoped; the doping type depends on the type of device.
  • the doping type of the channel material layer is P-type, and the doping impurity can be a group III element such as boron; for the P-type device, the doping type of the channel material layer is N-type, which can be used.
  • the doping impurities are five elements such as phosphorus and arsenic.
  • the channel region formed in the subsequent process has a doping concentration of 1e15 cm -3 , and the doping element used is boron, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the source/drain material layer 120 will become a main part of the source and drain regions of the device after being processed by a subsequent process, and its doping concentration is equal to the required concentration of the source and drain regions; the doping type depends on the type of the device.
  • the doping type of the channel material layer is N-type, and the doping impurities may be five elements such as phosphorus and arsenic;
  • the doping type of the channel material layer is P-type,
  • the doping impurity used is a group III element such as boron.
  • the source and drain regions formed in the subsequent process have a doping concentration of 1e19 cm -3 , and the doping element used is arsenic, and the doping is formed by in-situ doping by epitaxy, and the specific process steps are The existing processes are the same and will not be described here.
  • the structure after forming the source/drain material layer 120 is as shown in FIG. 2.
  • the thickness of the channel material layer 110 shown in the drawing is H2, which is equal to the height of the gate stack after the device is formed.
  • the thickness of the source/drain material layer 120 is H1.
  • the channel material layer 110 and the source/drain material layer 120 are etched by a conventional process such as projection, exposure, development, etching, etc. to form a first fin 210 and a second fin 220, the etching
  • the method can be dry etching or dry/wet etching.
  • the height after the etching of the first fin 210 and the second fin 220 is equal to the thickness H2+H1 of the channel material layer 110 and the source/drain material layer 120, wherein the trench
  • the thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process
  • the thickness H1 of the source/drain material layer 120 is the height of the source and drain regions formed in the subsequent process.
  • a gate stack 300 is formed over the substrate 100 and over the first fin 210 and the second fin 220, and is the same as the existing FinFET process.
  • the gate stack 300 includes an interface layer 310, a high-k dielectric layer 320, a metal gate work function adjustment layer 330, and polysilicon 340 in this order.
  • the material of the interface layer 310 is silicon dioxide for eliminating defects and interface states of the first and second fin surfaces, and the thickness of the interface layer 310 is generally considered in consideration of the gate control capability of the device and other properties.
  • the high-k dielectric layer 320 is generally a high-k dielectric such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO Or a combination thereof
  • the thickness of the gate dielectric layer may be 1 nm-10 nm, such as 3 nm, 5 nm or 8 nm, and the device structure after forming the high K dielectric layer is as shown in FIG.
  • the metal gate work function adjusting layer 330 may It is made of TiN, TaN or the like and has a thickness ranging from 3 nm to 15 nm.
  • the device structure after forming the metal gate work function adjusting layer 330 is as shown in FIG. 5 .
  • the above-described process for forming a gate stack is formed by atomic layer deposition.
  • polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330.
  • a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10 to 50 nm; next, the polysilicon layer is planarized, and the planarization method may be chemistry.
  • Mechanical polishing (CMP) the surface of the polysilicon is highly uniform, and the metal gate work function adjustment layer 330 is used as a stop layer of chemical mechanical polishing, so that the polysilicon of the remaining region is flush with the metal gate work function adjustment layer 330;
  • anisotropic selective engraving The polysilicon layer is directionally etched such that its surface is flush with the source/drain material layer 120, as shown in FIG.
  • the gate stack covering the first fin 210 and the second fin 220 is isotropically selectively etched to remove the portion above the polysilicon layer 340 to expose the fins. 7 is shown.
  • the source/drain regions are formed by oblique ion implantation or side scatter of the exposed fins.
  • a sidewall spacer 230 is formed on the exposed portion of the sidewall of the fin for separating the gate stack from the source and drain regions.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • the sidewall spacers may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm, or 80 nm.
  • the first and second oxide layers 510, 520 are formed over the source and drain regions.
  • the source-drain region epitaxy is often used in the art to increase the source-drain region volume, thereby reducing the parasitic resistance, due to the symmetry of the device and the interconnection structure of the circuit, the extension portion
  • the source and drain regions are often connected to each other, that is, the source terminals of the plurality of devices are connected to the same potential, and the drain terminals are connected to the same potential.
  • the previous epitaxial method inevitably causes the source and drain regions of the same device to be turned on immediately without passing through the channel, and the device cannot operate.
  • the present invention proposes a novel source-drain epitaxial structure, that is, partial extension of the fins of the source and drain regions, and at the same time, the epitaxial portions thereof are staggered to each other, so that the source and drain regions are not in contact with each other. purpose. In this manner, the parasitic resistance of the U-shaped FinFET device of the present invention is effectively reduced.
  • the source-drain epitaxial region is formed by the following steps. First, as shown in FIG. 9, the device is covered with a photoresist 400. Next, the shapes of the first and second oxide layers are etched by using a mask to expose the surface of the fin surface where the oxide layer needs to be grown. , as shown in Figure 10. The specific etching process is a common means in the art, and will not be described herein.
  • the first and second oxide layers 240, 250 are formed in regions not covered by the photoresist.
  • the present invention employs dry oxygen oxidation.
  • the fin covered by the glue 400 is exposed, and the region does not form the first oxide layer 510 and the second oxide layer 520 due to the protection of the photoresist, as shown in FIG.
  • a source-drain epitaxial region 240 that is, raised-SD. Since a part of the fin is blocked by the oxide layer, epitaxial growth cannot be performed above the region, and the obtained source
  • the drain epitaxial region exists only above the region not covered by the oxide layer. Since the oxide layers on the first and second fins are located on opposite ends of the different fins, and the thickness thereof is greater than 1/2 of the length of the fins, the source-drain epitaxial regions that can be grown are also located at the first and second fins.
  • Figure 13 shows a top view of the device after epitaxially growing the source-drain epitaxial region, the front view of which is shown in Figure 14. In-situ doping is performed while epitaxial growth, so that the epitaxial region has the same doping concentration as the source and drain regions.
  • a silicide and a metal electrode are formed over the source and drain regions and the gate, and specific process steps are not described herein.
  • the invention provides a novel source-drain epitaxial structure, that is, partial extension of the fins of the source region and the drain region, and at the same time, the epitaxial portions thereof are mutually staggered, thereby achieving the purpose of not contacting the source and drain regions, thereby solving the U. Since the source and drain regions are respectively located on two different fins, the FinFET device can be turned on by the existing epitaxial method, so that the source and drain regions of the same device can be turned on without passing through the channel, so that the device cannot work. The parasitic resistance of the U-shaped FinFET device in the present invention is effectively reduced.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种FinFET器件结构及其制造方法，包括：衬底（100）；第一、第二鳍片（210，220），所述第一、第二鳍片（210，220）位于所述衬底（100）上方，彼此平行；栅极叠层（300），覆盖所述衬底（100）和部分第一、第二鳍片（210，220）的侧壁；源区（410），位于所述第一鳍片（210）未被栅极叠层（300）所覆盖的区域；源端外延区（240），位于所述第一鳍片（210）一端的上方，其长度小于鳍片长度的1/2；漏区（420），位于所述第二鳍片（220）未被栅极叠层（300）所覆盖区域；漏端外延区（250），位于所述第二鳍片（220）中与源区（410）外延区相反的另一端的上方，其长度小于所述鳍片长度的1/2，上述设计有效地解决了短沟道效应所带来的问题。

Description

一种FinFET器件结构及其制造方法
本申请要求了2014年9月10日提交的、申请号为201410459154.7、发明名称为“一种FinFET器件结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种半导体器件制造方法，具体地，涉及一种FinFET制造方法。
技术背景
摩尔定律指出：集成电路上可容纳的晶体管数目每隔18个月增加一倍，性能也同时提升一倍。目前，随着集成电路工艺和技术的发展，先后出现了二极管、MOSFET、FinFET等器件，节点尺寸不断减小。然而，2011年以来，硅晶体管已接近了原子等级，达到了物理极限，由于这种物质的自然属性，除了短沟道效应以外，器件的量子效应也对器件的性能产生了很大的影响，硅晶体管的运行速度和性能难有突破性发展。因此，如何在在无法减小特征尺寸的情况下，大幅度的提升硅晶体管的性能已成为当前亟待解决的技术难点。
发明内容
本发明提供了一种U型FinFET结构及其制造方法，在现有FinFET工艺的基础上提出了一种新的器件结构，使器件的栅长不受footprint尺寸限制，有效地解决了短沟道效应所带来的问题。具体的，该结构包括：
衬底；
第一鳍片和第二鳍片，所述第一、第二鳍片位于所述衬底上方，彼此平行；
栅极叠层，所述栅极叠层覆盖所述衬底和部分第一、第二鳍片的侧壁；
源区，所述源区位于所述第一鳍片未被栅极叠层所覆盖的区域；
源端外延区，位于所述第一鳍片一端的上方，其长度小于鳍片长度的1/2；
漏区，所述漏区位于所述第二鳍片中未被栅极叠层所覆盖的区域；
漏端外延区，位于所述第二鳍片中与源区外延区相反的另一端的上方，其长度小于所述鳍片长度的1/2；
侧墙，所述侧墙位于所述第一、第二鳍片两侧，用于隔离源区、漏区和栅极叠层。
其中，所述第一、第二鳍片具有相同的高度、厚度和宽度。
其中，所述栅极叠层依次包括：界面层、高K介质层、金属栅功函数调节层以及多晶硅。
其中，所述栅极叠层的高度为所述第一、第二鳍片高度的1/2～3/4。
相应的，本发明还提供了一种U型FinFET器件制造方法，包括：
a.提供衬底，在所述衬底上形成第一鳍片和第二鳍片；
b.在所述衬底、所述第一、第二鳍片上方和侧面形成栅极叠层；
c.去除所述第一、第二鳍片上方和侧面的部分栅极叠层，在未被所述栅极叠层覆盖的第一、第二鳍片两侧形成侧墙；
d.在所述第一、第二鳍片未被侧墙覆盖的表面上分别形成第一氧化层和第二氧化层，所述第一、第二氧化层位于第一、第二鳍片相反地两端，其长度大于鳍片长度的1/2；
e.在未被所述第一、第二氧化层覆盖的第一、第二鳍片上分别形成源端外延区以及漏端外延区。
其中，形成所述第一鳍片和第二鳍片的方法为：
在所述衬底上依次形成沟道材料层和源漏材料层；
对所述沟道材料层和源漏材料层进行刻蚀，形成第一鳍片和第二鳍片。
其中，形成所述第一、第二氧化层的方法为：
以光刻胶覆盖所述半导体结构，以第一、第二氧化层的形状为掩膜版 进行刻蚀，使鳍片表面需要生长氧化层的区域暴露出来；
在未被光刻胶覆盖的区域生成所述第一、第二氧化层。
其中，形成所述第一、第二氧化层的方法为干氧氧化；形成所述源端外延区以及漏端外延区的方法为同质外延；其中，同质外延生长所述源端外延区以及漏端外延区的同时进行原位掺杂，掺杂杂质的浓度和类型与源漏区相同。
其中，所述第一、第二鳍片具有相同的高度、厚度和宽度。
其中，形成所述第一、第二鳍片的方法为各向异性刻蚀。
其中，所述栅极叠层依次包括：界面层、高K介质层、金属栅功函数调节层以及多晶硅。
其中，所述栅极叠层的高度为所述第一、第二鳍片高度的1/2～3/4。
其中，形成所述栅极叠层的方法为原子层淀积。
其中，去除部分栅极叠层的方法为各向异性选择性刻蚀。
其中，形成所述源漏区的方法为倾斜的离子注入。
其中，形成所述源漏区的方法为侧向散射。
本发明在现有FinFET工艺的基础上提出了一种新的U型器件结构，与现有技术中相比，该结构使器件具有垂直的沟道，因而在footprint尺寸不变的情况下，器件可以通过改变Fin的高度来调节栅长，改善短沟道效应。由于器件具有U型垂直沟道结构，器件源漏悬于衬底上方，与衬底天然分离，因而使得该器件的无法发生源漏穿通，从而具有较低的亚阈态斜率及漏电流。由于器件具有U型垂直沟道结构，器件源漏相互平行且悬于衬底上方，有效隔离了器件漏端电场对源端的影响，因而进一步改善了器件的短沟道效应，使器件具有较小的DIBL。同时，由于器件具有U型垂直沟道结构，器件源漏悬于衬底上方且位于同一平面内，因而便于制作源漏接触。最后，由于该器件具有源漏外延区，即raised-SD的结构，本发明有效的降低了源漏区的寄生电阻，提高了器件的开态电流。本发明提出的器件结构在制作工艺上与现有FinFET工艺完全兼容，极大地提高了器件性能。
附图说明
图1～图14示意性地示出了根据本发明中实施例1中的方法形成U型FinFET器件各阶段的示意图；其中，图10～图13为从器件顶部示出的俯视图；图14为沿鳍片长度方向的投影图；
图15示出了根据本发明中的实施例所述的方法形成的器件的最终结构；
图中相同或相似的图形代表相同的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
参见图15，本发明提供了一种FinFET结构，包括：衬底100；第一鳍片210和第二鳍片220，所述第一鳍片210和第二鳍片220位于所述衬底100上方，彼此平行；栅极叠层300，所述栅极叠层覆盖所述衬底和部分第一鳍片210和第二鳍片220的侧壁；源区410，所述源区位于所述第一鳍片210未被栅极叠层所覆盖的区域；源端外延区240，位于其长度小于所述第一鳍片210一端的上方，其长度小于鳍片长度的1/2；漏区420，所述漏区位于所述第二鳍片220未被栅极叠层所覆盖的区域；漏端外延区250，位于所述第二鳍片220中与源区外延区相反的另一端的上方，其长度小于所述鳍片长度的1/2。
其中，该结构还包括侧墙230，所述侧墙230位于所述第一鳍片210和第二鳍片220两侧，用于隔离源区、漏区和栅极叠层。
其中，所述第一鳍片210和第二鳍片220具有相同的高度、厚度和宽 度。
其中，所述栅极叠层依次包括：界面层310、高K介质层320、金属栅功函数调节层330以及多晶硅340。
其中，所述栅极叠层300的高度为所述第一、第二鳍片210、220高度的1/2～3/4。
本发明在现有FinFET工艺的基础上提出了一种新的U型器件结构，与现有技术中相比，该结构使器件具有垂直的沟道，因而在footprint尺寸不变的情况下，器件可以通过改变Fin的高度来调节栅长，改善短沟道效应。由于器件具有U型垂直沟道结构，器件源漏悬于衬底上方，与衬底天然分离，因而使得该器件的无法发生源漏穿通，从而具有较低的亚阈态斜率及漏电流。由于器件具有U型垂直沟道结构，器件源漏相互平行且悬于衬底上方，有效隔离了器件漏端电场对源端的影响，因而进一步改善了器件的短沟道效应，使器件具有较小的DIBL。同时，由于器件具有U型垂直沟道结构，器件源漏悬于衬底上方且位于同一平面内，因而便于制作源漏接触。最后，由于该器件具有源漏外延区，即raised-SD的结构，本发明有效的降低了源漏区的寄生电阻，提高了器件的开态电流。本发明提出的器件结构在制作工艺上与现有FinFET工艺完全兼容，极大地提高了器件性能。
以下将参照附图更详细地描述本实发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在……上面”或“在……上面并与之邻接”的表述方式。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。例如，衬底和鳍片的半导体材料可以选自IV族半导体，如Si或Ge，或III-V族半导体，如GaAs、InP、GaN、SiC，或上述半导体材料的叠层。
首先结合附图对本发明的实施例1进行详细描述。
参见图1，示出了本发明中的第一衬底100。所述第一衬底材料为半导体材料，可以是硅，锗，砷化镓等，优选的，在本实施例中，所用衬底为硅衬底。
接下来，在所述衬底100上依次外延生长沟道材料层110和源漏材料层120。所述沟道材料层110在经过后续工艺的处理后为器件沟道区的主要部分，可以轻掺杂或者不掺杂；掺杂类型根据器件的类型而定。对于N型器件，沟道材料层的掺杂类型为P型，可采用的掺杂杂质为硼等三族元素；对于P型器件，沟道材料层的掺杂类型为N型，可采用的掺杂杂质为磷、砷等五族元素。在本实施例中，后续工艺中形成的沟道区具有1e15cm-3的掺杂浓度，所采用的掺杂元素为硼，该掺杂通过外延时原位掺杂形成，具体的工艺步骤与现有工艺相同，在此不再赘述。
所述源漏材料层120在经过后续工艺的处理后，将成为器件源漏区的主要部分，其掺杂浓度与源漏区所需浓度相等；掺杂类型根据器件的类型而定。对于N型器件，沟道材料层的掺杂类型为N型，可采用的掺杂杂质为磷、砷等五族元素；对于P型器件，沟道材料层的掺杂类型为P型，可采用的掺杂杂质为硼等三族元素。在本实施例中，后续工艺中形成的源漏区具有1e19cm-3的掺杂浓度，所采用的掺杂元素为砷，该掺杂通过外延时原位掺杂形成，具体的工艺步骤与现有工艺相同，在此不再赘述。
形成源漏材料层120之后的结构如图2所示，图中所示沟道材料层110的厚度为H2，等于器件形成之后栅极叠层高度。源漏材料层120的厚度为H1。
接下来，经过投影，曝光，显影，刻蚀等常规工艺对所述沟道材料层110和源漏材料层120进行刻蚀，形成第一鳍片210和第二鳍片220，所述刻蚀方法可以是干法刻蚀或干法/湿法刻蚀。如图3所示，所述第一鳍片210和第二鳍片220刻蚀完成之后的高度等于所述沟道材料层110和源漏材料层120的厚度H2+H1，其中，所述沟道材料层110的厚度H2即为后续工艺中形成的栅极叠层的高度，所述源漏材料层120的厚度H1即为后续工艺中形成的源漏区的高度。
接下来，如图4～6所示，在所述衬底100和所述第一鳍片210和第二鳍片220上方和侧面形成栅极叠层300，与现有的FinFET工艺相同，所述栅极叠层300依次包括界面层310、高K介质层320、金属栅功函数调节层330以及多晶硅340。
其中，所述界面层310的材料为二氧化硅，用于消除第一、第二鳍片表面的缺陷和界面态，考虑到器件的栅控能力以及其他性能，所述界面层310的厚度一般为0.5～1nm；所述高K介质层320一般为高K介质，如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅介质层的厚度可以为1nm-10nm，例如3nm、5nm或8nm，形成高K介质层之后的器件结构如图4所示；所述金属栅功函数调节层330可以采用TiN、TaN等材料制成，其厚度范围为3nm～15nm，形成金属栅功函数调节层330之后的器件结构如图5所示。
为了使栅极叠层300具有良好的台阶覆盖特性，获得质量优良的薄膜，上述形成栅极叠层的工艺均采用原子层淀积的方法形成。
接下来，在所述金属栅功函数调节层330表面形成多晶硅340。首先，采用化学汽相淀积的方法在所述器件表面淀积一层多晶硅，使其覆盖整个器件10～50nm；接下来，对所述多晶硅层进行平坦化，所述平坦化方法可以是化学机械抛光(CMP)，使所述多晶硅表面高度一致，以所述金属栅功函数调节层330作为化学机械抛光的停止层，使其余区域的多晶硅与所述金属栅功函数调节层330平齐；接下来，使用各向异性选择性刻 蚀对所述多晶硅层进行定向刻蚀，使其表面与所述源漏材料层120平齐，如图6所示。
接下来，对覆盖所述第一鳍片210和第二鳍片220的栅极叠层进行各向同性选择性刻蚀，去除其位于多晶硅层340上方的部分，露出所述鳍片，如图7所示。对露出的鳍片进行倾斜的离子注入或者侧向散射形成所述源漏区。
接下来，如图8所示，在露出的部分所述鳍片的侧壁上形成侧墙230，用于将栅极叠层与源漏区隔开。侧墙230可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙230可以具有多层结构。侧墙可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来，在所述源漏区上方形成所述第一、第二氧化层510、520。为了减小源漏区的寄生电阻，本领域中多采用源漏区外延的方式来增大源漏区体积，从而减小寄生电阻，由于器件的对称性和电路的互连结构，外延部分的源漏区往往彼此相连，即多个器件的源端连接相同的电势，漏端连接相同的电势。然而在本发明中，由于源漏区分别位于两个不同的鳍片上，采用之前的外延方法将不可避免的使同一器件的源漏区不通过沟道即刻导通，时器件无法工作。
为了解决这一问题，本发明提出了一种新型源漏外延结构，即对源区和漏区的鳍片进行部分外延，同时使其外延的部分相互交错，从而达到使源漏区不接触的目的。采用这种方式，有效减小了本发明中的U型结构的FinFET器件的寄生电阻。
具体的，通过以下步骤形成源漏外延区。首先，如图9所示，采用光刻胶400覆盖所述器件，接下来，第一、第二氧化层的形状为掩膜版进行刻蚀，使鳍片表面需要生长氧化层的区域暴露出来，如图10所示。具体的刻蚀工艺为本领域中的常用手段，在此不再赘述。
接下来，在未被光刻胶覆盖的区域生成所述第一、第二氧化层240、250。为了保证鳍片与氧化层之间良好的界面性质，本发明采用干氧氧化 的方法形成所述第一、第二氧化层，使其覆盖第一、第二鳍片上未被光刻胶400覆盖的区域，如图11所示，最后去除光刻胶400，使被光刻胶400覆盖的鳍片暴露出来，该区域由于光刻胶的保护没有形成第一氧化层510和第二氧化层520，如图12所示。
接下来，以鳍片表面的硅为籽晶进行外延生长，形成源漏外延区240，即raised-SD，由于一部分鳍片被氧化层遮挡，因此该区域上方无法进行外延生长，从而得到的源漏外延区仅存在于未被氧化层覆盖的区域上方。由于第一、第二鳍片上的氧化层位于不同鳍片上相反地两端，且其厚度大于鳍片长度的1/2，因此可以生长获得的源漏外延区也位于第一、第二鳍片相反地两端，且由于其长度小于鳍片长度的1/2，因此在外延时不会彼此相连，有效的减小了源漏区寄生电阻。图13示出了外延生长源漏外延区之后的器件的俯视图，其正视图如图14所示。在外延生长的同时进行原位掺杂，使外延区具有与源漏区相同的掺杂浓度。
接下来，与现有技术相同，在所述源漏区和栅极上方形成硅化物以及金属电极，具体工艺步骤在此不再赘述。
本发明提出了一种新型源漏外延结构，即对源区和漏区的鳍片进行部分外延，同时使其外延的部分相互交错，从而达到使源漏区不接触的目的，从而解决了U型FinFET器件由于源漏区分别位于两个不同的鳍片上，采用现有的外延方法直接外延时产生的使同一器件的源漏区不通过沟道即可导通，使器件无法工作得问题，有效减小了本发明中的U型结构的FinFET器件的寄生电阻。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即 将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (18)

  1. 一种U型FinFET器件结构，包括：
    衬底(100)；
    第一鳍片(210)和第二鳍片(220)，所述第一鳍片(210)和第二鳍片(220)位于所述衬底(100)上方，彼此平行；
    栅极叠层(300)，所述栅极叠层覆盖所述衬底和部分第一鳍片(210)和第二鳍片(220)的侧壁；
    源区(410)，所述源区位于所述第一鳍片(210)未被栅极叠层所覆盖区域；
    源端外延区(240)，位于所述第一鳍片(210)一端的上方，其长度小于鳍片长度的1/2；
    漏区(420)，所述漏区位于所述第二鳍片(220)未被栅极叠层所覆盖区域；
    漏端外延区(250)，位于所述第二鳍片(220)中与源区外延区相反的另一端的上方，其长度小于所述鳍片长度的1/2；
    侧墙(230)，所述侧墙(230)位于所述第一鳍片(210)和第二鳍片(220)两侧，栅极叠层(300)上方，用于隔离源区、漏区和栅极叠层。
  2. 根据权利要求1所述的FinFET器件结构，其特征在于，所述第一鳍片(210)和第二鳍片(220)具有相同的高度、厚度和宽度。
  3. 根据权利要求1所述的FinFET器件结构，其特征在于，所述第一鳍片(210)和第二鳍片(220)之间的距离为5～50nm。
  4. 根据权利要求1所述的FinFET器件结构，其特征在于，所述栅极叠层依次包括：界面层(310)、高K介质层(320)、金属栅功函数调节层(330)以及多晶硅(340)。
  5. 根据权利要求1所述的FinFET器件结构，其特征在于，所述栅极叠层(300)的高度为所述第一、第二鳍片(210、220)高度的1/2～3/4。
  6. 一种U型FinFET器件制造方法，包括：
    a.提供衬底(100)，在所述衬底(100)上形成第一鳍片(210)和第二鳍片(220)；
    b.在所述衬底(100)、所述第一鳍片(210)和第二鳍片(220)上方和侧面形成栅极叠层；
    c.去除所述第一、第二鳍片上方和侧面的部分栅极叠层，在未被所述栅极叠层覆盖的第一、第二鳍片两侧形成侧墙(230)；
    d.在所述第一、第二鳍片未被侧墙(230)覆盖的表面上分别形成第一氧化层(510)和第二氧化层(520)，所述第一、第二氧化层位于第一、第二鳍片相反地两端，其长度大于鳍片长度的1/2；
    e.以未被所述第一、第二氧化层覆盖的鳍片表面的硅为籽晶进行外延生长，形成源端外延区(240)以及漏端外延区(250)。
  7. 根据权利要求6所述的制造方法，其特征在于，在步骤a中，形成所述第一鳍片(210)和第二鳍片(220)的方法为：
    在所述衬底(100)上依次形成沟道材料层(110)和源漏材料层(120)；
    对所述沟道材料层(110)和源漏材料层(120)进行刻蚀，形成第一鳍片(210)和第二鳍片(220)。
  8. 根据权利要求6所述的制造方法，其特征在于，形成所述第一、第二氧化层(510、520)的方法为：
    以光刻胶覆盖所述半导体结构，以第一、第二氧化层的形状为掩膜版进行刻蚀，使鳍片表面需要生长氧化层的区域暴露出来；
    在未被光刻胶覆盖的区域生成所述第一、第二氧化层(240、250)。
  9. 根据权利要求8所述的制造方法，其特征在于，形成所述第一、第二氧化层的方法为干氧氧化。
  10. 根据权利要求8所述的制造方法，其特征在于，形成所述源端外延区(240)以及漏端外延区(250)的方法为同质外延。
  11. 根据权利要求10所述的制造方法，其特征在于，同质外延生长所述源端外延区(240)以及漏端外延区(250)的同时进行原位掺杂，掺杂杂质的浓度和类型与源漏区相同。
  12. 根据权利要求6所述的制造方法，其特征在于，所述第一鳍片(210)和第二鳍片(220)之间的距离为5～50nm。
  13. 根据权利要求6所述的制造方法，其特征在于，形成所述第一鳍片(210)和第二鳍片(220)的方法为各向异性刻蚀。
  14. 根据权利要求6所述的制造方法，其特征在于，所述栅极叠层(300)的高度为所述第一、第二鳍片(210、220)高度的1/2～3/4。
  15. 根据权利要求6所述的制造方法，其特征在于，形成所述栅极叠层的方法为原子层淀积。
  16. 根据权利要求6所述的制造方法，其特征在于，去除部分栅极叠层的方法为各向异性选择性刻蚀。
  17. 根据权利要求6所述的制造方法，其特征在于，形成所述源漏区的方法为倾斜的离子注入。
  18. 根据权利要求6所述的制造方法，其特征在于，形成所述源漏区的方法为侧向散射。
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