WO2016026233A1 - 移位寄存器、阵列基板及显示装置 - Google Patents

移位寄存器、阵列基板及显示装置 Download PDF

Info

Publication number
WO2016026233A1
WO2016026233A1 PCT/CN2014/092512 CN2014092512W WO2016026233A1 WO 2016026233 A1 WO2016026233 A1 WO 2016026233A1 CN 2014092512 W CN2014092512 W CN 2014092512W WO 2016026233 A1 WO2016026233 A1 WO 2016026233A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
switching element
signal
shift register
terminal
Prior art date
Application number
PCT/CN2014/092512
Other languages
English (en)
French (fr)
Inventor
马占洁
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/772,224 priority Critical patent/US9805638B2/en
Publication of WO2016026233A1 publication Critical patent/WO2016026233A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display, and in particular to a shift register, an array substrate, and a display device.
  • a Shift Register is a device based on a flip-flop operating on several identical time pulses (clock signals) into which data is input in parallel or serially. The time pulses are sequentially shifted one bit to the left or right and output at the output.
  • the conventional shift register usually adopts the method of triggering and outputting simultaneously, that is, in a plurality of cascaded shift register structures, the output of the output of one stage is used as the input trigger signal of the shift register of the next stage. And as the output signal of this level.
  • Such a shift register has a simple structure and a wide application range, and has been widely used in various digital integrated circuits.
  • the output signal of such a shift register is affected by the fluctuation of the AC pulse signal of the clock signal, resulting in instability of the output signal and degradation of the signal quality.
  • an unstable output signal will affect the stability of the display pixel, resulting in a decrease in display effect or even display failure.
  • the present disclosure provides a shift register, an array substrate, and a display device, which are not separated from an AC pulse signal by separating a trigger and an output of the shift register from each other and using a DC power source as an operating voltage.
  • the effect of fluctuations can improve the stability of the output signal and display pixels.
  • a shift register including a trigger module, an output module, an input terminal, a first output terminal, and a second output terminal, wherein:
  • the triggering module is configured to output, to the second output end and the output module, a trigger signal that is in phase with the input signal and delayed by one-half clock period from the input signal according to an input signal from the input end under a clock signal;
  • the output module is configured to output, after the triggering of the trigger signal, a phase inversion with the input signal to the first output terminal and a delay of one-half clock period from the input signal under the trigger of the trigger signal output signal;
  • the operating voltage of the signal output by the first output is provided by a DC power source.
  • the trigger module includes six switching elements and a capacitor, wherein:
  • a second end of the first switching element is connected to the input end, and a first end thereof is connected to a first end of the second switching element, a first end of the capacitor, and a control end of the sixth switching element;
  • the second end of the second switching element is connected to the control end of the third switching element
  • the first end of the third switching element is connected to the second end of the fourth switching element and the control end of the fifth switching element;
  • the first end of the fourth switching element is connected to its control end
  • the first end of the fifth switching element is connected to the second end of the capacitor and the second end of the sixth switching element, and is connected to the second output end and the output module.
  • the second terminal of the third switching element is connected to a high-level operating voltage
  • the control terminal of the fourth switching element and the first terminal are connected to a low-level operating voltage
  • the clock signal includes a first clock signal and a second clock signal
  • the first clock signal is connected to a control end of the first switching element
  • the second clock signal is connected to the second switch a control end of the component and a first end of the sixth switching component.
  • the output module comprises four switching elements: seventh to tenth switching elements, wherein:
  • a first end of the seventh switching element is connected to the trigger module, and a second end thereof is connected to a control end of the eighth switching element;
  • the first end of the eighth switching element is connected to the first end of the tenth switching element, and is connected to the first output end;
  • a control end of the tenth switching element is connected to a second end of the ninth switching element
  • the control end of the ninth switching element is connected to the first end and to the second end of the tenth switching element.
  • the second end of the eighth switching element is connected to a high-level operating voltage
  • the control terminal of the ninth switching element and the first terminal are connected to a low-level operating voltage
  • the clock signal includes a first clock signal and a second clock signal, the second clock signal being coupled to a control terminal of the seventh switching element.
  • the switching element is a P-channel type thin film transistor.
  • An array substrate comprising any one of the above shift registers.
  • a display device comprising any one of the above array substrates.
  • the present disclosure mainly provides a shift register with a two-stage output structure by using a separate design of the trigger module and the output module, and uses a DC power supply to provide an operating voltage of the second-stage output (ie, the first output terminal) so that it is not subjected to an AC pulse.
  • the effect of signal fluctuations mainly provides a shift register with a two-stage output structure by using a separate design of the trigger module and the output module, and uses a DC power supply to provide an operating voltage of the second-stage output (ie, the first output terminal) so that it is not subjected to an AC pulse.
  • the first output is used for the output of the line
  • the second output is used for the trigger of the next line and the output of the line, so that the trigger and the output are separated from each other, and since the line is provided
  • the first output of the gate line signal is supplied with a DC power supply, so the output is not affected by the fluctuation of the AC pulse signal, the output signal is more stable, and the display pixel is more stable.
  • FIG. 1 is a schematic structural diagram of a shift register in an embodiment of the present disclosure
  • FIG. 2 is a circuit structural diagram of a shift register in an embodiment of the present disclosure
  • 3 is a timing chart showing the operation of a shift register in one embodiment of the present disclosure.
  • FIG. 1 is a block diagram showing the structure of a shift register in one embodiment of the present disclosure.
  • the shift register includes a trigger module, an output module, an input terminal, a first output terminal, and a second output terminal.
  • the trigger module is configured to output, according to an input signal from the input end, a trigger signal that is in phase with the input signal and delayed by one-half clock period from the input signal according to the input signal from the input terminal;
  • the output module is configured to output, under the action of the trigger signal, the output signal inverted from the input signal and delayed by one-half clock period from the input signal to the first output terminal under the trigger of the trigger signal;
  • the operating voltage of the signal outputted by the first output is provided by a DC power source.
  • the actual function of the trigger module is basically equivalent to the function of the shift register, and the output module is based on this to achieve the secondary output. Connection relationship, trigger module and input The input is connected, and a trigger signal is output to the second output terminal and the output module, and the output module is triggered by the trigger signal, and the output signal is output to the first output terminal.
  • the function of the shift register itself can also be derived.
  • the output trigger signal and the output signal mentioned here actually refer to the time sequence of the clock signal.
  • the pulse mentioned here refers only to a single pulse signal (ie, a low-high-low or high-low-high single square wave waveform), but in reality all waveforms can be superimposed by several single-pulse signals. Therefore, there is no substantial difference between the two, and in a broad sense, it can be a high-low waveform of any shape.
  • the DC power supply is used to provide the operating voltage of the first output terminal, the signal outputted by the first output terminal is not affected by the band of the AC AC pulse signal, and thus the stability of the output signal can be ensured. This feature ensures the stability of the display pixels when used in a gate line driving circuit in a display device.
  • the trigger module includes six switching elements M1 to M6 and a capacitor Cst, wherein:
  • the second end of the first switching element M1 is connected to the input terminal STV, and the first end thereof is connected to the first end of the second switching element M2, the first end of the capacitor Cst, and the control end of the sixth switching element M6;
  • the second end of the second switching element M2 is connected to the control end of the third switching element M3;
  • the first end of the third switching element M3 is connected to the second end of the fourth switching element M4 and the control end of the fifth switching element M5;
  • the first end of the fourth switching element M4 is connected to its control end
  • the first end of the fifth switching element M5 is connected to the second end of the capacitor and the second end of the sixth switching element M6, and is connected to the second output terminal OUTPUT and the output module.
  • the trigger module having the structure can directly output a trigger signal that is in phase with the input signal and delayed by half a clock cycle from the input signal, and uses only six switching elements and one capacitor, and can be adapted to the display panel fabrication process.
  • the specific circuit timing of this trigger module will be described below.
  • the second terminal of the third switching element M3 is connected to the operating voltage VGH of the high level
  • the control terminal of the fourth switching element M4 and the first terminal are connected to the operating voltage VGL of the low level to ensure the overall circuit. consistency.
  • the clock signal here includes a first clock signal CLK1 and a second clock signal CLK2, which are generally square wave pulse signals alternately appearing at a high frequency and a low frequency at a fixed time.
  • the first clock signal CLK1 is connected to the control end of the first switching element M1
  • the second clock signal CLK2 is connected to the control end of the second switching element M2 and the first end of the sixth switching element M6.
  • the above is an exemplary circuit structure of the trigger module, and an output module that can be used with the trigger module will be further described below.
  • the output module includes four switching elements M7 to M10, wherein:
  • the first end of the seventh switching element M7 is connected to the trigger module, and the second end thereof is connected to the control end of the eighth switching element M8;
  • the first end of the eighth switching element M8 is connected to the first end of the tenth switching element M10, and is connected to the first output end STV2;
  • a control end of the tenth switching element M10 is connected to a second end of the ninth switching element M9;
  • the control end of the ninth switching element M9 is connected to the first end and to the second end of the tenth switching element M10.
  • the output module having the structure can directly output an output signal which is inverted from the input signal and delayed by half a clock cycle from the input signal, and uses only four switching elements, and can be adapted to the display panel manufacturing process.
  • the specific circuit timing of this output module will be described below.
  • the second terminal of the eighth switching element M8 is connected to the high-level operating voltage VGH, and the control terminal of the ninth switching element M9 and the first terminal are connected to the low-level operating voltage VGL to ensure uniformity of the overall circuit.
  • the operating voltages VGH and VGL here are provided by the DC power supply to eliminate the influence of the AC pulse signal on the output.
  • the first clock signal CLK1 is connected to the control end of the first switching element M1
  • the second clock signal CLK2 is connected to the control end of the second switching element M2, the first end of the sixth switching element M6, and the seventh
  • the control terminal of the switching element M7 Only M7 belongs to the output module. It can be seen that the clock signal is not directly connected to the output signal path in the output module, so that the control terminal of the M7 is separated from the overall output signal path, so the output signal is not affected. The effect of the clock AC pulse signal.
  • a P-channel Thin Film Transistor is used as the switching element, and the control terminal is the gate of the TFT, the first end is the source of the TFT, and the second end is the TFT.
  • the drain is used.
  • an N-channel thin film transistor can also be used. In this case, the terminal is the gate of the TFT, the first end is the drain of the TFT, and the second end is the source of the TFT.
  • FIG. 3 is a timing chart showing the operation of a shift register in one embodiment of the present disclosure.
  • the overall operation timing chart can be as shown in FIG. 3 (STV corresponds to the input signal, STV2 corresponds to the trigger signal, and OUTPUT corresponds to the output signal).
  • the working sequence diagram includes four stages, and the first stage to the fourth stage are represented by 1, 2, 3, and 4, respectively.
  • the first stage STV and CLK1 are turned on, the STV signal is input to the gate of the transistor M6 through the transistor M1, and the potential is held by the capacitor Cst, while the STV signal turns on the transistor M6, and the OFF signal (high voltage signal) of the CLK2 is passed. Transistor M6 is transferred to the STV2 line.
  • the inverter composed of the transistors M3 and M4, since the transistor M3 is turned off, the inverter outputs the turn-on potential (low voltage signal) controlled by the transistor M4, turning on the transistor M5, and outputting the high voltage signal of the VGH to the STV2. on-line.
  • the transistor M7 controlled by CLK2 is in the off state, so that M8 in the inverter structure composed of the transistors M8, M9, M10 is in the off state, and the inverter outputs the VGL low voltage signal controlled by M9 and M10, and the signal is transmitted to This level is OUTPUT.
  • the second phase CLK1 becomes a high voltage shutdown signal, and CLK2 becomes a low voltage turn-on signal. Since the low voltage signal on the gate of transistor M6 is held by capacitor Cst, transistor M6 is turned on, and the low voltage signal of CLK2 is transmitted through transistor M6 to the STV2 line. At the same time, the transistor M2 controlled by CLK2 is also turned on, and the M6 gate low voltage signal is transmitted to the gate of the transistor M3 through M2, so that the transistor M3 is turned on. At this time, the inverter composed of M3 and M4 outputs the VGH signal, and the signal passes. M3 is transferred to the gate of M5, leaving M5 in the off state.
  • the primary structure outputs a low-voltage turn-on signal, which is the turn-on signal of the downlink shift register on the one hand, and the start signal of the secondary structure of the bank.
  • a low-voltage turn-on signal which is the turn-on signal of the downlink shift register on the one hand
  • the start signal of the secondary structure of the bank When the low voltage signal of CLK2 is transmitted to STV2, M7 controlled by CLK2 is turned on, and the low voltage signal is transmitted to the gate of M8.
  • the inverter composed of M8, M9, M10 outputs the VGH high voltage signal controlled by M8.
  • M1 controlled by CLK1 is turned on, the high voltage STV signal is transmitted to the gate terminal of M6, and held by the capacitor Cst. Make M6 in the off state.
  • the inverter composed of M3, M4 outputs a VGL signal, which turns M5 on and transmits the VGH signal to the STV2 line.
  • the inverter composed of M8, M9, and M10 outputs a VGL signal, which is transmitted to the OUTPUT.
  • CLK2 becomes the on signal, and the inverter composed of M3 and M4 outputs VGL to the M5 gate, so that the VGH signal is transmitted to the STV2 line through M5.
  • the inverter consisting of M8, M9, M10 still outputs the low voltage signal of VGL.
  • CLK1 and CLK2 are repeated in the third and fourth phases, so that the primary output remains as the VGH high voltage signal, and the secondary output remains as the VGL low voltage signal.
  • the above circuit can realize the shift output function of the shift register, and is specifically applied to the gate drive circuit here, so that the trigger and the output can be separated from each other. Moreover, since the first output terminal of the line signal of the line is supplied with a DC power supply, the output thereof is not affected by the fluctuation of the AC pulse signal, the output signal is more stable, and the display pixel is more stable.
  • an embodiment of the present disclosure provides an array substrate including any one of the foregoing shift registers.
  • it can apply a shift register in a gate line driving circuit of an array substrate, and provide a gate line driving signal to the pixel unit in a plurality of cascaded shift registers.
  • the input end of each stage shift register is connected to the second output end of the first stage shift register or the gate line driving signal, and the first output end of each stage shift register is connected to the gate line driving signal output of the line.
  • the first output terminal of the grid signal of the bank is supplied with a DC power supply, the output thereof is not affected by the fluctuation of the AC pulse signal, and the output signal is more stable, so that the display pixel is also more stable.
  • the shift register can also be used in other parts of the array substrate based on the same idea, and the use of the shift register is not limited to the same shift register cascade, and can be replaced or combined with other circuit structures.
  • an embodiment of the present disclosure provides a display device, which includes any of the foregoing array substrates, which may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, or a television. Any product or component with display function, such as a machine, monitor, laptop, digital photo frame, navigator, etc.
  • the present disclosure provides a shift register, an array substrate, and a display device, which are not separated from an AC pulse signal by separating a trigger and an output of the shift register from each other and using a DC power source as an operating voltage. Influence, which can improve the stability of the output signal and display pixels Sex.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种移位寄存器、阵列基板及显示装置，该移位寄存器包括：触发模块、输出模块、输入端、第一输出端和第二输出端，其中：触发模块用于在时钟信号作用下根据来自输入端的输入信号向第二输出端和输出模块输出与输入信号同相、且比输入信号延迟半个时钟周期的触发信号；输出模块用于在时钟信号作用下在触发信号的触发下向第一输出端输出与输入信号反相、且比输入信号延迟半个时钟周期的输出信号；第一输出端所输出信号的工作电压由直流电源提供。通过将移位寄存器中触发和输出相互分离，并以直流电源作为工作电压，使其不会受到交流脉冲信号波动的影响，从而提高输出信号及显示像素的稳定性。

Description

移位寄存器、阵列基板及显示装置 技术领域
本公开涉及显示领域，具体涉及一种移位寄存器、阵列基板及显示装置。
背景技术
在数字电路中，移位寄存器(Shift Register)是一种在若干相同时间脉冲(时钟信号)下工作的触发器为基础的器件，数据以并行或串行的方式输入到该器件中，然后每个时间脉冲依次向左或右移动一个比特，在输出端进行输出。
传统的移位寄存器通常采用触发、输出同时进行的方式，也就是在多个级联的移位寄存器结构中，某一级的输出端输出的信号既作为下一级移位寄存器的输入触发信号，又作为本一级的输出信号。这样的移位寄存器结构简单，适用范围广，已经广泛应用于各类数字集成电路中。
但是，此类移位寄存器的输出信号会受时钟信号的交流脉冲信号波动影响，造成输出信号的不稳定、信号质量下降。以具体的实际应用场景为例，当这样的移位寄存器应用于阵列基板的栅线驱动电路时，不稳定的输出信号将会影响到显示像素的稳定性，造成显示效果下降甚至显示故障。
发明内容
针对现有技术的不足，本公开提供一种移位寄存器、阵列基板及显示装置，通过将移位寄存器中触发和输出相互分离，并以直流电源作为工作电压，使其不会受到交流脉冲信号波动的影响，从而可以提高输出信号及显示像素的稳定性。
按照本公开的一个方面，提供一种移位寄存器，该移位寄存器包括触发模块、输出模块、输入端、第一输出端和第二输出端，其中：
所述触发模块用于在时钟信号作用下根据来自输入端的输入信号向所述第二输出端和输出模块输出与所述输入信号同相、且比所述输入信号延迟半个时钟周期的触发信号；
所述输出模块用于在时钟信号作用下在所述触发信号的触发下向所述第一输出端输出与所述输入信号反相、且比所述输入信号延迟半个时钟周期的 输出信号；
所述第一输出端所输出信号的工作电压由直流电源提供。
可替换地，所述触发模块包括六个开关元件和一个电容，其中：
第一开关元件的第二端与所述输入端相连，其第一端与第二开关元件的第一端、电容的第一端、以及第六开关元件的控制端相连；
所述第二开关元件的第二端与第三开关元件的控制端相连；
所述第三开关元件的第一端与第四开关元件的第二端、以及第五开关元件的控制端相连；
所述第四开关元件的第一端与其控制端相连；
所述第五开关元件的第一端与电容的第二端、以及第六开关元件的第二端相连，并与所述第二输出端和所述输出模块相连。
可替换地，所述第三开关元件的第二端接高电平的工作电压，所述第四开关元件的控制端和第一端接低电平的工作电压。
可替换地，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号接于所述第一开关元件的控制端，所述第二时钟信号接于所述第二开关元件的控制端和所述第六开关元件的第一端。
可替换地，所述输出模块包括四个开关元件：第七至第十开关元件，其中：
第七开关元件的第一端与所述触发模块相连，其第二端与第八开关元件的控制端相连；
所述第八开关元件的第一端与第十开关元件的第一端相连，并与所述第一输出端相连；
所述第十开关元件的控制端与第九开关元件的第二端相连；
所述第九开关元件的控制端与第一端相连，并与所述第十开关元件的第二端相连。
可替换地，所述第八开关元件的第二端接高电平的工作电压，所述第九开关元件的控制端和第一端接低电平的工作电压。
可替换地，所述时钟信号包括第一时钟信号和第二时钟信号，所述第二时钟信号接于所述第七开关元件的控制端。
可替换地，所述开关元件为P沟道型薄膜晶体管。
一种阵列基板，所述阵列基板包括上述任意一种移位寄存器。
一种显示装置，所述显示装置包括上述任意一种阵列基板。
本公开主要通过触发模块和输出模块的分离设计，使移位寄存器具有两级输出结构，而且使用直流电源提供第二级输出(即第一输出端)的工作电压，使其不会受到交流脉冲信号波动的影响。
具体应用在阵列基板上时，将第一输出端用于本行的输出，将第二输出端用于下一行和本行输出的触发，以此使触发和输出相互分离，而且由于提供本行栅线信号的第一输出端是使用直流电源提供工作电压的，所以其输出不会受到交流脉冲信号波动的影响，输出信号会更加稳定，从而显示像素也会更加稳定。
当然，实施本公开的任一产品或方法并不一定需要同时达到以上所述的所有优点。
附图说明
图1是本公开一个实施例中移位寄存器的结构示意图；
图2是本公开一个实施例中移位寄存器的电路结构图；
图3是本公开一个实施例中移位寄存器的工作时序图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。
图1示出本公开一个实施例中移位寄存器的结构示意图。参见图1，该移位寄存器包括触发模块、输出模块、输入端、第一输出端和第二输出端。
在图1中，触发模块用于在时钟信号作用下根据来自输入端的输入信号向第二输出端和输出模块输出与输入信号同相、且比输入信号延迟半个时钟周期的触发信号；
输出模块用于在时钟信号作用下在触发信号的触发下向第一输出端输出与输入信号反相、且比输入信号延迟半个时钟周期的输出信号；
第一输出端所输出信号的工作电压由直流电源提供。
从图1中可以看出，触发模块实际的功能就基本等同于移位寄存器的功能，而输出模块则是在此基础上实现二级输出。连接关系上，触发模块与输 入相连，并输出触发信号给第二输出端和输出模块，而输出模块受触发信号的触发，就会向第一输出端输出输出信号。当然，整个过程都是在时钟信号的作用下进行的，结合移位寄存器自身的功能也可以推导出，这里所说的输出触发信号和输出信号实际上指的是按照时钟信号的时间顺序，将与输入脉冲同样形状的同相或反相输出脉冲输出，两者只是在时钟信号的时间顺序上有所差别，而脉冲的形状是同相或反相的。
而且，这里所说的脉冲狭义上来讲只是指单脉冲信号(即低-高-低或高-低-高的单一方波波形)，但实际上所有波形都可以由若干个单脉冲信号叠加而成，所以两者并无实质上的区别，广义上而言可以是任意形状的高低电平波形。
由于本公开实施例采用了直流电源来提供第一输出端的工作电压，所以第一输出端所输出的信号并不会受到时钟交流脉冲信号波段的影响，进而其可以保证输出信号的稳定性。在用于显示装置中的栅线驱动电路中时，这一特点可以保证显示像素的稳定性。
为了进一步说明本公开实施例中示例性的实施方式，这里分别展示一种可替换的触发模块和一种可替换的输出模块。
图2示出本公开一个实施例中移位寄存器的电路结构图。参见图2，触发模块包括六个开关元件M1至M6和一个电容Cst，其中：
第一开关元件M1的第二端与输入端STV相连，其第一端与第二开关元件M2的第一端、电容Cst的第一端、以及第六开关元件M6的控制端相连；
第二开关元件M2的第二端与第三开关元件M3的控制端相连；
第三开关元件M3的第一端与第四开关元件M4的第二端、以及第五开关元件M5的控制端相连；
第四开关元件M4的第一端与其控制端相连；
第五开关元件M5的第一端与电容的第二端、以及第六开关元件M6的第二端相连，并与第二输出端OUTPUT和输出模块相连。
具有该结构的触发模块可以直接输出与输入信号同相、且比输入信号延迟半个时钟周期的触发信号，而且只使用了六个开关元件和一个电容，并能与显示面板制作工艺相适应。该触发模块的具体的电路时序将在下文中介绍。
对应地，在第三开关元件M3的第二端接高电平的工作电压VGH，在第四开关元件M4的控制端和第一端接低电平的工作电压VGL，以保证整体电路的 一致性。
与电路设计中的常用习惯一致，使这里的时钟信号包括第一时钟信号CLK1和第二时钟信号CLK2，两者一般为时刻反相、频率固定的高低电平交替出现的方波脉冲信号。对应地，将第一时钟信号CLK1接于第一开关元件M1的控制端，将第二时钟信号CLK2接于第二开关元件M2的控制端和第六开关元件M6的第一端。
以上为触发模块的示例性电路结构，下面继续介绍一种可以和该触发模块配合使用的输出模块。
参见图2，该输出模块包括四个开关元件M7至M10，其中：
第七开关元件M7的第一端与触发模块相连，其第二端与第八开关元件M8的控制端相连；
第八开关元件M8的第一端与第十开关元件M10的第一端相连，并与第一输出端STV2相连；
第十开关元件M10的控制端与第九开关元件M9的第二端相连；
第九开关元件M9的控制端与第一端相连，并与第十开关元件M10的第二端相连。
具有该结构的输出模块可以直接输出与输入信号反相、且比输入信号延迟半个时钟周期的输出信号，而且只使用了四个开关元件，并能与显示面板制作工艺相适应。该输出模块的具体的电路时序将在下文中介绍。
对应地，在第八开关元件M8的第二端接高电平的工作电压VGH，在第九开关元件M9的控制端和第一端接低电平的工作电压VGL，以保证整体电路的一致性，与上述特征对应，这里的工作电压VGH和VGL就是由直流电源所提供的，以消除交流脉冲信号对输出的影响。
整体电路结构中，第一时钟信号CLK1接于第一开关元件M1的控制端，第二时钟信号CLK2接于第二开关元件M2的控制端、第六开关元件M6的第一端、以及第七开关元件M7的控制端。当中只有M7是属于输出模块这一部分的，可见时钟信号并未直接接于输出模块中的输出信号通路中，而使通过M7的控制端与整体的输出信号通路隔开，因此输出信号不会受到时钟交流脉冲信号的影响。
可替换地，采用P沟道型薄膜晶体管(Thin Film Transistor，TFT)作为开关元件，其控制端即为TFT的栅极，第一端即TFT的源极，第二端即TFT 的漏极。当然也可以选用N沟道型的薄膜晶体管，此时制端即为TFT的栅极，第一端即TFT的漏极，第二端即TFT的源极。
图3是本公开一个实施例中移位寄存器的工作时序图。对于上述电路应用到TFT显示领域的情形(多个移位寄存器级联，并将第一输出端STV2用于本行的输出，将第二输出端OUTPUT用于下一行和本行输出的触发)，其整体的工作时序图可以如图3所示(STV对应于上述输入信号、STV2对应于上述触发信号、OUTPUT对应于上述输出信号)。如图3所示，该工作时序图包括四个阶段，分别以1、2、3、4表示第一阶段至第四阶段。
1、第一阶段：STV和CLK1开启，STV信号通过晶体管M1输入到晶体管M6的栅极，并且通过电容Cst进行电位保持，同时STV信号使晶体管M6开启，将CLK2的关闭信号(高压信号)通过晶体管M6传输到STV2线上。此时由晶体管M3和M4构成的反相器中，由于晶体管M3关闭，反相器输出由晶体管M4控制的开启电位(低压信号)，使晶体管M5开启，将VGH的高压信号也输出给STV2的线上。同时由CLK2控制的晶体管M7处于关闭状态，使得由晶体管M8，M9，M10构成的反相器结构中的M8处于关闭状态，反相器输出由M9和M10控制的VGL低压信号，该信号传输给本级OUTPUT。
2、第二阶段：CLK1变成高压关断信号，CLK2变成低压开启信号。由于晶体管M6的栅极上低压信号通过电容Cst进行保持，将晶体管M6开启，使CLK2的低压信号通过晶体管M6传输到STV2线。同时由CLK2控制的晶体管M2也开启，将M6栅极低压信号通过M2传输到晶体管M3的栅极，使晶体管M3开启，此时由M3和M4构成的反相器边输出VGH信号，该信号通过M3传输到M5的栅极，使M5处于关闭状态。这样一级结构便输出低压开启信号，该信号一方面是下行移位寄存器的开启信号，同时也是本行二级结构的出发信号。当CLK2的低压信号传输到STV2时，由CLK2控制的M7开启，将低压信号传输到M8的栅极，此时由M8，M9，M10构成的反相器便输出由M8控制的VGH高压信号。
3、第三阶段：CLK1变成低压开始信号，STV此时为高压关断信号。由CLK1控制的M1开启，将高压STV信号传输到M6的栅极端，并且通过电容Cst进行保持。使得M6处于关断状态。此时由M3，M4，构成的反相器输出VGL信号，该信号使M5开启，将VGH信号传输给STV2线上。此时由M8，M9，M10构成的反相器输出VGL信号，该信号传输到OUTPUT上。
4、第四阶段：CLK2变成开启信号，同样使得由M3和M4构成的反相器输出VGL给M5栅极，使VGH信号通过M5传输给STV2线上。由M8，M9，M10构成的反相器依旧输出VGL的低压信号。后续的CLK1，CLK2时均是在重复第三和第四阶段动作，这样一级输出保持为VGH高压信号，二级输出保持为VGL的低压信号。
可见，上述电路可以实现移位寄存器的移位输出功能，具体应用到这里的栅极驱动电路中，可以使触发和输出相互分离。而且由于提供本行栅线信号的第一输出端是使用直流电源提供工作电压的，所以其输出不会受到交流脉冲信号波动的影响，输出信号会更加稳定，从而显示像素也会更加稳定。
当然，上述电路仅作为示例，其移位寄存器的使用环境、使用方式、具体触发模块的结构以及输出模块的结构都可以依照本公开实施例进行调整，其显然没有脱离本公开实施例技术方案的精神和范围。
基于同样的公开思路，本公开实施例提供了一种阵列基板，该阵列基板包括前述的任意一种移位寄存器。举例而言，其可以将移位寄存器应用在阵列基板的栅线驱动电路中，以多个级联的移位寄存器向像素单元提供栅线驱动信号。在此情境下，每级移位寄存器的输入端接上一级移位寄存器的第二输出端或栅线驱动信号，每级移位寄存器的第一输出端接本行的栅线驱动信号输出。
如前所述，由于提供本行栅线信号的第一输出端是使用直流电源提供工作电压的，所以其输出不会受到交流脉冲信号波动的影响，输出信号会更加稳定，从而显示像素也会更加稳定。
当然，基于同样的思路也可以在阵列基板的其他部分使用该移位寄存器，而且移位寄存器的使用方式也不仅限于同样的移位寄存器级联，也可以与其他电路结构进行替换或是组合。
基于相同的公开构思，本公开实施例提出了一种显示装置，该显示装置包括前述的任意一种阵列基板，该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上所述，本公开提供一种移位寄存器、阵列基板及显示装置，通过将移位寄存器中触发和输出相互分离，并以直流电源作为工作电压，使其不会受到交流脉冲信号波动的影响，从而可以提高输出信号及显示像素的稳定 性。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
本申请要求于2014年8月22日递交的中国专利申请第201410418847.1号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (10)

  1. 一种移位寄存器，包括触发模块、输出模块、输入端、第一输出端和第二输出端，其中：
    所述触发模块用于在时钟信号作用下根据来自输入端的输入信号向所述第二输出端和输出模块输出与所述输入信号同相、且比所述输入信号延迟半个时钟周期的触发信号；
    所述输出模块用于在时钟信号作用下在所述触发信号的触发下向所述第一输出端输出与所述输入信号反相、且比所述输入信号延迟半个时钟周期的输出信号；
    所述第一输出端所输出信号的工作电压由直流电源提供。
  2. 根据权利要求1所述的移位寄存器，其中，所述触发模块包括六个开关元件和一个电容，其中：
    第一开关元件的第二端与所述输入端相连，其第一端与第二开关元件的第一端、电容的第一端、以及第六开关元件的控制端相连；
    所述第二开关元件的第二端与第三开关元件的控制端相连；
    所述第三开关元件的第一端与第四开关元件的第二端、以及第五开关元件的控制端相连；
    所述第四开关元件的第一端与其控制端相连；
    所述第五开关元件的第一端与电容的第二端、以及第六开关元件的第二端相连，并与所述第二输出端和所述输出模块相连。
  3. 根据权利要求2所述的移位寄存器，其中，所述第三开关元件的第二端接高电平的工作电压，所述第四开关元件的控制端和第一端接低电平的工作电压。
  4. 根据权利要求2或3所述的移位寄存器，其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第一时钟信号接于所述第一开关元件的控制端，所述第二时钟信号接于所述第二开关元件的控制端和所述第六开关元件的第一端。
  5. 根据权利要求1-4之一所述的移位寄存器，其中，所述输出模块包括四个开关元件：第七至第十开关元件，其中：
    第七开关元件的第一端与所述触发模块相连，其第二端与第八开关元件的控制端相连；
    所述第八开关元件的第一端与第十开关元件的第一端相连，并与所述第一输出端相连；
    所述第十开关元件的控制端与第九开关元件的第二端相连；
    所述第九开关元件的控制端与第一端相连，并与所述第十开关元件的第二端相连。
  6. 根据权利要求5所述的移位寄存器，其中，所述第八开关元件的第二端接高电平的工作电压，所述第九开关元件的控制端和第一端接低电平的工作电压。
  7. 根据权利要求5或6所述的移位寄存器，其中，所述时钟信号包括第一时钟信号和第二时钟信号，所述第二时钟信号接于所述第七开关元件的控制端。
  8. 根据权利要求1至7中任意一项所述的移位寄存器，其中，所述开关元件为P沟道型薄膜晶体管。
  9. 一种阵列基板，其中，所述阵列基板包括如权利要求1至8中任意一项所述的移位寄存器。
  10. 一种显示装置，其中，所述显示装置包括如权利要求9所述的阵列基板。
PCT/CN2014/092512 2014-08-22 2014-11-28 移位寄存器、阵列基板及显示装置 WO2016026233A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/772,224 US9805638B2 (en) 2014-08-22 2014-11-28 Shift register, array substrate and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410418847.1 2014-08-22
CN201410418847.1A CN104299554B (zh) 2014-08-22 2014-08-22 移位寄存器、阵列基板及显示装置

Publications (1)

Publication Number Publication Date
WO2016026233A1 true WO2016026233A1 (zh) 2016-02-25

Family

ID=52319256

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/092512 WO2016026233A1 (zh) 2014-08-22 2014-11-28 移位寄存器、阵列基板及显示装置

Country Status (3)

Country Link
US (1) US9805638B2 (zh)
CN (1) CN104299554B (zh)
WO (1) WO2016026233A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104361860B (zh) * 2014-11-19 2017-02-22 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路以及显示装置
CN104900192B (zh) * 2015-07-01 2017-10-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106057143A (zh) * 2016-05-30 2016-10-26 京东方科技集团股份有限公司 移位寄存器及其操作方法、栅极驱动电路和显示装置
CN108376533B (zh) * 2018-03-15 2020-02-07 广东工业大学 一种单机移位寄存器以及一种行驱动电路
KR20210137705A (ko) * 2020-05-11 2021-11-18 주식회사 엘엑스세미콘 화소의 구동을 위한 클럭생성장치 및 이를 포함하는 디스플레이장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040239608A1 (en) * 2001-10-16 2004-12-02 Woo-Suk Chung Shift register and liquid crystal display having the same
CN101202114A (zh) * 2006-12-13 2008-06-18 中华映管股份有限公司 移位寄存器以及使用其的驱动电路与显示装置
CN102629463A (zh) * 2012-03-29 2012-08-08 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
KR20140079106A (ko) * 2012-12-18 2014-06-26 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985905A (en) * 1988-09-30 1991-01-15 Advanced Micro Devices, Inc. Two phase CMOS shift register bit for optimum power dissipation
KR100574363B1 (ko) * 2002-12-04 2006-04-27 엘지.필립스 엘시디 주식회사 레벨 쉬프터를 내장한 쉬프트 레지스터
WO2005122178A1 (en) * 2004-06-14 2005-12-22 Semiconductor Energy Laboratory Co., Ltd. Shift register and semiconductor display device
CN100489932C (zh) * 2006-01-17 2009-05-20 奇晶光电股份有限公司 平面显示器、显示器驱动装置以及移位暂存器
KR101319356B1 (ko) * 2006-06-09 2013-10-16 엘지디스플레이 주식회사 액정표시장치의 쉬프트 레지스터 및 이의 구동방법
KR101375863B1 (ko) * 2007-03-08 2014-03-17 삼성디스플레이 주식회사 표시장치 및 이의 구동방법
KR20080113567A (ko) * 2007-06-25 2008-12-31 삼성전자주식회사 표시 장치
JP5429604B2 (ja) * 2009-02-24 2014-02-26 株式会社リコー シフトレジスタ用回路並びにこれを用いたシフトレジスタ及び画像表示装置
WO2010146740A1 (ja) * 2009-06-17 2010-12-23 シャープ株式会社 表示駆動回路、表示装置及び表示駆動方法
EP2444958B1 (en) * 2009-06-17 2017-09-20 Sharp Kabushiki Kaisha Shift resister, display-driving circuit, displaying panel, and displaying device
KR101863332B1 (ko) * 2011-08-08 2018-06-01 삼성디스플레이 주식회사 주사 구동부, 이를 포함하는 표시 장치 및 그 구동 방법
CN103236273B (zh) * 2013-04-16 2016-06-22 北京京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN103489425B (zh) * 2013-10-12 2015-11-25 合肥京东方光电科技有限公司 电平转换电路、阵列基板及显示装置
CN106033683A (zh) * 2015-03-20 2016-10-19 南京瀚宇彩欣科技有限责任公司 移位寄存装置和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040239608A1 (en) * 2001-10-16 2004-12-02 Woo-Suk Chung Shift register and liquid crystal display having the same
CN101202114A (zh) * 2006-12-13 2008-06-18 中华映管股份有限公司 移位寄存器以及使用其的驱动电路与显示装置
CN102629463A (zh) * 2012-03-29 2012-08-08 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
KR20140079106A (ko) * 2012-12-18 2014-06-26 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치

Also Published As

Publication number Publication date
US9805638B2 (en) 2017-10-31
US20160284263A1 (en) 2016-09-29
CN104299554A (zh) 2015-01-21
CN104299554B (zh) 2017-07-18

Similar Documents

Publication Publication Date Title
EP3369090B1 (en) Shift register, goa circuit containing the same, and related display device
WO2016101618A1 (zh) 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
US9886927B2 (en) Display device, TFT substrate and GOA driving circuit
US10140910B2 (en) Shift register, a gate line driving circuit, an array substrate and a display apparatus
US10262572B2 (en) Gate-on-array driving unit, gate-on-array driving method, gate-on-array driving circuit, and display device
US9269455B2 (en) Shift register unit, gate driving circuit, array substrate and display apparatus
US20180374410A1 (en) Shift Register, Method for Driving the Same, and Display Device
EP3200182B1 (en) Shift register unit, shift register, gate drive circuit and display device
US9767916B2 (en) Shift register and display apparatus
WO2016188287A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2016026233A1 (zh) 移位寄存器、阵列基板及显示装置
US11200860B2 (en) Shift register unit, gate driving circuit and driving method thereof
WO2019091168A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2013135061A1 (zh) 栅极驱动电路及显示器
US10955966B2 (en) Touch electrode driving circuit, touch electrode driver and touch display device
KR20130130721A (ko) 시프트 레지스터, 구동 회로, 및 디스플레이 장치
WO2016161727A1 (zh) 移位寄存器单元及其驱动方法、阵列基板栅极驱动装置、以及显示面板
TWI521490B (zh) 顯示面板與閘極驅動器
US20180330667A1 (en) Gate Driving Unit, Gate Driving Circuit, Display Driving Circuit and Display Device
US10515601B2 (en) GOA circuit for preventing clock signals from missing
US9159447B2 (en) Shift register unit, shift register, array substrate and display apparatus
US9818360B2 (en) Liquid crystal display and control method for the same
WO2019080619A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2018205653A1 (zh) 公共电压补偿电路单元、显示面板、显示装置和显示面板的公共电压补偿方法
KR102210845B1 (ko) Goa 회로

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14772224

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14900087

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC

122 Ep: pct application non-entry in european phase

Ref document number: 14900087

Country of ref document: EP

Kind code of ref document: A1