WO2016008232A1 - 像素电路和显示装置 - Google Patents

像素电路和显示装置 Download PDF

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Publication number
WO2016008232A1
WO2016008232A1 PCT/CN2014/089763 CN2014089763W WO2016008232A1 WO 2016008232 A1 WO2016008232 A1 WO 2016008232A1 CN 2014089763 W CN2014089763 W CN 2014089763W WO 2016008232 A1 WO2016008232 A1 WO 2016008232A1
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Prior art keywords
unit
sub
switch unit
signal
control
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PCT/CN2014/089763
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English (en)
French (fr)
Inventor
杨盛际
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/777,942 priority Critical patent/US10147362B2/en
Publication of WO2016008232A1 publication Critical patent/WO2016008232A1/zh
Priority to US16/179,239 priority patent/US10943545B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present disclosure relates to a pixel circuit and a display device.
  • OLED display is one of the hotspots in the field of flat panel display research. Compared with liquid crystal display, OLED display has low energy consumption, low production cost, self-illumination, wide viewing angle and fast response. Etc. At present, OLED displays in mobile phones, personal digital assistants (PDAs), digital cameras and other display fields have begun to replace the traditional liquid crystal display (LCD). Pixel driver circuit design is the core technology content of OLED display, which has important research significance.
  • TFT-LCD Thin Film Transistor
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • a pixel circuit generally corresponds to one sub-pixel, and each pixel circuit includes at least one data line, one voltage line for supplying an operating voltage, and a plurality of scanning signal lines, which leads to a complicated manufacturing process and is disadvantageous for Reduce the pixel pitch.
  • At least one embodiment of the present disclosure reduces the number of signal lines for a pixel circuit in a display device, reduces the cost of the integrated circuit, and increases the pixel density of the display device.
  • a pixel circuit including three sub-pixel circuits and a power supply circuit, the three sub-pixel circuits sharing a data line;
  • the power supply circuit is connected to the first level terminal, the first signal control line and the sub-pixel circuit, and the power supply circuit is configured to pass the first level end to the said signal under the signal control of the first signal control line
  • the sub-pixel circuit provides a first level
  • the sub-pixel circuit is connected to the power supply circuit and the data line for use in the power supply circuit
  • the first level and the data signal of the data line are provided to display gray scale under control.
  • the power supply circuit includes: a first switch unit, a control end of the first switch unit is connected to the first signal control line, and a first end of the first switch unit is connected to the first level end
  • the second end of the first switching unit is connected to the three sub-pixel circuits for providing a first level of the first level terminal to the three sub-pixel circuits under the signal control of the first signal control line.
  • the power supply circuit includes: a first switch unit, a second switch unit, and a third switch unit;
  • a control end of the first switch unit is connected to the first signal control line, a first end of the first switch unit is connected to the first level end, and a second end of the first switch unit is connected to three sub-pixels a first sub-pixel circuit in the circuit for providing a first level of the first level terminal to the first sub-pixel circuit under signal control of the first signal control line.
  • a control end of the second switch unit is connected to the first signal control line, a first end of the second switch unit is connected to the first level end, and a second end of the second switch unit is connected to three sub-pixels a second sub-pixel circuit in the circuit for providing a first level of the first level terminal to the second sub-pixel circuit under signal control of the first signal control line.
  • a control end of the third switch unit is connected to the first signal control line, a first end of the third switch unit is connected to the first level end, and a second end of the third switch unit is connected to three sub-pixels a third sub-pixel circuit in the circuit for providing a first level of the first level terminal to the third sub-pixel circuit under signal control of the first signal control line.
  • each of the sub-pixel circuits includes: four switch units, a drive unit, an energy storage unit, and an electroluminescence unit, which are fourth to seventh switch units, respectively;
  • the control end of the fourth switch unit inputs a first scan signal, the first end of the fourth switch unit is connected to the second level end; the second end of the fourth switch unit is connected to the first pole of the energy storage unit; the fourth switch unit And a signal for writing the second level end to the first pole of the energy storage unit under the control of the first scan signal;
  • a control signal of the fifth switch unit inputs a third scan signal, a first end of the fifth switch unit is connected to the data line; and a fifth switch unit is configured to: signal the data line under the control of the third scan signal The second end output of the fifth switching unit;
  • a second scanning signal is input to the control end of the sixth switching unit, a first end of the sixth switching unit is connected to the first pole of the energy storage unit, and a second end of the sixth switching unit is connected to the fifth switching unit
  • the second end of the sixth switch unit is configured to write a signal of the data line to the first pole of the energy storage unit under the control of the second scan signal to couple the second pole of the energy storage unit Level;
  • a control end of the driving unit is connected to the second end of the sixth switching unit, and an input end of the driving unit is connected to the second pole of the energy storage unit, and the driving unit is configured to output a driving current;
  • the control end of the seventh switch unit inputs a fourth scan signal, the first end of the seventh switch unit is connected to the output end of the drive unit, and the second end of the seventh switch unit is connected to the second level end,
  • the seventh switching unit is configured to control the driving current to be input to the first pole of the electroluminescent unit under the control of the fourth scanning signal;
  • a first pole of the electroluminescent unit is connected to an output end of the driving unit, a second pole of the electroluminescent unit is connected to the second level end, and an electroluminescent unit is used for controlling the driving current
  • the gray scale is displayed below;
  • the second pole of the energy storage unit is connected to the power supply circuit, and the energy storage unit is configured to store a signal of the data line and a threshold voltage of the driving unit.
  • the first sub-pixel circuit, the second sub-pixel circuit, and the second sub-pixel circuit share a first scan line to input a first scan signal to a control end of the fourth switch unit.
  • a control end of the fifth switching unit of the first sub-pixel circuit is connected to the first scan line, and the first scan signal and the third scan signal of the first sub-pixel circuit are in the same timing.
  • the first sub-pixel circuit, the second sub-pixel circuit and the second sub-pixel circuit share a second scan line to the control end of the sixth switch unit and the first
  • the control terminal of the seven-switch unit inputs a second scan signal and a fourth scan signal, wherein the second scan signal and the fourth scan signal have the same timing.
  • a control end of the fifth switching unit of the third sub-pixel circuit is connected to the second scan line, and a third switch circuit is input to the control terminal of the fifth switch unit.
  • the third scan signal is the same as the second scan signal input to the control terminal of the sixth switching unit.
  • the sub-pixel circuit further connects the second signal control line and the first level terminal, wherein each of the sub-pixel circuits comprises: four switch units respectively being eighth to eleventh switching units , a drive unit, an energy storage unit, and an electroluminescent unit;
  • the first pole of the energy storage unit is connected to the first level end for writing the first level of the first level end to the first pole of the energy storage unit;
  • the control end of the eighth switch unit is connected to the second signal control line, the first end of the eighth switch unit is connected to the second pole of the energy storage unit, and the second end of the eighth switch unit is connected to the second level end,
  • the eight-switch unit is configured to write the second level of the second level terminal to the second pole of the energy storage unit under the signal control of the second signal control line;
  • the control end of the ninth switch unit inputs a second scan signal, the first end of the ninth switch unit is connected to the data line, the second end of the ninth switch unit is connected to the output end of the drive unit, and the ninth switch unit Generating a signal of the data line to an output end of the driving unit under the control of the second scan signal;
  • the control end of the tenth switch unit inputs a first scan signal, the first end of the tenth switch unit is connected to the second pole of the energy storage unit, and the second pole of the tenth switch unit is connected to the input end of the drive unit and the power supply a circuit, the tenth switch unit is configured to write a signal of the data line and a threshold voltage of the driving unit to the second pole of the energy storage unit;
  • a control end of the driving unit is connected to the first end of the tenth switching unit for outputting a driving current at the output end;
  • a control end of the eleventh switch unit is connected to the first signal control line, a first end of the eleventh switch unit is connected to an output end of the driving unit, and an eleventh switch unit is used for the first signal Controlling the drive current to input the first pole of the electroluminescent unit under signal control of the control line;
  • a first pole of the electroluminescent unit is connected to a second end of the eleventh switch unit, a second pole of the electroluminescent unit is connected to the second level end, and the electroluminescent unit is used for
  • the gray scale is displayed under the control of the drive current.
  • control end of the ninth switch unit and the control end of the tenth switch unit share one scan line, so that the first scan signal and the second scan signal have the same timing.
  • the sub-pixel circuit further connects the second signal control line and the third signal control line, wherein each of the sub-pixel circuits comprises: four switch units respectively being the twelfth to fifteenth switch units , a drive unit, an energy storage unit, and an electroluminescent unit;
  • the control end of the twelfth switch unit inputs a first scan signal, the first end of the twelfth switch unit is connected to the data line, and the second end of the twelfth switch unit is connected to the first pole of the energy storage unit
  • the twelfth switch unit is configured to write the signal of the data line to the first pole of the energy storage unit under the control of the first scan signal;
  • a control end of the thirteenth switch unit is connected to the second signal control line, a first end of the thirteenth switch unit is connected to a second end of the twelfth switch unit, and a third end of the thirteenth switch unit The second end is connected to the second level end, and the thirteenth switch unit is configured to write the second level of the second level end to the first pole of the energy storage unit under the signal control of the second signal control line ;
  • the control end of the fourteenth switch unit is connected to the second signal control line, the first end of the fourteenth switch unit is connected to the second pole of the energy storage unit, and the first end is connected to the output end of the drive unit.
  • a four-switch unit for writing a first level and a threshold voltage of the driving unit to the second pole of the energy storage unit under the control of the second signal control line;
  • An input end of the driving unit is connected to the power supply circuit, a control end of the driving unit is connected to a second pole of the energy storage unit, and an output end of the driving unit is connected to a second end of the fourteenth switching unit
  • the driving unit is configured to output a driving current at the output end;
  • the control end of the fifteenth switch unit is connected to the third signal control line, the first end of the fifteenth switch unit is connected to the output end of the drive unit, and the fifteenth switch unit is used for the third signal control line Controlling the driving current to be input to the first pole of the electroluminescent unit;
  • a first pole of the electroluminescent unit is connected to a second end of the fifteenth switch unit, a second pole is connected to the second level end, and the electroluminescent unit is used under the control of the driving current Show grayscale.
  • the switching unit and the driving unit are thin film transistors, and the control ends of the respective switching units are gates of the thin film transistors, the first ends of the respective switching units are the sources of the thin film transistors, and the second ends of the respective switching units are thin film transistors.
  • the input end of the driving unit is the source of the thin film transistor, the control end of the driving unit is the gate of the thin film transistor, and the output end of the driving unit is the drain of the thin film transistor.
  • the energy storage unit is a capacitor.
  • the electroluminescent unit is an organic light emitting diode.
  • a display device including any of the above pixel circuits is provided.
  • the three sub-pixel circuits of the pixel circuit are located in the same pixel.
  • the three sub-pixel circuits are located on the same side of the data line.
  • three sub-pixel circuits of the pixel circuit are located in two adjacent pixels, wherein adjacent first sub-pixel circuits and second sub-pixel circuits of the three sub-pixel circuits are located in the first pixel, The third sub-pixel circuit is located in the second pixel;
  • first sub-pixel circuit of the three sub-pixel circuits is located in the first pixel
  • adjacent second sub-pixel circuit and the third sub-pixel circuit are located in the second pixel, wherein the first pixel and the second pixel phase adjacent.
  • a data line is located between the first pixel and the second pixel.
  • At least one embodiment of the present disclosure provides a pixel circuit and a display device capable of reducing a display device by sharing a data line by three adjacent sub-pixel circuits while supplying an operating voltage to three sub-pixel circuits through a first level terminal.
  • the number of signal lines used in the pixel circuit reduces the cost of the integrated circuit while increasing the pixel density of the display device.
  • FIG. 1 is a block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 3 is a timing diagram of key signals in the pixel circuit provided in FIG. 2 according to the present disclosure
  • FIG. 4 is a schematic diagram of current flow in the w1 phase of the pixel circuit provided in FIG. 2 according to the present disclosure
  • FIG. 5 is a schematic diagram of current flow in the w2 phase of the pixel circuit provided in FIG. 2 according to the present disclosure
  • FIG. 6 is a schematic diagram of current flow in the w3 phase of the pixel circuit provided in FIG. 2 according to the present disclosure
  • FIG. 7 is a schematic diagram of current flow in the w4 phase of the pixel circuit provided in FIG. 2 according to the present disclosure
  • FIG. 8 is a schematic diagram of current flow in the w5 phase of the pixel circuit provided in FIG. 2 according to the present disclosure
  • FIG. 9 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a pixel circuit according to still another embodiment of the present disclosure.
  • FIG. 11 is a timing diagram of key signals in a pixel circuit as disclosed in FIG. 10;
  • FIG. 12 is a schematic diagram of current flow in the w1 phase of the pixel circuit provided in FIG. 10 according to the present disclosure
  • FIG. 13 is a schematic diagram of current flow in the w2 phase of the pixel circuit provided in FIG. 10 according to the present disclosure
  • FIG. 14 is a schematic diagram of current flow in the w3 phase of the pixel circuit provided in FIG. 10 according to the present disclosure
  • FIG. 15 is a schematic diagram of current flow in the w4 phase of the pixel circuit provided in FIG. 10 according to the present disclosure
  • FIG. 16 is a schematic diagram of current flow in the w5 phase of the pixel circuit provided in FIG. 10 according to the present disclosure
  • FIG. 17 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 19 is a timing diagram of key signals in the pixel circuit provided in FIG. 18 according to the present disclosure.
  • FIG. 20 is a schematic diagram of current flow in the w1 phase of the pixel circuit provided in FIG. 18 according to the present disclosure
  • FIG. 21 is a schematic diagram of current flow in the w2 phase of the pixel circuit provided in FIG. 18 according to the present disclosure
  • FIG. 22 is a schematic diagram of current flow in the w3 phase of the pixel circuit provided in FIG. 18 according to the present disclosure
  • FIG. 23 is a schematic diagram of current flow in the w4 phase of the pixel circuit provided in FIG. 18 according to the present disclosure
  • FIG. 24 is a schematic diagram showing current flow in the w5 phase in the pixel circuit provided in FIG. 18 according to the present disclosure
  • FIG. 25 is a schematic structural diagram of a pixel circuit according to still another embodiment of the present disclosure.
  • 26 is a schematic diagram of a positional relationship between a pixel circuit and a pixel in a display device according to an embodiment of the present disclosure
  • FIG. 27 is a schematic diagram showing a positional relationship between a pixel circuit and a pixel in a display device according to an embodiment of the present disclosure
  • FIG. 28 is a schematic diagram of a positional relationship between a pixel circuit and a pixel in a display device according to an embodiment of the present disclosure.
  • the switching transistor and the driving transistor used in all the embodiments of the present disclosure may be a thin film transistor or a field effect transistor or other devices having the same characteristics. Since the source and the drain of the switching transistor used herein are symmetrical, the source thereof, The drains are interchangeable. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure includes a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off.
  • the driving transistor includes a P type and an N type, wherein the P type driving transistor has a low level at the gate voltage (the gate voltage is less than the source voltage), And the absolute value of the voltage difference of the gate source is greater than the threshold voltage in an amplified state or a saturated state; wherein the gate voltage of the N-type driving transistor is at a high level (the gate voltage is greater than the source voltage), and the gate source When the absolute value of the differential pressure is greater than the threshold voltage, it is amplified State or saturated state.
  • FIG. 1 is a block diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit includes: three sub-pixel circuits (P1, P2, and P3), and a power supply circuit VL, the three sub-pixel circuits share a data line Data;
  • the power supply circuit VL is connected to a first level terminal VA, a first signal control line EM1 and the sub-pixel circuits (P1, P2 and P3), and the power supply circuit VL is used for a signal at the first signal control line EM1 Controlling, by the first level terminal VA, the first level to the sub-pixel circuits (P1, P2, and P3);
  • the sub-pixel circuits (P1, P2, and P3) are connected to the power supply circuit VL and the data line Data for displaying under the control of the first level provided by the power supply circuit VL and the data signal of the data line Data. Grayscale.
  • the pixel circuit provided by the embodiment of the present disclosure can reduce the pixel for the pixel device in the display device by sharing the data line with the adjacent three sub-pixel circuits while providing the working voltage to the three sub-pixel circuits through one first level terminal.
  • the number of signal lines reduces the cost of the integrated circuit while increasing the pixel density of the display device.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes three sub-pixel circuits (P1, P2, and P3), and a power supply circuit VL, the three sub-pixel circuits share a data line Data;
  • the power supply circuit includes a first switching unit T11, a second switching unit T21 and a third switching unit T31;
  • the control terminal of T11 is connected to the first signal control line EM1, the first end of T11 is connected to the first level terminal VA, and the second end of T11 is connected to the first sub-pixel circuit P1 of the three sub-pixel circuits for the first
  • the signal of the signal control line EM1 is controlled to supply the first level of the first level terminal VA to the first sub-pixel circuit P1.
  • the control terminal of T21 is connected to the first signal control line EM1, the first end of T21 is connected to the first level terminal VA, and the second end of T21 is connected to the second sub-pixel circuit P2 of the three sub-pixel circuits for
  • the signal of the first signal control line EM1 is controlled to provide a first level of the first level terminal VA to the second sub-pixel circuit P2.
  • the control end of the T31 is connected to the first signal control line EM1, and the first end of the T31 is connected to the The first level terminal VA, the second end of the T31 is connected to the third sub-pixel circuit P3 of the three sub-pixel circuits for providing the third sub-pixel circuit P3 under the signal control of the first signal control line EM1.
  • the first level of a level terminal VA is connected to the first signal control line EM1
  • each of the sub-pixel circuits includes: four switching units, a driving unit, an energy storage unit, and an electroluminescent unit; wherein, in order to distinguish, four switching units included in P1 are sequentially The fourth switching unit T12, the fifth switching unit T13, the sixth switching unit T14, and the seventh switching unit T15, the driving unit is D16, the energy storage unit is C1, and the electroluminescent unit is O1; four included in P2
  • the switch unit is, in order, the fourth switch unit T22, the fifth switch unit T23, the sixth switch unit T24, the seventh switch unit T25, the drive unit is D26, the energy storage unit is C2, and the electroluminescent unit is O2;
  • the four switching units are sequentially the fourth switching unit T32, the fifth switching unit T33, the sixth switching unit T34, the seventh switching unit T35, the driving unit is D36, the energy storage unit is C3, and the electroluminescent unit is O3;
  • control terminal of T12 inputs the first scan signal S1, the first end of T12 is connected to the second level terminal VB; the second end of T12 is connected to the first pole of the energy storage unit C1; and T12 is used for the first scan signal Writing the signal of the second level terminal VB to the first pole of the energy storage unit C1 under the control of S1;
  • the control terminal of T13 inputs a third scan signal S3, and the first end of T13 is connected to the data line Data; T13 is for using the signal of the data line Data at the second of the T13 under the control of the third scan signal S3. Terminal output
  • the control terminal of T14 inputs a second scan signal S2, the first end of T14 is connected to the first pole of the energy storage unit C1, the second end of T14 is connected to the second end of the T13, and T14 is used for the second end.
  • the signal of the data line Data is written into the first pole of the energy storage unit C1 under the control of the scan signal S2 to couple the level of the second pole of the energy storage unit C1;
  • the control end of the driving unit D16 is connected to the second end of the T14, the input end of the driving unit D16 is connected to the second pole of the energy storage unit C1; D16 is used for outputting the driving current;
  • the control terminal of T15 inputs a fourth scan signal S4, the first end of T15 is connected to the output end of the driving unit D16, the second end is connected to the second level end VB; T15 is used for the fourth scan signal S4 Controlling the driving current to be input to the first pole of the electroluminescent unit O1;
  • a first pole of the electroluminescent unit O1 is connected to an output end of the driving unit D16, and a second pole of the electroluminescent unit O1 is connected to the second level terminal VB; O1 is used for the driving current Display gray scale under control;
  • the second pole of the energy storage unit C1 is connected to the power supply circuit VL; C1 is used to store the signal of the data line Data and the threshold voltage of the driving unit D16.
  • the first sub-pixel circuit P1, the second sub-pixel circuit P2, and the third sub-pixel circuit P3 share a first scan line Scan1 to the fourth switch unit (T12, T22) And the control terminal of T32) inputs the first scan signal S1. Since the three sub-pixel units share one scan line, the number of signal lines of the pixel circuit can be reduced to a certain extent, and the cost of the integrated circuit is reduced.
  • the control end of the fifth switching unit T13 of the first sub-pixel circuit P1 is connected to the first scan line Scan1, and the timings of the first scan signal S1 and the third scan signal S3 of the first sub-pixel circuit P1 are the same. Since the first scan line Scan1 is shared, the number of signal lines of the pixel circuit can be reduced, and the cost of the integrated circuit can be reduced.
  • the first sub-pixel circuit P1, the second sub-pixel circuit P2, and the third sub-pixel circuit share a second scan line Scan2 to the sixth switch unit (T14, T24, respectively)
  • the control terminals of T34) and the control terminals of the seventh switching units (T15, T25, and T35) input scan signals S2 and S4, wherein the second scan signal S2 and the fourth scan signal S4 are in the same timing. Since the three sub-pixel units share one scan line, the number of signal lines of the pixel circuit can be reduced to a certain extent, and the cost of the integrated circuit is reduced.
  • the control end of the fifth switching unit T33 of the third sub-pixel circuit P3 is connected to the second scan line Scan2, and since the second scan line Scan2 is simultaneously connected to the control ends of T33 and T34,
  • the third scan signal S3 of the control terminal of the input T33 in the third sub-pixel circuit P3 and the second scan signal S2 of the control terminal of the input T34 are in the same timing. Since the second scan line Scan2 is shared, the number of signal lines of the pixel circuit can be reduced, and the cost of the integrated circuit can be reduced.
  • the control end of the fifth switching unit T23 of the second sub-pixel circuit P2 is connected to the third scan line Scan3.
  • the first level is a high level VDD and the second level is a low level VSS provided through ground.
  • FIG. 3 is a timing diagram of key signals in a pixel circuit as disclosed in FIG. 2 of the present disclosure.
  • 4-8 are current flow directions of the w1, w2, w3, w4, and w5 stages in the pixel circuit provided in FIG. schematic diagram. The operation principle of the pixel circuit provided in FIG. 2 will be described below by taking the first level as VDD and the second level as VSS as an example, in conjunction with the signal timing diagram shown in FIG. 3 and the current flow diagrams of FIGS. 4-8.
  • Each of the switching units is exemplified by a thin film transistor (referred to as a switching transistor or a TFT).
  • the driving unit is a driving thin film transistor (referred to as a driving transistor or a DTFT).
  • the energy storage unit is an example of a capacitor, and the electroluminescent unit is an organic light emitting unit.
  • the diode OLED is described as an example.
  • the signal timing diagram shown in Figure 3 can be divided into five stages, which are respectively represented as reset stage w1, first discharge Stage w2, second discharge stage w3, third discharge stage w4, and illuminating stage w5.
  • the signals are all low level, except T14, T24, T34, T23 are cut off, the other TFTs are turned on, the first pole b1 of capacitor C1 and the first of capacitor C2
  • the pole b2 point, and the first pole b3 point of C3 are all grounded at the same time, the three-point potential is 0V, the second pole a1 and a2 and a3 are connected to the high voltage VDD at three points, and the gate of D16 is turned on because T13 and T33 are turned on.
  • the gates d3 of the poles d1 and D36 are connected to the signal Vdata of the data line, and the potential is V1. Referring to FIG. 4, a schematic diagram of the current flow in the w1 phase is shown.
  • Scan1, Scan2, and Scan3 are both low level, EM1 is high, and TFT conduction is: T12, T22, T32, T13, T23, T33, T15, T25, T35 are turned on, others The TFT is turned off and the capacitors C1, C2, and C3 are discharged.
  • the discharge paths of the capacitors C1, C2, and C3 in the respective sub-pixel units are shown in FIG.
  • Capacitors C1, C2, and C3 are discharged until the potential of a1 is V1+Vth1, the potential of a2 is V1+Vth2, and the potential of a3 is V1+Vth3, where Vth1, Vth2, and Vth3 are the threshold voltages of driving units D16, D26, and D36, respectively. . During this discharge, the current still does not pass through the electroluminescent units (O1, O2 and O3).
  • the gates d2 of the gates d1 and D26 of D16 and the gate d3 of D36 are connected to the data line signal Vdata at a potential of V1.
  • Scan1 is converted to a high level, and the potential difference between C1 is V1+Vth1; Scan2 and Scan3 are kept at a low level, EM1 is at a high level, and TFT conduction is: T23, T33, T15, T25 and T35 are turned on, and the remaining TFTs are turned off.
  • the voltage of the signal Vdata of the data line is V2.
  • C2 and C3 in the second sub-pixel P2 and the third sub-pixel P3 continue to discharge (the path of the discharge current is shown in FIG. 6), the potential of the a2 terminal of the capacitor C2 becomes V2+Vth2, and the a3 end of the capacitor C3 The potential becomes V2+Vth3 and is prepared for the following stages.
  • Scan1 and Scan3 are both high level, Scan2 is low level, and the TFT conduction state is: T33, T15, T25, T35 are turned on, and the remaining TFTs are all turned off.
  • C3 in the third pixel continues to discharge (the path of the discharge current is shown in FIG. 7), at which time the voltage of the signal Vdata of the data line is V3, so the potential of the a3 terminal of the capacitor C3 becomes V3+Vth3, and is the following Prepare for the lighting phase.
  • the electroluminescence unit (O1, O2, and O3) is in the normal light-emitting phase
  • EM1 is at a low level
  • Scan1, Scan2, and Scan3 are both at a high level
  • the TFT conduction states are: T11, T21, T31, T14, T24, and T34 are turned on, and the remaining TFTs are turned off.
  • the a1 end of the three capacitors C1, the a2 end of the C2, and the a3 end of the C3 are connected to the high level VDD of the first voltage terminal VA, and the b1 end of the capacitor C1, the b2 end of the C2, and the b3 end of the C3 are floated.
  • the d1 point potential is VDD-V1-Vth1
  • the d2 point potential is VDD-V2-Vth2
  • the d3 point potential is VDD-V3-Vth3, in Figure 8. The flow path of the current in the circuit at this stage is shown.
  • the current I OLED flowing into O1 is calculated by the following formula:
  • I OLED K(V GS -Vth1) 2
  • Vth1 is a threshold voltage of the driving unit D16
  • Vth2 is a threshold voltage of the driving unit D26
  • Vth3 is a threshold voltage of the driving unit D36.
  • V GS is the voltage between the gate and the source of the driving transistor.
  • C ox is the process constant
  • W is the TFT channel width
  • L is the channel length of the thin film transistor
  • both W and L are selectively designtable constants.
  • the operating current I OLED is already unaffected by the threshold voltage of the driving transistor and is only related to the voltages (V1, V2 and V3) on the data line Data.
  • the problem that the threshold voltage (Vth) drifts due to the process process and long-time operation of the driving transistor affects the working current I OLED is completely solved, the influence of the threshold voltage pair is eliminated, and the normal operation of the OLED is ensured.
  • the power supply circuit VL may include only one switch unit, that is, the first switch unit T11, and the control end of the T11 is connected to the first signal control line EM1, and the first end of the T11 is connected.
  • the first level terminal VA, the second end of the T11 is connected to the three sub-pixel circuits for providing the first power of the first level terminal VA to the three sub-pixel circuits under the signal control of the first signal control line EM1 level.
  • FIG. 9 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the power supply circuit VL includes only one TFT at this time, which further reduces the circuit wiring complexity and reduces the cost of the integrated circuit. By compressing the number of TFT devices in this way, the sub-pixel size can be greatly reduced and the IC cost can be reduced, thereby achieving higher image quality.
  • the pixel circuit provided by the embodiment of the present disclosure can reduce the pixel for the pixel device in the display device by sharing the data line with the adjacent three sub-pixel circuits while providing the working voltage to the three sub-pixel circuits through one first level terminal.
  • the number of signal lines reduces the cost of the integrated circuit and increases the pixel density of the display device.
  • the operating current flowing through the electroluminescent unit is not affected by the threshold voltage of the corresponding driving transistor, completely solving the threshold voltage drift of the driving transistor. Causes uneven display brightness.
  • FIG. 10 is a schematic structural diagram of a pixel circuit according to still another embodiment of the present disclosure.
  • the pixel circuit includes three sub-pixel circuits (P1, P2, and P3), and a power supply circuit VL, the three sub-pixel circuits share a data line Data;
  • the power supply circuit includes a first switching unit T11, a second switching unit T21 and a third switching unit T31;
  • the control terminal of T11 is connected to the first signal control line EM1, the first end of T11 is connected to the first level terminal VA, and the second end of T11 is connected to the first sub-pixel circuit P1 of the three sub-pixel circuits; T11 is used in the The signal control of a signal control line EM1 provides a first level of the first level terminal to the first sub-pixel circuit P1.
  • the control terminal of T21 is connected to the first signal control line EM1, the first end of T21 is connected to the first level terminal VA, and the second end of T21 is connected to the second sub-pixel circuit P2 of the three sub-pixel circuits; T21 is used in the The signal control of a signal control line EM1 provides a first level of the first level terminal VA to the second sub-pixel circuit P2.
  • the control terminal of T31 is connected to the first signal control line EM1, the first end of T31 is connected to the first level terminal VA, and the second end of T31 is connected to the third sub-pixel circuit P3 of the three sub-pixel circuits, T31 is used for
  • the signal control of a signal control line EM1 provides a first level of the first level terminal VA to the third sub-pixel circuit P3.
  • each of the sub-pixel circuits (P1, P2, P3) is further connected to the second signal control line EM2 and the first level terminal VA, wherein each of the sub-pixel circuits (P1, P2, P3) comprises: Four switch units, a drive unit, an energy storage unit, and an electroluminescence unit; wherein, in order to distinguish the four switch units included in P1, the eighth switch unit T12, the ninth switch unit T13, and the tenth switch unit T14, The eleven switch unit T15, the drive unit is D16, the energy storage unit is C1, and the electroluminescent unit is O1; the four switch units included in P2 are the eighth switch unit T22, the ninth switch unit T23, and the tenth switch.
  • the unit T24, the eleventh switch unit T25, the drive unit is D26, the energy storage unit is C2, and the electroluminescent unit is O2;
  • the four switch units included in P3 are the eighth switch unit T32 and the ninth switch unit T33.
  • the tenth switch unit T34, the eleventh switch unit T35, the drive unit is D36, the energy storage unit is C3, and the electroluminescent unit is O3;
  • the first pole a1 of the energy storage unit C1 is connected to the first level terminal VA for writing the first level of the first level terminal VA to the first pole a1 of the energy storage unit C1;
  • the control terminal of T12 is connected to the second signal control line EM2, the first end of T12 is connected to the second pole b1 of the energy storage unit C1, the second end of T12 is connected to the second level terminal VB; and T12 is used for the second The second level of the second level terminal VB is written to the second pole b1 of the energy storage unit C1 under the control of the signal of the signal control line EM2;
  • the control terminal of T13 inputs a second scan signal S2, the first end of T13 is connected to the data line Data, the second end of the T13 is connected to the output end of the driving unit D16, and T13 is used for the second scan signal. Writing the signal of the data line Data to the output end of the driving unit D16 under the control of S2;
  • the control terminal of T14 inputs a first scan signal S1, and the first end of T14 is connected to the second pole b1 of the energy storage unit C1, and the second end of T14 is connected to the input end of the driving unit D16 and the power supply circuit VL; Writing the signal of the data line Data and the threshold voltage of D16 to the second pole b1 of the energy storage unit C1;
  • the control end of D16 is connected to the first end of the T14 for outputting a driving current at the output end;
  • T15 is connected to the first signal control line EM1, and the first end of T15 is connected to the output end of the D16; T15 is for controlling the driving current input under the signal control of the first signal control line EM1 Describe the first pole of the electroluminescent unit O1;
  • a first pole of the electroluminescent unit O1 is connected to the second end of the T15, and a second pole of the electroluminescent unit O1 is connected to the second level terminal VB for controlling under the driving current Show grayscale.
  • the control end of the ninth switch unit (T13, T23 or T33) and the control end of the tenth switch unit (T14, T24 or T34) share a scan line, so that The first scan signal S1 and the second scan signal S2 are in the same timing.
  • the control end of T13 and the control end of T14 in P1 are connected to the first scan line Scan1
  • the control end of T23 in P2 and the control end of T24 are connected to the second scan line Scan2
  • the control end of T33 in P3 and T34 The control terminal is connected to the third scan line Scan3. Sharing the scan lines can reduce the number of signal lines in the pixel circuit and reduce the cost of the integrated circuit.
  • the first level is a high level VDD and the second level is a low level VSS provided through ground.
  • FIG. 11 is a timing diagram of key signals in the pixel circuit provided in FIG. 10, and FIG. 12-16 is a schematic diagram of current flow in stages of w1, w2, w3, w4, and w5 in the pixel circuit provided in FIG.
  • the pixel provided in FIG. 10 is combined with the signal timing diagram shown in FIG. 11 and the current flow direction diagrams of FIGS. 12-16.
  • the working principle of the circuit is explained.
  • Each of the switching units is exemplified by a thin film transistor (referred to as a switching transistor or a TFT).
  • the driving unit is a driving thin film transistor (referred to as a driving transistor or a DTFT).
  • the energy storage unit is an example of a capacitor, and the electroluminescent unit is an organic light emitting unit.
  • the diode OLED is described as an example.
  • FIG. 11 also shows timing signals of the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3, and each of the switch units is a P-type switching transistor as an example, and the signal timing diagram shown in FIG. It can be divided into five stages, which are respectively denoted as reset stage w1, first discharge stage w2, second discharge stage w3, third discharge stage w4, and illumination stage w5.
  • Scan1 is at a low level
  • Scan2, Scan3, EM1, and EM2 are both at a high potential
  • the level of the data line is V1.
  • the conduction state of the TFT is: T13, T14 are turned on, and the remaining TFTs are turned off.
  • the capacitor C1 is discharged, and the discharge path of C1 in the sub-pixel unit P1 is shown in FIG.
  • the potential to point b1 is V1-Vth1, and the potential of point a1 is VDD, where Vth1 is the threshold voltage of the driving unit D16.
  • Scan2 In the second discharge phase w3, Scan2 is at a low level, and Scan1, Scan3, EM1, and EM2 are both at a high potential, and the level of the data line is V2, and the conduction state of the TFT is: T23, T24 are turned on, and the remaining TFTs are all turned off.
  • the capacitor C2 is discharged, and the discharge path of C2 in the sub-pixel unit P2 is shown in FIG. 14 until the b2 point potential is V2-Vth2, and the a2 point potential is VDD, where Vth2 is the threshold voltage of the driving unit D26.
  • Scan3 is at a low level, and Scan1, Scan2, EM1, and EM2 are both at a high potential, and the level of the data line is V3.
  • the conduction state of the TFT is: T33 and T34 are turned on, and the remaining TFTs are turned off.
  • the capacitor C3 is discharged, and the path discharge path of C3 in the sub-pixel unit P3 is shown in FIG. 15 until the b3 point potential is V3-Vth3, and the a3 point potential is VDD, where Vth3 is the threshold voltage of the driving unit D36.
  • the electroluminescent units O1, O2, and O3
  • EM1 is at a low level
  • Scan1, Scan2, Scan3, and EM2 are both at a high level
  • the TFT conduction states are: T11, T21, T31, T15, T25, and T35 are turned on, and the remaining TFTs are turned off.
  • the a1 end of the capacitor C1, the a2 end of the C2, and the a3 end of the C3 are connected to the high level VDD of the first voltage terminal VA, and the capacitors C1, C2, and C3 maintain the original voltage difference, and the gate b1 potential of the D16 is V1-Vth1, D26 has a gate b2 point potential of V2-Vth2, and D36 has a gate b3 point potential of V3-Vth3.
  • the flow of current in the circuit at this stage is shown in FIG.
  • the current I OLED flowing into O1 is calculated by the following formula:
  • I OLED K(V GS -Vth1) 2
  • Vth1 is the threshold voltage of the driving unit D16
  • Vth2 is the threshold voltage of the driving unit D26
  • Vth3 is the threshold voltage of the driving unit D36.
  • V GS is the gate and source of the driving transistor.
  • Voltage between, ⁇ , C ox is the process constant
  • W is the TFT channel width
  • L is the channel length of the thin film transistor
  • both W and L are selectively designtable constants.
  • the operating current I OLED has not been affected by the threshold voltage of the driving transistor, and is only related to the data line Data voltages (V1, V2 and V3).
  • the problem that the threshold voltage (Vth) drift of the driving transistor due to the process process and long-time operation affects the working current I OLED is completely solved, and the influence of the threshold voltage on the I OLED is eliminated, and the normal operation of the OLED is ensured.
  • the power supply circuit VL may include only one switch unit, that is, the first switch unit T11, and the control end of the T11 is connected to the first signal control line EM1, and the first end of the T11 is connected to the first level terminal VA.
  • the second end of T11 is coupled to the three sub-pixel circuits for providing a first level of the first level terminal VA to the three sub-pixel circuits under the signal control of the first signal control line EM1.
  • FIG. 17 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure. As shown in FIG. 17, the power supply circuit VL includes only one TFT at this time, which further reduces the circuit wiring complexity and reduces the cost of the integrated circuit. By compressing the number of TFT devices in this way, the sub-pixel size can be greatly reduced and the IC cost can be reduced, thereby achieving higher image quality.
  • the pixel circuit provided by the embodiment of the present disclosure can reduce the pixel for the pixel device in the display device by sharing the data line with the adjacent three sub-pixel circuits while providing the working voltage to the three sub-pixel circuits through one first level terminal.
  • the number of signal lines reduces the cost of the integrated circuit and increases the pixel density of the display device.
  • the operating current flowing through the electroluminescent unit is not affected by the threshold voltage of the corresponding driving transistor, completely solving the threshold voltage drift of the driving transistor. Causes uneven display brightness.
  • FIG. 18 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes three sub-pixel circuits (P1, P2, and P3), and a power supply circuit VL, the three sub-pixel circuits share a data line Data;
  • the power supply circuit VL includes a first switching unit T11, a second switching unit T21 and a third switching unit T31;
  • the control terminal of T11 is connected to the first signal control line EM1, the first end of T11 is connected to the first level terminal VA, and the second end of T11 is connected to the first sub-pixel circuit P1 of the three sub-pixel circuits, and the power supply circuit VL A first level for providing the first level terminal VA to the first sub-pixel circuit P1 under the signal control of the first signal control line EM1.
  • the control terminal of the T21 is connected to the first signal control line EM1, the first end of the T21 is connected to the first level terminal VA, and the second end of the T21 is connected to the second sub-pixel circuit P2 of the three sub-pixel circuits.
  • the power supply circuit VL is for supplying the first level of the first level terminal VA to the second sub-pixel circuit P2 under the signal control of the first signal control line EM1.
  • the control terminal of T31 is connected to the first signal control line EM1, the first end of T31 is connected to the first level terminal VA, and the second end of T31 is connected to the third sub-pixel circuit P3 of the three sub-pixel circuits, the power supply circuit VL A first level for providing the first level terminal VA to the third sub-pixel circuit P3 under the signal control of the first signal control line EM1.
  • each of the sub-pixel circuits (P1, P2, P3) is further connected to the second signal control line EM2 and the third signal control line EM3, wherein each of the sub-pixel circuits (P1, P2, P3) comprises: four a switching unit, a driving unit, an energy storage unit and an electroluminescent unit; wherein, for distinguishing, the four switching units included in P1 are, in order, a twelfth switching unit T12, a thirteenth switching unit T13, and a fourteenth switching unit T14, the fifteenth switch unit T15, the drive unit is D16, the energy storage unit is C1, the electroluminescent unit is O1; the four switch units included in P2 are the twelfth switch unit T22 and the thirteenth switch unit T23, the fourteenth switch unit T24, the fifteenth switch unit T25, the drive unit is D26, the energy storage unit is C2, the electroluminescent unit is O2, and the four switch units included in P3 are the twelfth switch unit. T32, the thirteenth switch
  • the control terminal of T12 inputs a first scan signal S1, the first end of T12 is connected to the data line Data, the second end of T12 is connected to the first pole a1 of the C1, and T12 is used for the first scan signal.
  • the signal of the data line is written into the first pole a1 of the C1 under the control;
  • the control terminal of T13 is connected to the second signal control line EM2, the first end of the T13 is connected to the second end of the T12, the second end of the T13 is connected to the second level terminal VB;
  • the second level of the second level terminal VB is written to the first pole a1 of the C1 under the control of the signal of the second signal control line EM2;
  • the control terminal of T14 is connected to the second signal control line EM2, the first end of the T14 is connected to the second pole b1 of the C1, the second end is connected to the output end of the driving unit D16, and the T14 is used for the second signal control line EM2. Controlling the first level and the threshold voltage of D16 to the second pole b1 of the C1 under the control of the signal;
  • the input end of the D16 is connected to the power supply circuit VL, the control end of the D16 is connected to the second pole b1 of the C1, the output end of the D16 is connected to the second end of the T14; and D16 is used at the output end.
  • Output drive current
  • the control terminal of T15 is connected to the third signal control line EM3, the first end of the T15 is connected to the output end of the D16; the T15 is used to control the driving current input under the signal control of the third signal control line EM3 Describe the first pole of the electroluminescent unit O1;
  • a first pole of the electroluminescent unit O1 is connected to the second end of the T15, and a second pole is connected to the second level end VB; the electroluminescent unit O1 is configured to be displayed under the control of the driving current Grayscale.
  • the first level is a high level VDD and the second level is a low level VSS provided through ground.
  • FIG. 19 is a timing diagram of key signals in the pixel circuit provided in FIG. 18 according to the present disclosure.
  • FIGS. 20-24 are schematic diagrams showing current flows in stages of w1, w2, w3, w4, and w5 in the pixel circuit provided in FIG. Taking the first level as the high level VDD and the second level as the ground low level VSS as an example, the pixel provided in FIG. 18 is combined with the signal timing diagram shown in FIG. 19 and the current flow diagrams of FIGS. 20-24. The working principle of the circuit is explained.
  • Each of the switching units is exemplified by a thin film transistor (referred to as a switching transistor or a TFT).
  • the driving unit is a driving thin film transistor (referred to as a driving transistor or a DTFT).
  • the energy storage unit is an example of a capacitor, and the electroluminescent unit is an organic light emitting unit.
  • the diode OLED is described as an example.
  • 19 shows timing signals of EM1, EM2, EM3, first scan line Scan1, second scan line Scan2, and third scan line Scan3, wherein the first scan line Scan provides a first scan signal to T12 of P1;
  • the scan line Scan2 is used to provide a first scan signal to T22 of P2;
  • the third scan line Scan3 is used to provide a first scan signal to T32 of P3; for each switch unit, a P-type switch transistor is taken as an example for description.
  • the illustrated signal timing diagram can be divided into five stages, denoted as charging phase w1, first pixel compensation phase w2, second pixel compensation phase w3, third pixel compensation phase w4, and illumination phase w5.
  • the conduction states of the TFTs are: T12, T22, T32, T15, T25, and T35 are turned off, and the remaining TFTs are all guided.
  • the capacitors C1, C2, and C3 flow along the current shown in FIG. 20 until the b1 point potential is VDD-Vth1, the b2 point potential is VDD-Vth2, and the b3 point potential is VDD-Vth3, where Vth1, Vth2, and Vth3 are respectively The threshold voltages for D16, D26, and D36.
  • current does not pass through O1, O2, and O3.
  • the a1, a2, and a3 points are grounded and the potential is 0V.
  • the data line level is V1
  • the TFT conduction state is: T12 is on, and the remaining TFTs are off.
  • the a1 point potential is changed from the original 0V to V1
  • the b1 point is in the floating state. Therefore, the original voltage difference between the two points a1 and b1 (VDD-Vth1) is maintained, and the potential of the gate b1 of D16 occurs.
  • the voltage jumps, the b1 point potential jumps to VDD - Vth1 + V1, and the flow path of the first pixel compensation phase current is shown in FIG.
  • Scan2 is at a low level, and Scan1, Scan3, EM1, EM2, and EM3 are all at a high potential, and the level of the data line is V2, and the TFT conduction state is: T22 is turned on, and the remaining TFTs are all turned off.
  • the a2 point potential is changed from the original 0V to V2, and the b2 point is in the floating state. Therefore, the original voltage difference between the two points a2 and b2 (VDD-Vth2) is maintained, and the potential of the gate b2 of D26 occurs.
  • the voltage jumps, the b2 point potential jumps to VDD - Vth2 + V2, and the flow path of the second pixel compensation phase current is shown in FIG.
  • the third pixel compensation stage w4 Scan3 is low level, Scan1, Scan2, EM1, EM2, and EM3 are all high, the data line level is V3, and the TFT conduction state is: T32 is on, and the remaining TFTs are off.
  • the a3 point potential is changed from the original 0V to V3, and the b3 point is in the floating state. Therefore, the original differential pressure (VDD-Vth3) of the two points a3 and b3 is maintained, and the potential of the gate b3 of the D36 occurs.
  • the voltage jumps, the b3 point potential jumps to VDD - Vth3 + V3, and the third pixel compensation stage circuit flow path is shown in FIG.
  • the electroluminescent units O1, O2, and O3
  • EM1 and EM3 are at a low level
  • Scan1, Scan2, Scan3, and EM2 are both at a high level
  • the TFT conduction state is: T11, T21, T31, T15, T25, and T35 are turned on, and the remaining TFTs are turned off.
  • the three sub-pixel circuits are connected to the high level VDD of the first voltage terminal VA, and the capacitors C1, C2 and C3 maintain the original voltage difference, the b1 point potential is VDD-Vth1+V1, and the b2 point potential is VDD-Vth2+V2.
  • the b3 point potential is VDD-Vth3+V3, and the flow of current in the circuit at this stage is shown in FIG.
  • the current I OLED flowing into O1 is calculated by the following formula:
  • I OLED K(V GS -Vth1) 2
  • Vth1 is the threshold voltage of the driving unit D16
  • Vth2 is the threshold voltage of the driving unit D26
  • Vth3 is the threshold voltage of the driving unit D36.
  • V GS is the voltage between the gate and the source of the driving transistor.
  • C ox is the process constant
  • W is the TFT channel width
  • L is the channel length of the thin film transistor
  • both W and L are selectively designtable constants.
  • the operating current I OLED has not been affected by the threshold voltage of the driving transistor, and is only related to the data line Data voltages (V1, V2 and V3).
  • the problem that the threshold voltage (Vth) drift of the driving transistor due to the process process and long-time operation affects the working current I OLED is completely solved, and the influence of the threshold voltage on the I OLED is eliminated, and the normal operation of the OLED is ensured.
  • the power supply circuit VL may include only one switch unit, that is, the first switch unit T11, and the control end of the T11 is connected to the first signal control line EM1, and the first end of the T11 is connected to the first level terminal VA.
  • the second end of T11 is coupled to the three sub-pixel circuits for providing a first level of the first level terminal VA to the three sub-pixel circuits under the signal control of the first signal control line EM1.
  • FIG. 25 is a schematic structural diagram of a pixel circuit according to still another embodiment of the present disclosure. As shown in FIG. 25, the power supply circuit VL includes only one TFT at this time, which further reduces the circuit wiring complexity and reduces the cost of the integrated circuit. By compressing the number of TFT devices in this way, the sub-pixel size can be greatly reduced and the IC cost can be reduced, thereby achieving higher image quality.
  • the pixel circuit provided by the embodiment of the present disclosure can reduce the pixel for the pixel device in the display device by sharing the data line with the adjacent three sub-pixel circuits while providing the working voltage to the three sub-pixel circuits through one first level terminal.
  • the number of signal lines reduces the cost of the integrated circuit and increases the pixel density of the display device.
  • the operating current flowing through the electroluminescent unit is not affected by the threshold voltage of the corresponding driving transistor, completely solving the threshold voltage drift of the driving transistor. Causes uneven display brightness.
  • Embodiments of the present disclosure provide a display device including any of the above pixel circuits.
  • 26-28 are schematic diagrams showing the positional relationship between a pixel circuit and a pixel in a display device according to an embodiment of the present disclosure.
  • the three sub-pixel circuits are located on the same side of the data line.
  • the sub-pixel circuit P1, the sub-pixel circuit P2, and the sub-pixel circuit P3 are located on the same side of the data line Data, that is, between the two data lines Data, wherein P1, P2, and P3 constitute one pixel. Circuit.
  • three sub-pixel circuits of the pixel circuit are located in two adjacent pixels, wherein adjacent first sub-pixel circuits and second sub-pixel circuits of the three sub-pixel circuits are located Within one pixel, the third sub-pixel circuit is located in the second pixel; as shown in FIG. 27, the sub-pixel circuit P1 and the sub-pixel circuit P2 are located in the first pixel; the sub-pixel circuit P3 is located in the second pixel;
  • the first sub-pixel circuit of the three sub-pixels is located in the first pixel, and the adjacent second sub-pixel circuit and the third sub-pixel circuit are located in the second pixel.
  • the sub-pixel circuit P1 is located in the first pixel; the sub-pixel circuit P2 and the sub-pixel circuit P3 are located in the second pixel; wherein, as shown in FIGS. 27 and 28,
  • the data line Data is located between the first pixel and the second pixel. This enables the distribution of the components on the corresponding substrate to be more uniform, and the gate line Gata crossing the data line Data is also shown in FIGS. 26, 27, and 28 above.
  • the display device can be any product or component having display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.

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Abstract

一种像素电路和显示装置。像素电路包括三个子像素电路（P1，P2，P3）和一个供电电路（VL），三个子像素电路（P1，P2，P3）共用数据线（Data）；供电电路（VL）连接第一电平端（VA）、第一信号控制线（EM1）和子像素电路（P1，P2，P3），用于在第一信号控制线（EM1）的信号控制下通过第一电平端（VA）向子像素电路（P1，P2，P3）提供第一电平；子像素电路（P1，P2，P3）连接供电电路（VL）和数据线（Data），用于在供电电路（VL）提供的第一电平和数据线（Data）的数据信号控制下显示灰阶。像素电路能够缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度。

Description

像素电路和显示装置 技术领域
本公开涉及一种像素电路和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示器是当今平板显示器研究领域的热点之一，与液晶显示器相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、掌上电脑(Personal Digital Assistant，简称PDA)、数码相机等显示领域OLED显示器已经开始取代传统的液晶显示屏(Liquid Crystal Display，简称LCD)。像素驱动电路设计是OLED显示器核心技术内容，具有重要的研究意义。
与薄膜晶体管(Thin Film Transistor，简称TFT)-液晶显示器(TFT-LCD)利用稳定的电压控制亮度不同，OLED显示器属于电流驱动，需要稳定的电流来控制发光。
通常，一个像素电路一般对应于一个子像素，每个像素电路都至少包含一条数据线、一条提供工作电压的电压线和多条扫描信号线，这样就导致相应的制作工艺较为复杂，并且不利于缩小像素间距。
发明内容
本公开的至少一个实施例缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度。
根据本公开的一方面，提供一种像素电路，包括三个子像素电路和一个供电电路，所述三个子像素电路共用数据线；
所述供电电路连接第一电平端、第一信号控制线和所述子像素电路，所述供电电路用于在所述第一信号控制线的信号控制下通过所述第一电平端向所述子像素电路提供第一电平；
所述子像素电路连接所述供电电路和所述数据线，用于在所述供电电路 提供的第一电平和所述数据线的数据信号控制下显示灰阶。
可选地，所述供电电路包括，第一开关单元，所述第一开关单元的控制端连接所述第一信号控制线，所述第一开关单元的第一端连接所述第一电平端，所述第一开关单元的第二端连接所述三个子像素电路，用于在所述第一信号控制线的信号控制下向三个子像素电路提供第一电平端的第一电平。
可选地，所述供电电路包括，第一开关单元，第二开关单元和第三开关单元；
所述第一开关单元的控制端连接所述第一信号控制线，所述第一开关单元的第一端连接所述第一电平端，所述第一开关单元的第二端连接三个子像素电路中的第一子像素电路，用于在所述第一信号控制线的信号控制下向第一子像素电路提供第一电平端的第一电平。
所述第二开关单元的控制端连接所述第一信号控制线，所述第二开关单元的第一端连接所述第一电平端，所述第二开关单元的第二端连接三个子像素电路中的第二子像素电路，用于在所述第一信号控制线的信号控制下向第二子像素电路提供第一电平端的第一电平。
所述第三开关单元的控制端连接所述第一信号控制线，所述第三开关单元的第一端连接所述第一电平端，所述第三开关单元的第二端连接三个子像素电路中的第三子像素电路，用于在所述第一信号控制线的信号控制下向第三子像素电路提供第一电平端的第一电平。
可选地，每个所述子像素电路包括：分别为第四至第七开关单元的四个开关单元、驱动单元、储能单元和电致发光单元；
其中，第四开关单元的控制端输入第一扫描信号，第四开关单元的第一端连接第二电平端；第四开关单元的第二端连接储能单元的第一极；第四开关单元用于在所述第一扫描信号的控制下将所述第二电平端的信号写入所述储能单元的第一极；
第五开关单元的控制端输入第三扫描信号，第五开关单元的第一端连接所述数据线；第五开关单元用于在所述第三扫描信号的控制下将数据线的信号在所述第五开关单元的第二端输出；
第六开关单元的控制端输入第二扫描信号，第六开关单元的第一端连接所述储能单元的第一极，所述第六开关单元的第二端连接所述第五开关单元 的第二端，第六开关单元用于在所述第二扫描信号的控制下将所述数据线的信号写入所述储能单元的第一极以耦合抬升所述储能单元第二极的电平；
驱动单元的控制端连接所述第六开关单元的第二端，驱动单元的输入端连接储能单元的第二极，驱动单元用于输出驱动电流；
第七开关单元的控制端输入第四扫描信号，所述第七开关单元的第一端连接所述驱动单元的输出端，所述第七开关单元的第二端连接所述第二电平端，第七开关单元用于在所述第四扫描信号的控制下控制所述驱动电流输入所述电致发光单元的第一极；
所述电致发光单元的第一极连接所述驱动单元的输出端，所述电致发光单元的第二极连接所述第二电平端，电致发光单元用于在所述驱动电流的控制下显示灰阶；
所述储能单元的第二极连接所述供电电路，储能单元用于储存所述数据线的信号和驱动单元的阈值电压。
可选地，所述三个子像素电路中，第一子像素电路、第二子像素电路和第二子像素电路共用一条第一扫描线向所述第四开关单元的控制端输入第一扫描信号。
可选地，所述第一子像素电路的第五开关单元的控制端连接所述第一扫描线，所述第一子像素电路的第一扫描信号和第三扫描信号时序相同。
可选地，所述三个子像素电路中，第一子像素电路、第二子像素电路和第二子像素电路共用一条第二扫描线分别向所述第六开关单元的控制端和所述第七开关单元的控制端输入第二扫描信号和第四扫描信号，其中所述第二扫描信号和第四扫描信号时序相同。
可选地，所述三个子像素电路中，所述第三子像素电路的第五开关单元的控制端连接所述第二扫描线，所述第三子像素电路中输入第五开关单元控制端的第三扫描信号和输入第六开关单元控制端的第二扫描信号时序相同。
可选地，所述子像素电路还连接第二信号控制线和所述第一电平端，其中，每个所述子像素电路包括：分别为第八至第十一开关单元的四个开关单元、驱动单元、储能单元和电致发光单元；
其中，储能单元的第一极连接所述第一电平端，用于将第一电平端的第一电平写入储能单元的第一极；
第八开关单元的控制端连接所述第二信号控制线，第八开关单元的第一端连接所述储能单元的第二极，第八开关单元的第二端连接第二电平端，第八开关单元用于在第二信号控制线的信号控制下将第二电平端的第二电平写入所述储能单元的第二极；
第九开关单元的控制端输入第二扫描信号，第九开关单元的第一端连接所述数据线，所述第九开关单元的第二端连接所述驱动单元的输出端，第九开关单元用于在所述第二扫描信号的控制下将所述数据线的信号写入所述驱动单元的输出端；
第十开关单元的控制端输入第一扫描信号，第十开关单元的第一端连接储能单元的第二极，第十开关单元的第二极连接所述驱动单元的输入端和所述供电电路，第十开关单元用于将数据线的信号和所述驱动单元的阈值电压写入所述储能单元的第二极；
驱动单元的控制端连接所述第十开关单元的第一端，用于在输出端输出驱动电流；
第十一开关单元的控制端连接所述第一信号控制线，所述第十一开关单元的第一端连接所述驱动单元的输出端，第十一开关单元用于在所述第一信号控制线的信号控制下控制所述驱动电流输入所述电致发光单元的第一极；
所述电致发光单元的第一极连接所述第十一开关单元的第二端，所述电致发光单元的第二极连接所述第二电平端，所述电致发光单元用于在所述驱动电流的控制下显示灰阶。
可选地，同一个所述子像素电路中，第九开关单元的控制端和所述第十开关单元的控制端共用一条扫描线，使得所述第一扫描信号和第二扫描信号时序相同。
可选地，所述子像素电路还连接第二信号控制线和第三信号控制线，其中，每个所述子像素电路包括：分别为第十二至第十五开关单元的四个开关单元、驱动单元、储能单元和电致发光单元；
其中，第十二开关单元的控制端输入第一扫描信号，第十二开关单元的第一端连接所述数据线，第十二开关单元的第二端连接所述储能单元的第一极，第十二开关单元用于在所述第一扫描信号的控制下将所述数据线的信号写入所述储能单元的第一极；
第十三开关单元的控制端连接所述第二信号控制线，所述第十三开关单元的第一端连接所述第十二开关单元的第二端，所述第十三开关单元的第二端连接第二电平端，第十三开关单元用于在所述第二信号控制线的信号控制下将所述第二电平端的第二电平写入所述储能单元的第一极；
第十四开关单元的控制端连接第二信号控制线，所述第十四开关单元的第一端连接所述储能单元的第二极，第一端连接所述驱动单元的输出端第十四开关单元，用于在第二信号控制线的控制下将第一电平和驱动单元的阈值电压写入所述储能单元的第二极；
所述驱动单元的输入端连接所述供电电路，所述驱动单元的控制端连接所述储能单元的第二极，所述驱动单元的输出端连接所述第十四开关单元的第二端，所述驱动单元用于在输出端输出驱动电流；
第十五开关单元的控制端连接第三信号控制线，所述第十五开关单元的第一端连接所述驱动单元的输出端，第十五开关单元用于在所述第三信号控制线的控制下控制所述驱动电流输入所述电致发光单元的第一极；
所述电致发光单元的第一极连接所述第十五开关单元的第二端，第二极连接所述第二电平端，所述电致发光单元用于在所述驱动电流的控制下显示灰阶。
可选地，开关单元和驱动单元为薄膜晶体管，各个开关单元的控制端为薄膜晶体管的栅极，各个开关单元的第一端为薄膜晶体管的源极，各个开关单元的第二端为薄膜晶体管的漏极，所述驱动单元的输入端为薄膜晶体管的源极，所述驱动单元的控制端为薄膜晶体管的栅极，所述驱动单元的输出端为薄膜晶体管的漏极。
可选地，所述储能单元为电容。
可选地，所述电致发光单元为有机发光二极管。
根据本公开的一方面，提供一种包括上述任一像素电路的显示装置。
可选地，所述像素电路的三个子像素电路位于同一像素内。
可选地，所述三个子像素电路位于数据线的同一侧。
可选地，所述像素电路的三个子像素电路位于相邻的两个像素内，其中所述三个子像素电路中相邻的第一子像素电路和第二子像素电路位于第一像素内，第三子像素电路位于第二像素内；
或者，其中所述三个子像素电路中第一子像素电路位于第一像素内，相邻的第二子像素电路和第三子像素电路位于第二像素内，其中第一像素和第二像素相邻。
可选地，数据线位于所述第一像素和第二像素之间。
本公开的至少一个实施例提供的像素电路和显示装置，通过将相邻的三个子像素电路共用一条数据线，同时通过一个第一电平端向三个子像素电路提供工作电压，因此能够缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度。
附图说明
下面将对实施例中使用的附图作简单地介绍。
图1为本公开实施例提供的一种像素电路的框图；
图2为本公开另一实施例提供的一种像素电路的结构示意图；
图3为本公开如图2提供的像素电路中关键信号的时序图；
图4为本公开如图2提供的像素电路中w1阶段的电流流向示意图；
图5为本公开如图2提供的像素电路中w2阶段的电流流向示意图；
图6为本公开如图2提供的像素电路中w3阶段的电流流向示意图；
图7为本公开如图2提供的像素电路中w4阶段的电流流向示意图；
图8为本公开如图2提供的像素电路中w5阶段的电流流向示意图；
图9为本公开又一实施例提供的一种像素电路的结构示意图；
图10为本公开再一实施例提供的一种像素电路的结构示意图；
图11为本公开如图10提供的像素电路中关键信号的时序图；
图12为本公开如图10提供的像素电路中w1阶段的电流流向示意图；
图13为本公开如图10提供的像素电路中w2阶段的电流流向示意图；
图14为本公开如图10提供的像素电路中w3阶段的电流流向示意图；
图15为本公开如图10提供的像素电路中w4阶段的电流流向示意图；
图16为本公开如图10提供的像素电路中w5阶段的电流流向示意图；
图17为本公开另一实施例提供的一种像素电路的结构示意图；
图18为本公开又一实施例提供的一种像素电路的结构示意图；
图19为本公开如图18提供的像素电路中关键信号的时序图；
图20为本公开如图18提供的像素电路中w1阶段的电流流向示意图；
图21为本公开如图18提供的像素电路中w2阶段的电流流向示意图；
图22为本公开如图18提供的像素电路中w3阶段的电流流向示意图；
图23为本公开如图18提供的像素电路中w4阶段的电流流向示意图；
图24为本公开如图18提供的像素电路中w5阶段的电流流向示意图；
图25为本公开再一实施例提供的一种像素电路的结构示意图；
图26为本公开实施例提供的显示装置中像素电路与像素的一种位置关系的示意图；
图27为本公开实施例提供的显示装置中像素电路与像素的一种位置关系的示意图；
图28为本公开实施例提供的显示装置中像素电路与像素的一种位置关系的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的开关晶体管和驱动晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本公开实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止；驱动晶体管包括P型和N型，其中P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态；其中N型驱动晶体管的栅极电压为高电平(栅极电压大于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大 状态或饱和状态。
图1为本公开实施例提供的一种像素电路的框图。如图1所示，该像素电路包括：三个子像素电路(P1、P2和P3)，和一个供电电路VL，所述三个子像素电路共用数据线Data；
所述供电电路VL连接第一电平端VA、第一信号控制线EM1和所述子像素电路(P1、P2和P3)，所述供电电路VL用于在所述第一信号控制线EM1的信号控制下通过所述第一电平端VA向所述子像素电路(P1、P2和P3)提供第一电平；
所述子像素电路(P1、P2和P3)连接所述供电电路VL和所述数据线Data，用于在所述供电电路VL提供的第一电平和所述数据线Data的数据信号控制下显示灰阶。
本公开的实施例提供的像素电路，通过将相邻的三个子像素电路共用一条数据线，同时通过一个第一电平端向三个子像素电路提供工作电压，因此能够缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度。
第一实施例：
图2为本公开另一实施例提供的一种像素电路的结构示意图。参照图2所示，该像素电路包括三个子像素电路(P1、P2和P3)，和一个供电电路VL，所述三个子像素电路共用数据线Data；
其中所述供电电路包括，第一开关单元T11，第二开关单元T21和第三开关单元T31；
T11的控制端连接第一信号控制线EM1，T11的第一端连接第一电平端VA，T11的第二端连接三个子像素电路中的第一子像素电路P1，用于在所述第一信号控制线EM1的信号控制下向第一子像素电路P1提供第一电平端VA的第一电平。
T21的控制端连接所述第一信号控制线EM1，T21的第一端连接所述第一电平端VA，T21的第二端连接三个子像素电路中的第二子像素电路P2，用于在所述第一信号控制线EM1的信号控制下向第二子像素电路P2提供第一电平端VA的第一电平。
T31的控制端连接所述第一信号控制线EM1，所述T31的第一端连接所 述第一电平端VA，T31的第二端连接三个子像素电路中的第三子像素电路P3，用于在所述第一信号控制线EM1的信号控制下向第三子像素电路P3提供第一电平端VA的第一电平。
进一步的，每个所述子像素电路(P1、P2、P3)包括：四个开关单元、驱动单元、储能单元和电致发光单元；其中为了区分,在P1中包括的四个开关单元依次为第四开关单元T12、第五开关单元T13、第六开关单元T14、第七开关单元T15，驱动单元为D16、储能单元为C1、电致发光单元为O1；在P2中包括的四个开关单元依次为第四开关单元T22、第五开关单元T23、第六开关单元T24、第七开关单元T25、驱动单元为D26、储能单元为C2、电致发光单元为O2；在P3中包括的四个开关单元依次为第四开关单元T32、第五开关单元T33、第六开关单元T34、第七开关单元T35，驱动单元为D36、储能单元为C3、电致发光单元为O3；
以下仅以P1中的各器件的连接关系为例进行描述，P2、P3的器件连接关系参考P1不再赘述。
其中，T12的控制端输入第一扫描信号S1，T12的第一端连接第二电平端VB；T12的第二端连接储能单元C1的第一极；T12用于在所述第一扫描信号S1的控制下将所述第二电平端VB的信号写入所述储能单元C1的第一极；
T13的控制端输入第三扫描信号S3，T13的第一端连接所述数据线Data；T13用于在所述第三扫描信号S3的控制下将数据线Data的信号在所述T13的第二端输出；
T14的控制端输入第二扫描信号S2，T14的第一端连接所述储能单元C1的第一极，T14的第二端连接所述T13的第二端；T14用于在所述第二扫描信号S2的控制下将所述数据线Data的信号写入所述储能单元C1的第一极以耦合抬升所述储能单元C1第二极的电平；
驱动单元D16的控制端连接T14的第二端，驱动单元D16的输入端连接储能单元C1的第二极；D16用于输出驱动电流；
T15的控制端输入第四扫描信号S4，T15的第一端连接所述驱动单元D16的输出端，第二端连接所述第二电平端VB；T15用于在所述第四扫描信号S4的控制下控制所述驱动电流输入所述电致发光单元O1的第一极；
所述电致发光单元O1的第一极连接所述驱动单元D16的输出端，所述电致发光单元O1的第二极连接所述第二电平端VB；O1用于在所述驱动电流的控制下显示灰阶；
所述储能单元C1的第二极连接所述供电电路VL；C1用于储存所述数据线Data的信号和驱动单元D16的阈值电压。
可选地，所述三个子像素电路中，第一子像素电路P1、第二子像素电路P2和第三子像素电路P3共用一条第一扫描线Scan1向所述第四开关单元(T12、T22和T32)的控制端输入第一扫描信号S1。由于三个子像素单元共用一条扫描线在一定程度上可以减少像素电路的信号线路数目，降低集成电路成本。
进一步的，所述第一子像素电路P1的第五开关单元T13的控制端连接所述第一扫描线Scan1，所述第一子像素电路P1的第一扫描信号S1和第三扫描信号S3时序相同。由于共用第一扫描线Scan1可以减少像素电路的信号线路数目，降低集成电路成本。
可选地，所述三个子像素电路中，第一子像素电路P1、第二子像素电路P2和第三子像素电路共用一条第二扫描线Scan2分别向所述第六开关单元(T14、T24和T34)的控制端和所述第七开关单元(T15、T25和T35)的控制端输入扫描信号S2和S4，其中所述第二扫描信号S2和第四扫描信号S4时序相同。由于三个子像素单元共用一条扫描线在一定程度上可以减少像素电路的信号线路数目，降低集成电路成本。
所述三个子像素电路中，所述第三子像素电路P3的第五开关单元T33的控制端连接所述第二扫描线Scan2，由于第二扫描线Scan2同时连接T33和T34的控制端，因此所述第三子像素电路P3中输入T33控制端的第三扫描信号S3和输入T34控制端的第二扫描信号S2时序相同。由于共用第二扫描线Scan2可以减少像素电路的信号线路数目，降低集成电路成本。
所述第二子像素电路P2的第五开关单元T23的控制端连接所述第三扫描线Scan3。
例如，第一电平为高电平VDD、第二电平为通过接地提供的低电平VSS。
图3为本公开如图2提供的像素电路中关键信号的时序图。图4-8分别为本公开如图2提供的像素电路中w1、w2、w3、w4、w5阶段的电流流向 示意图。下面以第一电平为VDD、第二电平为VSS为例，结合图3所示的信号时序图以及图4-8的电流流向示意图，对图2提供的像素电路的工作原理进行说明。其中，各个开关单元以薄膜晶体管(简称开关晶体管或TFT)为例，驱动单元以驱动型薄膜晶体管(简称驱动晶体管或DTFT)为例，储能单元以电容为例，电致发光单元为有机发光二极管OLED为例进行说明。图2中还示出第一扫描线Scan1，第二扫描线Scan2和第三扫描线Scan3，其中第三扫描线Scan3用于向P2中的T23提供第三扫描信号S3，开关晶体管T14、T24、T34以N型开关晶体管为例，其余各个开关单元均以P型开关晶体管为例进行说明，图3所示的信号时序图可分为五个阶段，分别表示为重置阶段w1，第一放电阶段w2、第二放电阶段w3、第三放电阶段w4，发光阶段w5。
在重置阶段w1，Scan1,Scan2，EM1上的信号均为低电平，除了T14、T24、T34、T23截止，其余TFT均导通，电容C1的第一极b1点与电容C2的第一极b2点，以及C3的第一极b3点都同时接地，三点电势为0V，第二极a1与a2及a3共三点都接入高电压VDD，由于T13和T33导通，D16的栅极d1与D36的栅极d3接入数据线的信号Vdata，电势为V1，参照图4示出了w1阶段的电流流向示意图。
在第一放电阶段w2，Scan1、Scan2和Scan3均为低电平，EM1为高电位，TFT导通情况是：T12、T22、T32、T13、T23、T33、T15、T25、T35导通，其他TFT截止，电容C1、C2和C3放电。图5中示出电容C1、C2和C3在各个子像素单元中的放电路径。电容C1、C2和C3放电直至a1点电势为V1+Vth1，a2点电势为V1+Vth2，a3点电势为V1+Vth3，其中Vth1、Vth2和Vth3分别为驱动单元D16、D26和D36的阈值电压。此放电过程，电流仍然不会通过电致发光单元(O1、O2和O3)。D16的栅极d1、D26的栅极d2和D36的栅极d3点接入数据线信号Vdata，电势为V1。
在第二放电阶段w3，Scan1转换为高电平，C1两端的电势差为V1+Vth1；Scan2和Scan3持续为低电平，EM1为高电平，TFT导通情况为：T23、T33、T15、T25、T35导通，其余TFT均截止，此时数据线的信号Vdata的电压为V2。第二子像素P2和第三子像素P3中的C2和C3继续放电(图6中示出了放电电流的路径)，电容C2的a2端电势变为V2+Vth2，电容C3的a3端 电势变为V2+Vth3，并为下面的阶段作准备。
在第三放电阶段w4，EM1、Scan1和Scan3都为高电平，Scan2为低电平，TFT导通情况为：T33、T15、T25、T35导通，其余TFT均截止。第三像素中的C3继续放电(图7中示出了放电电流的路径)，此时数据线的信号Vdata的电压为V3,所以电容C3的a3端电势变为V3+Vth3，并为下面的发光阶段作准备。
在发光阶段w5，即电致发光单元(O1、O2和O3)正式发光阶段，EM1为低电平，Scan1和Scan2、Scan3都为高电平，TFT导通情况为：T11、T21、T31、T14、T24、T34导通，其余TFT截止。三个电容C1的a1端、C2的a2端和C3的a3端接入第一电压端VA的高电平VDD，而电容C1的b1端、C2的b2端和C3的b3端浮接，均要保持原来的压差，因此会发生等压跳变，因此，d1点电势为VDD-V1-Vth1，d2点电势为VDD-V2-Vth2，d3点电势为VDD-V3-Vth3，图8中示出了该阶段电路中电流的流向路径。
根据饱和电流公式，流入O1的电流IOLED，由以下公式计算：
IOLED＝K(VGS-Vth1)2
＝K[VDD-(VDD-V1-Vth1)-Vth1]2
＝K·V12
其中，Vth1为驱动单元D16的阈值电压，上述Vth2为驱动单元D26的阈值电压，上述Vth3为驱动单元D36的阈值电压。
同理可以得到，流入O2的电流为IOLED＝K·V22，流入O3的电流为IOLED＝K·V32；VGS为驱动晶体管栅极和源极之间的电压，
Figure PCTCN2014089763-appb-000001
μ、Cox为工艺常数，W为TFT沟道宽度，L为薄膜晶体管的沟道长度，W、L都为可选择性设计的常数。
由上式中可以看到此时工作电流IOLED已经不受驱动晶体管阈值电压的影响，只与数据线Data上的电压(V1、V2和V3)有关。彻底解决了驱动晶体管由于工艺制程及长时间的操作造成阈值电压(Vth)漂移从而影响工作电流IOLED的问题，消除阈值电压对的影响，保证OLED的正常工作。
进一步的，所述供电电路VL可以仅包括一个开关单元，即第一开关单元T11，T11的控制端连接所述第一信号控制线EM1，T11的第一端连接所 述第一电平端VA，T11的第二端连接所述三个子像素电路，用于在所述第一信号控制线EM1的信号控制下向三个子像素电路提供第一电平端VA的第一电平。图9为本公开又一实施例提供的一种像素电路的结构示意图。如图9所示，供电电路VL此时仅包括一个TFT，进一步的降低电路布线复杂度，降低集成电路成本。以这种方式来压缩TFT器件个数，这样可大幅缩减子像素大小并降低IC成本，从而获得更高的画质品质。
本公开的实施例提供的像素电路，通过将相邻的三个子像素电路共用一条数据线，同时通过一个第一电平端向三个子像素电路提供工作电压，因此能够缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度；同时流经电致发光单元的工作电流不受对应的驱动晶体管的阈值电压的影响，彻底解决了由于驱动晶体管的阈值电压漂移导致显示亮度不均的问题。
第二实施例：
图10为本公开再一实施例提供的一种像素电路的结构示意图。参照图10所示，该像素电路包括三个子像素电路(P1、P2和P3)，和一个供电电路VL，所述三个子像素电路共用数据线Data；
其中，所述供电电路包括，第一开关单元T11，第二开关单元T21和第三开关单元T31；
T11的控制端连接第一信号控制线EM1，T11的第一端连接第一电平端VA，T11的第二端连接三个子像素电路中的第一子像素电路P1；T11用于在所述第一信号控制线EM1的信号控制下向第一子像素电路P1提供第一电平端的第一电平。
T21的控制端连接第一信号控制线EM1，T21的第一端连接第一电平端VA，T21的第二端连接三个子像素电路中的第二子像素电路P2；T21用于在所述第一信号控制线EM1的信号控制下向第二子像素电路P2提供第一电平端VA的第一电平。
T31的控制端连接第一信号控制线EM1，T31的第一端连接第一电平端VA，T31的第二端连接三个子像素电路中的第三子像素电路P3，T31用于在所述第一信号控制线EM1的信号控制下向第三子像素电路P3提供第一电平端VA的第一电平。
进一步的，所述子像素电路(P1、P2、P3)还连接第二信号控制线EM2和所述第一电平端VA，其中，每个所述子像素电路(P1、P2、P3)包括：四个开关单元、驱动单元、储能单元和电致发光单元；其中为了区分在P1中包括的四个开关单元依次为第八开关单元T12、第九开关单元T13、第十开关单元T14、第十一开关单元T15，驱动单元为D16、储能单元为C1、电致发光单元为O1；在P2中包括的四个开关单元依次为第八开关单元T22、第九开关单元T23、第十开关单元T24、第十一开关单元T25，驱动单元为D26、储能单元为C2、电致发光单元为O2；在P3中包括的四个开关单元依次为第八开关单元T32、第九开关单元T33、第十开关单元T34、第十一开关单元T35，驱动单元为D36、储能单元为C3、电致发光单元为O3；
以下仅以P1中的各器件的连接关系为例进行描述，P2、P3的器件连接关系参考P1不再赘述。
其中，储能单元C1的第一极a1连接所述第一电平端VA，用于将第一电平端VA的第一电平写入储能单元C1的第一极a1；
T12的控制端连接所述第二信号控制线EM2，T12的第一端连接所述储能单元C1的第二极b1，T12的第二端连接第二电平端VB；T12用于在第二信号控制线EM2的信号控制下将第二电平端VB的第二电平写入所述储能单元C1的第二极b1；
T13的控制端输入第二扫描信号S2，T13的第一端连接所述数据线Data，所述T13的第二端连接所述驱动单元D16的输出端；T13用于在所述第二扫描信号S2的控制下将所述数据线Data的信号写入所述驱动单元D16的输出端；
T14的控制端输入第一扫描信号S1，T14的第一端连接储能单元C1的第二极b1，T14的第二端连接所述驱动单元D16的输入端和所述供电电路VL；T14用于将数据线Data的信号和D16的阈值电压写入储能单元C1的第二极b1；
D16的控制端连接所述T14的第一端，用于在输出端输出驱动电流；
T15的控制端连接所述第一信号控制线EM1，T15的第一端连接所述D16的输出端；T15用于在所述第一信号控制线EM1的信号控制下控制所述驱动电流输入所述电致发光单元O1的第一极；
所述电致发光单元O1的第一极连接所述T15的第二端，所述电致发光单元O1的第二极连接所述第二电平端VB，用于在所述驱动电流的控制下显示灰阶。
可选地，同一个所述子像素电路中，第九开关单元(T13、T23或T33)的控制端和所述第十开关单元(T14、T24或T34)的控制端共用一条扫描线，使得所述第一扫描信号S1和第二扫描信号S2时序相同。如图10所示，P1中T13的控制端和T14的控制端连接第一扫描线Scan1，P2中T23的控制端和T24的控制端连接第二扫描线Scan2，P3中T33的控制端和T34的控制端连接第三扫描线Scan3。共用扫描线可以减少像素电路的信号线路数目，降低集成电路成本。
例如，第一电平为高电平VDD、第二电平为通过接地提供的低电平VSS。
图11为本公开如图10提供的像素电路中关键信号的时序图，图12-16为本公开如图10提供的像素电路中w1、w2、w3、w4、w5阶段的电流流向示意图。下面以第一电平为高电平VDD、第二电平为接地低电平VSS为例，结合图11所示的信号时序图以及图12-16的电流流向示意图，对图10提供的像素电路的工作原理进行说明。其中，各个开关单元以薄膜晶体管(简称开关晶体管或TFT)为例，驱动单元以驱动型薄膜晶体管(简称驱动晶体管或DTFT)为例，储能单元以电容为例，电致发光单元为有机发光二极管OLED为例进行说明。图11中还示出第一扫描线Scan1，第二扫描线Scan2和第三扫描线Scan3的时序信号，以各个开关单元均为P型开关晶体管为例进行说明，图11所示的信号时序图可分为五个阶段，分别表示为重置阶段w1，第一放电阶段w2、第二放电阶段w3、第三放电阶段w4，发光阶段w5。
在重置阶段w1，EM1、Scan1、Scan2和Scan3为高电平，EM2为低电平；各TFT的导通情况是：T12、T22、T32导通，其余TFT均截止，电容C1的第二极b1点与电容C2的第二极b2点，以及C3的第二极b3点都同时接地，三点电势为0V，第一极a1与a2及a3共三点都接入高电压VDD，参照图12示出了w1阶段的电流流向示意图。
在第一放电阶段w2，Scan1为低电平，Scan2、Scan3、EM1和EM2均为高电位，数据线的电平为V1，TFT导通情况是：T13、T14导通，其余TFT均截止，电容C1放电，图13中示出C1在子像素单元P1中的放电路径，直 至b1点电势为V1-Vth1，a1点电势为VDD，其中Vth1为驱动单元D16的阈值电压。
在第二放电阶段w3，Scan2为低电平，Scan1、Scan3、EM1和EM2均为高电位，数据线的电平为V2，TFT导通情况是：T23、T24导通，其余TFT均截止，电容C2放电，图14中示出C2在子像素单元P2中的放电路径，直至b2点电势为V2-Vth2，a2点电势为VDD，其中Vth2为驱动单元D26的阈值电压。
在第三放电阶段w4，Scan3为低电平，Scan1、Scan2、EM1和EM2均为高电位，数据线的电平为V3，TFT导通情况是：T33、T34导通，其余TFT均截止，电容C3放电，图15中示出C3在子像素单元P3中的路径放电路径，直至b3点电势为V3-Vth3，a3点电势为VDD，其中Vth3为驱动单元D36的阈值电压。
在发光阶段w5，即电致发光单元(O1、O2和O3)正式发光阶段，EM1为低电平，Scan1、Scan2、Scan3和EM2都为高电平，TFT导通情况为：T11、T21、T31、T15、T25、T35导通，其余TFT截止。电容C1的a1端、C2的a2端和C3的a3端接入第一电压端VA的高电平VDD，而电容C1、C2和C3均保持原来的压差，D16的栅极b1点电势为V1-Vth1，D26的栅极b2点电势为V2-Vth2，D36的栅极b3点电势为V3-Vth3，图16中示出了该阶段电路中电流的流向。
根据饱和电流公式，流入O1的电流IOLED，由以下公式计算：
IOLED＝K(VGS-Vth1)2
＝K[VDD-(V1-Vth1)-Vth1]2
＝K·(VDD-V1)2
其中，Vth1为驱动单元D16的阈值电压，Vth2为驱动单元D26的阈值电压，Vth3为驱动单元D36的阈值电压。
同理可以得到，流入O2的电流为IOLED＝K·(VDD-V2)2，流入O3的电流为IOLED＝K·(VDD-V3)2；VGS为驱动晶体管栅极和源极之间的电压，
Figure PCTCN2014089763-appb-000002
μ、Cox为工艺常数，W为TFT沟道宽度，L为薄膜晶体管的沟道长度，W、L都为可选择性设计的常数。
由上式中可以看到此时工作电流IOLED已经不受驱动晶体管阈值电压的影响，只与数据线Data电压(V1、V2和V3)有关。彻底解决了驱动晶体管由于工艺制程及长时间的操作造成阈值电压(Vth)漂移从而影响工作电流IOLED的问题，消除阈值电压对IOLED的影响，保证OLED的正常工作。
进一步的，所述供电电路VL可以仅包括一个开关单元，即第一开关单元T11，T11的控制端连接所述第一信号控制线EM1，T11的第一端连接所述第一电平端VA，T11的第二端连接所述三个子像素电路，用于在所述第一信号控制线EM1的信号控制下向三个子像素电路提供第一电平端VA的第一电平。图17为本公开另一实施例提供的一种像素电路的结构示意图。如图17所示，供电电路VL此时仅包括一个TFT，进一步的降低电路布线复杂度，降低集成电路成本。以这种方式来压缩TFT器件个数，这样可大幅缩减子像素大小并降低IC成本，从而获得更高的画质品质。
本公开的实施例提供的像素电路，通过将相邻的三个子像素电路共用一条数据线，同时通过一个第一电平端向三个子像素电路提供工作电压，因此能够缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度；同时流经电致发光单元的工作电流不受对应的驱动晶体管的阈值电压的影响，彻底解决了由于驱动晶体管的阈值电压漂移导致显示亮度不均的问题。
第三实施例：
图18为本公开又一实施例提供的一种像素电路的结构示意图。参照图18所示，该像素电路包括三个子像素电路(P1、P2和P3)，和一个供电电路VL，所述三个子像素电路共用数据线Data；
其中，所述供电电路VL包括，第一开关单元T11，第二开关单元T21和第三开关单元T31；
T11的控制端连接所述第一信号控制线EM1，T11的第一端连接所述第一电平端VA，T11的第二端连接三个子像素电路中的第一子像素电路P1，供电电路VL用于在所述第一信号控制线EM1的信号控制下向第一子像素电路P1提供第一电平端VA的第一电平。
T21的控制端连接所述第一信号控制线EM1，T21的第一端连接所述第一电平端VA，T21的第二端连接三个子像素电路中的第二子像素电路P2， 供电电路VL用于在所述第一信号控制线EM1的信号控制下向第二子像素电路P2提供第一电平端VA的第一电平。
T31的控制端连接所述第一信号控制线EM1，T31的第一端连接所述第一电平端VA，T31的第二端连接三个子像素电路中的第三子像素电路P3，供电电路VL用于在所述第一信号控制线EM1的信号控制下向第三子像素电路P3提供第一电平端VA的第一电平。
进一步的，所述子像素电路(P1、P2、P3)还连接第二信号控制线EM2和第三信号控制线EM3，其中，每个所述子像素电路(P1、P2、P3)包括：四个开关单元、驱动单元、储能单元和电致发光单元；其中为了区分，在P1中包括的四个开关单元依次为第十二开关单元T12、第十三开关单元T13、第十四开关单元T14、第十五开关单元T15，驱动单元为D16、储能单元为C1、电致发光单元为O1；在P2中包括的四个开关单元依次为第十二开关单元T22、第十三开关单元T23、第十四开关单元T24、第十五开关单元T25、驱动单元为D26、储能单元为C2、电致发光单元为O2；在P3中包括的四个开关单元依次为第十二开关单元T32、第十三开关单元T33、第十四开关单元T34、第十五开关单元T35，驱动单元为D36、储能单元为C3、电致发光单元为O3；
以下仅以P1中的各器件的连接关系为例进行描述，P2、P3的器件连接关系参考P1不再赘述。
其中，T12的控制端输入第一扫描信号S1，T12的第一端连接所述数据线Data，T12的第二端连接所述C1的第一极a1；T12用于在所述第一扫描信号的控制下将所述数据线的信号写入所述C1的第一极a1；
T13的控制端连接所述第二信号控制线EM2，所述T13的第一端连接所述T12的第二端，所述T13的第二端连接第二电平端VB；T13用于在所述第二信号控制线EM2的信号控制下将所述第二电平端VB的第二电平写入所述C1的第一极a1；
T14的控制端连接第二信号控制线EM2，所述T14的第一端连接所述C1的第二极b1，第二端连接驱动单元D16的输出端；T14用于在第二信号控制线EM2的信号控制下将第一电平和D16的阈值电压写入所述C1的第二极b1；
所述D16的输入端连接所述供电电路VL，所述D16的控制端连接所述C1的第二极b1，所述D16的输出端连接所述T14的第二端；D16用于在输出端输出驱动电流；
T15的控制端连接第三信号控制线EM3，所述T15的第一端连接所述D16的输出端；T15用于在所述第三信号控制线EM3的信号控制下控制所述驱动电流输入所述电致发光单元O1的第一极；
所述电致发光单元O1的第一极连接所述T15的第二端，第二极连接所述第二电平端VB；所述电致发光单元O1用于在所述驱动电流的控制下显示灰阶。
例如，第一电平为高电平VDD、第二电平为通过接地提供的低电平VSS。
图19为本公开如图18提供的像素电路中关键信号的时序图，图20-24为本公开如图18提供的像素电路中w1、w2、w3、w4、w5阶段的电流流向示意图。下面以第一电平为高电平VDD、第二电平为接地低电平VSS为例，结合图19所示的信号时序图和图20-24的电流流向示意图，对图18提供的像素电路的工作原理进行说明。其中，各个开关单元以薄膜晶体管(简称开关晶体管或TFT)为例，驱动单元以驱动型薄膜晶体管(简称驱动晶体管或DTFT)为例，储能单元以电容为例，电致发光单元为有机发光二极管OLED为例进行说明。图19中示出EM1，EM2，EM3，第一扫描线Scan1，第二扫描线Scan2和第三扫描线Scan3的时序信号，其中第一扫描线Scan向P1的T12提供第一扫描信号；第二扫描线Scan2用于向P2的T22提供第一扫描信号；第三扫描线Scan3用于向P3的T32提供第一扫描信号；以各个开关单元均以P型开关晶体管为例进行说明，图18所示的信号时序图可分为五个阶段，分别表示为充电阶段w1，第一像素补偿阶段w2、第二像素补偿阶段w3、第三像素补偿阶段w4，发光阶段w5。
在充电阶段w1，Scan1、Scan2、Scan3、EM3为高电平，EM1、EM2为低电平；各TFT的导通情况是：T12、T22、T32、T15、T25和T35截止，其余TFT均导通，电容C1、C2和C3沿图20所示的电流流向放电，直至b1点电势为VDD-Vth1，b2点电势为VDD-Vth2，b3点电势为VDD-Vth3，其中Vth1、Vth2、Vth3分别为D16、D26和D36的阈值电压。此放电过程，电流不会通过O1、O2和O3。a1、a2和a3点接地，电势都为0V。
在第一像素补偿阶段w2，Scan1为低电平，Scan2、Scan3、EM1、EM2和EM3均为高电位，数据线的电平为V1，TFT导通情况是：T12导通，其余TFT均截止，此时a1点电势由原来的0V变为V1，而b1点为浮接状态，因此要维持a1、b1两点原来的压差(VDD-Vth1)，D16的栅极b1点电势会发生等压跳变，b1点电势跳变为VDD–Vth1+V1，图21中示出第一像素补偿阶段电流的流动路径。
在第二像素补偿阶段w3，Scan2为低电平，Scan1、Scan3、EM1、EM2和EM3均为高电位，数据线的电平为V2，TFT导通情况是：T22导通，其余TFT均截止，此时a2点电势由原来的0V变为V2，而b2点为浮接状态，因此要维持a2、b2两点原来的压差(VDD-Vth2)，D26的栅极b2点电势会发生等压跳变，b2点电势跳变为VDD–Vth2+V2，图22中示出第二像素补偿阶段电流的流动路径。
在第三像素补偿阶段w4，Scan3为低电平，Scan1、Scan2、EM1、EM2和EM3均为高电位，数据线的电平为V3，TFT导通情况是：T32导通，其余TFT均截止，此时a3点电势由原来的0V变为V3，而b3点为浮接状态，因此要维持a3、b3两点原来的压差(VDD-Vth3)，D36的栅极b3点电势会发生等压跳变，b3点电势跳变为VDD–Vth3+V3，图23中示出第三像素补偿阶段电路流动路径。
在发光阶段w5，即电致发光单元(O1、O2和O3)正式发光阶段，EM1、EM3为低电平，Scan1、Scan2、Scan3和EM2都为高电平，TFT导通情况为：T11、T21、T31、T15、T25、T35导通，其余TFT截止。
三个子像素电路接入第一电压端VA的高电平VDD，而电容C1、C2和C3均保持原来的压差，b1点电势为VDD-Vth1+V1，b2点电势为VDD-Vth2+V2，b3点电势为VDD-Vth3+V3，图24中示出了该阶段电路中电流的流向。
根据饱和电流公式，流入O1的电流IOLED，由以下公式计算：
IOLED＝K(VGS-Vth1)2
＝K[VDD-(VDD-Vth1+V1)-Vth1]2
＝K·V12
其中，Vth1为驱动单元D16的阈值电压，Vth2为驱动单元D26的阈值电压，Vth3为驱动单元D36的阈值电压。
同理可以得到，流入O2的电流为IOLED＝K·V22，流入O3的电流为IOLED＝K·V32；VGS为驱动晶体管栅极和源极之间的电压，
Figure PCTCN2014089763-appb-000003
μ、Cox为工艺常数，W为TFT沟道宽度，L为薄膜晶体管的沟道长度，W、L都为可选择性设计的常数。
由上式中可以看到此时工作电流IOLED已经不受驱动晶体管阈值电压的影响，只与数据线Data电压(V1、V2和V3)有关。彻底解决了驱动晶体管由于工艺制程及长时间的操作造成阈值电压(Vth)漂移从而影响工作电流IOLED的问题，消除阈值电压对IOLED的影响，保证OLED的正常工作。
进一步的，所述供电电路VL可以仅包括一个开关单元，即第一开关单元T11，T11的控制端连接所述第一信号控制线EM1，T11的第一端连接所述第一电平端VA，T11的第二端连接所述三个子像素电路，用于在所述第一信号控制线EM1的信号控制下向三个子像素电路提供第一电平端VA的第一电平。图25为本公开再一实施例提供的一种像素电路的结构示意图。如图25所示，供电电路VL此时仅包括一个TFT，进一步的降低电路布线复杂度，降低集成电路成本。以这种方式来压缩TFT器件个数，这样可大幅缩减子像素大小并降低IC成本，从而获得更高的画质品质。
本公开的实施例提供的像素电路，通过将相邻的三个子像素电路共用一条数据线，同时通过一个第一电平端向三个子像素电路提供工作电压，因此能够缩减显示装置中用于像素电路的信号线路数目，降低集成电路成本，同时提高显示装置的像素密度；同时流经电致发光单元的工作电流不受对应的驱动晶体管的阈值电压的影响，彻底解决了由于驱动晶体管的阈值电压漂移导致显示亮度不均的问题。
本公开的实施例提供一种显示装置，包括上述任一像素电路。
图26-28分别为本公开实施例提供的显示装置中像素电路与像素的位置关系的示意图。可选地，所述三个子像素电路位于数据线的同一侧。参照图26所示，子像素电路P1、子像素电路P2、子像素电路P3、位于数据线Data的同一侧，即位于两条数据线Data之间，其中P1、P2和P3构成一个像素 电路。
可选地，参照图27所示，像素电路的三个子像素电路位于相邻的两个像素内，其中所述三个子像素电路中相邻的第一子像素电路和第二子像素电路位于第一像素内，第三子像素电路位于第二像素内；如图27所示，子像素电路P1和子像素电路P2位于第一像素内；子像素电路P3位于第二像素内；
可选地，参照图28所示，其中所述三个子像素中第一子像素电路位于第一像素内，相邻的第二子像素电路和第三子像素电路位于第二像素内。
其中第一像素和第二像素相邻，如图28所示，子像素电路P1位于第一像素内；子像素电路P2和子像素电路P3位于第二像素内；其中参照图27和28所示，数据线Data位于第一像素和第二像素之间。这样能够使得元器件在相应的基板上的分布更加均匀，以上图26、27、28中还示出了与数据线Data交叉的栅线Gata。
显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2014年7月17日递交的中国专利申请第201410342198.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种像素电路，包括三个子像素电路和一个供电电路，所述三个子像素电路共用数据线；
    所述供电电路连接第一电平端、第一信号控制线和所述子像素电路，所述供电电路用于在所述第一信号控制线的信号控制下通过所述第一电平端向所述子像素电路提供第一电平；
    所述子像素电路连接所述供电电路和所述数据线，用于在所述供电电路提供的第一电平和所述数据线的数据信号控制下显示灰阶。
  2. 根据权利要求1所述的像素电路，其中，所述供电电路包括第一开关单元，所述第一开关单元的控制端连接所述第一信号控制线，所述第一开关单元的第一端连接所述第一电平端，所述第一开关单元的第二端连接所述三个子像素电路，用于在所述第一信号控制线的信号控制下向三个子像素电路提供第一电平端的第一电平。
  3. 根据权利要求1所述的像素电路，其中，所述供电电路包括，第一开关单元，第二开关单元和第三开关单元；
    所述第一开关单元的控制端连接所述第一信号控制线，所述第一开关单元的第一端连接所述第一电平端，所述第一开关单元的第二端连接三个子像素电路中的第一子像素电路，用于在所述第一信号控制线的信号控制下向第一子像素电路提供第一电平端的第一电平；
    所述第二开关单元的控制端连接所述第一信号控制线，所述第二开关单元的第一端连接所述第一电平端，所述第二开关单元的第二端连接三个子像素电路中的第二子像素电路，用于在所述第一信号控制线的信号控制下向第二子像素电路提供第一电平端的第一电平；
    所述第三开关单元的控制端连接所述第一信号控制线，所述第三开关单元的第一端连接所述第一电平端，所述第三开关单元的第二端连接三个子像素电路中的第三子像素电路，用于在所述第一信号控制线的信号控制下向第三子像素电路提供第一电平端的第一电平。
  4. 根据权利要求1至3中任一项所述的像素电路，其中，每个所述子像素电路包括：分别为第四至第七开关单元的四个开关单元、驱动单元、储能 单元和电致发光单元；
    其中，第四开关单元的控制端输入第一扫描信号，第四开关单元的第一端连接第二电平端，第四开关单元的第二端连接储能单元的第一极，第四开关单元用于在所述第一扫描信号的控制下将所述第二电平端的信号写入所述储能单元的第一极；
    第五开关单元的控制端输入第三扫描信号，第五开关单元的第一端连接所述数据线，第五开关单元用于在所述第三扫描信号的控制下将数据线的信号在所述第五开关单元的第二端输出；
    第六开关单元的控制端输入第二扫描信号，第六开关单元的第一端连接所述储能单元的第一极，所述第六开关单元的第二端连接所述第五开关单元的第二端，第六开关单元用于在所述第二扫描信号的控制下将所述数据线的信号写入所述储能单元的第一极以耦合抬升所述储能单元第二极的电平；
    驱动单元的控制端连接所述第六开关单元的第二端，驱动单元的输入端连接储能单元的第二极，驱动单元用于输出驱动电流；
    第七开关单元的控制端输入第四扫描信号，所述第七开关单元的第一端连接所述驱动单元的输出端，所述第七开关单元的第二端连接所述第二电平端，第七开关单元用于在所述第四扫描信号的控制下控制所述驱动电流输入所述电致发光单元的第一极；
    所述电致发光单元的第一极连接所述驱动单元的输出端，所述电致发光单元的第二极连接所述第二电平端，电致发光单元用于在所述驱动电流的控制下显示灰阶；
    所述储能单元的第二极连接所述供电电路，储能单元用于储存所述数据线的信号和驱动单元的阈值电压。
  5. 根据权利要求4所述的像素电路，其中，所述三个子像素电路中，第一子像素电路、第二子像素电路和第三子像素电路共用一条第一扫描线向所述第四开关单元的控制端输入第一扫描信号。
  6. 根据权利要求5所述的像素电路，其中，所述第一子像素电路的第五开关单元的控制端连接所述第一扫描线，所述第一子像素电路的第一扫描信号和第三扫描信号时序相同。
  7. 根据权利要求4至6中任一项所述的像素电路，其中，所述三个子像 素电路中，第一子像素电路、第二子像素电路和第三子像素电路共用一条第二扫描线分别向所述第六开关单元的控制端和所述第七开关单元的控制端输入第二扫描信号和第四扫描信号，其中所述第二扫描信号和第四扫描信号时序相同。
  8. 根据权利要求7所述的像素电路，其中，所述三个子像素电路中，所述第三子像素电路的第五开关单元的控制端连接所述第二扫描线，所述第三子像素电路中输入第五开关单元控制端的第三扫描信号和输入第六开关单元控制端的第二扫描信号时序相同。
  9. 根据权利要求1至3中任一项所述的像素电路，其中，所述子像素电路还连接第二信号控制线和所述第一电平端，其中，每个所述子像素电路包括：分别为第八至第十一开关单元的四个开关单元、驱动单元、储能单元和电致发光单元；
    其中，储能单元的第一极连接所述第一电平端，用于将第一电平端的第一电平写入储能单元的第一极；
    第八开关单元的控制端连接所述第二信号控制线，第八开关单元的第一端连接所述储能单元的第二极，第八开关单元的第二端连接第二电平端，第八开关单元用于在第二信号控制线的信号控制下将第二电平端的第二电平写入所述储能单元的第二极；
    第九开关单元的控制端输入第二扫描信号，第九开关单元的第一端连接所述数据线，所述第九开关单元的第二端连接所述驱动单元的输出端，第九开关单元用于在所述第二扫描信号的控制下将所述数据线的信号写入所述驱动单元的输出端；
    第十开关单元的控制端输入第一扫描信号，第十开关单元的第一端连接储能单元的第二极，第十开关单元的第二极连接所述驱动单元的输入端和所述供电电路，第十开关单元用于将数据线的信号和所述驱动单元的阈值电压写入所述储能单元的第二极；
    驱动单元的控制端连接所述第十开关单元的第一端，用于在输出端输出驱动电流；
    第十一开关单元的控制端连接所述第一信号控制线，所述第十一开关单元的第一端连接所述驱动单元的输出端，第十一开关单元用于在所述第一信 号控制线的信号控制下控制所述驱动电流输入所述电致发光单元的第一极；
    所述电致发光单元的第一极连接所述第十一开关单元的第二端，所述电致发光单元的第二极连接所述第二电平端，所述电致发光单元用于在所述驱动电流的控制下显示灰阶。
  10. 根据权利要求9所述的像素电路，其中，同一个所述子像素电路中，第九开关单元的控制端和所述第十开关单元的控制端共用一条扫描线，使得所述第一扫描信号和第二扫描信号时序相同。
  11. 根据权利要求1至3中任一项所述的像素电路，其中，所述子像素电路还连接第二信号控制线和第三信号控制线，其中，每个所述子像素电路包括：分别为第十二至第十五开关单元的四个开关单元、驱动单元、储能单元和电致发光单元；
    其中，第十二开关单元的控制端输入第一扫描信号，第十二开关单元的第一端连接所述数据线，第十二开关单元的第二端连接所述储能单元的第一极，第十二开关单元用于在所述第一扫描信号的控制下将所述数据线的信号写入所述储能单元的第一极；
    第十三开关单元的控制端连接所述第二信号控制线，所述第十三开关单元的第一端连接所述第十二开关单元的第二端，所述第十三开关单元的第二端连接第二电平端，第十三开关单元用于在所述第二信号控制线的信号控制下将所述第二电平端的第二电平写入所述储能单元的第一极；
    第十四开关单元的控制端连接第二信号控制线，所述第十四开关单元的第一端连接所述储能单元的第二极，第一端连接所述驱动单元的输出端，第十四开关单元用于在第二信号控制线的信号控制下将第一电平和驱动单元的阈值电压写入所述储能单元的第二极；
    所述驱动单元的输入端连接所述供电电路，所述驱动单元的控制端连接所述储能单元的第二极，所述驱动单元的输出端连接所述第十四开关单元的第二端，所述驱动单元用于在输出端输出驱动电流；
    第十五开关单元的控制端连接第三信号控制线，所述第十五开关单元的第一端连接所述驱动单元的输出端，第十五开关单元用于在所述第三信号控制线的信号控制下控制所述驱动电流输入所述电致发光单元的第一极；
    所述电致发光单元的第一极连接所述第十五开关单元的第二端，第二极 连接所述第二电平端，所述电致发光单元用于在所述驱动电流的控制下显示灰阶。
  12. 根据权利要求2-11任一项所述的像素电路，其中，开关单元和驱动单元为薄膜晶体管，各个开关单元的控制端为薄膜晶体管的栅极，各个开关单元的第一端为薄膜晶体管的源极，各个开关单元的第二端为薄膜晶体管的漏极，所述驱动单元的输入端为薄膜晶体管的源极，所述驱动单元的控制端为薄膜晶体管的栅极，所述驱动单元的输出端为薄膜晶体管的漏极。
  13. 根据权利要求2-11任一项所述的像素电路，其中，所述储能单元为电容。
  14. 根据权利要求2-11任一项所述的像素电路，其中，所述电致发光单元为有机发光二极管。
  15. 一种包括如权利要求1-14任一项所述的像素电路的显示装置。
  16. 根据权利要求15所述的显示装置，其中，所述像素电路的三个子像素电路位于同一像素内。
  17. 根据权利要求16所述的显示装置，其中，所述三个子像素电路位于数据线的同一侧。
  18. 根据权利要求15所述的显示装置，其中，所述像素电路的三个子像素电路位于相邻的两个像素内，其中所述三个子像素电路中相邻的第一子像素电路和第二子像素电路位于第一像素内，第三子像素电路位于第二像素内；
    或者，其中所述三个子像素电路中第一子像素电路位于第一像素内，相邻的第二子像素电路和第三子像素电路位于第二像素内，
    其中第一像素和第二像素相邻。
  19. 根据权利要求18所述的显示装置，其中，数据线位于所述第一像素和第二像素之间。
PCT/CN2014/089763 2014-07-17 2014-10-29 像素电路和显示装置 WO2016008232A1 (zh)

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104464641B (zh) * 2014-12-30 2017-03-08 昆山国显光电有限公司 像素电路及其驱动方法和有源矩阵有机发光显示装置
KR102522534B1 (ko) * 2016-07-29 2023-04-18 엘지디스플레이 주식회사 유기발광 표시장치와 그 구동방법
CN106782309A (zh) * 2017-02-23 2017-05-31 京东方科技集团股份有限公司 像素驱动电路、像素驱动电路的驱动方法及显示装置
CN109427266A (zh) * 2017-09-01 2019-03-05 创王光电股份有限公司 显示器系统
CN109523954B (zh) * 2018-12-24 2020-12-22 合肥鑫晟光电科技有限公司 像素单元、显示面板、驱动方法以及补偿控制方法
TWI699748B (zh) * 2019-01-31 2020-07-21 友達光電股份有限公司 顯示裝置
KR20200105598A (ko) * 2019-02-28 2020-09-08 삼성디스플레이 주식회사 표시 장치
CN110599963A (zh) * 2019-09-25 2019-12-20 京东方科技集团股份有限公司 像素驱动电路、阵列基板、显示装置及像素驱动方法
CN112767873B (zh) * 2019-11-01 2022-03-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示面板、显示装置
CN111063301B (zh) * 2020-01-09 2024-04-12 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006309155A (ja) * 2005-01-31 2006-11-09 Toshiba Matsushita Display Technology Co Ltd 表示装置、アレイ基板、及び表示装置の駆動方法
CN102982766A (zh) * 2012-12-10 2013-03-20 友达光电股份有限公司 一种像素补偿电路
CN103218972A (zh) * 2013-04-15 2013-07-24 京东方科技集团股份有限公司 像素电路、像素电路驱动方法及显示装置
CN203689881U (zh) * 2013-12-27 2014-07-02 合肥京东方光电科技有限公司 像素驱动电路、阵列基板和显示装置
CN103927978A (zh) * 2013-12-31 2014-07-16 厦门天马微电子有限公司 Amoled显示面板及有机发光显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW587239B (en) * 1999-11-30 2004-05-11 Semiconductor Energy Lab Electric device
JP2004151194A (ja) * 2002-10-29 2004-05-27 Tohoku Pioneer Corp アクティブ型発光表示パネルの駆動装置
US7502001B2 (en) * 2003-03-12 2009-03-10 Koninklijke Philips Electronics N.V. Light emissive active matrix display devices with optical feedback effective on the timing, to counteract ageing
JP4062179B2 (ja) * 2003-06-04 2008-03-19 ソニー株式会社 画素回路、表示装置、および画素回路の駆動方法
KR100581810B1 (ko) * 2004-08-25 2006-05-23 삼성에스디아이 주식회사 발광 표시장치와 그의 구동방법
KR100592636B1 (ko) * 2004-10-08 2006-06-26 삼성에스디아이 주식회사 발광표시장치
KR101152120B1 (ko) * 2005-03-16 2012-06-15 삼성전자주식회사 표시 장치 및 그 구동 방법
KR100761077B1 (ko) * 2005-05-12 2007-09-21 삼성에스디아이 주식회사 유기 전계발광 표시장치
KR100882907B1 (ko) * 2007-06-21 2009-02-10 삼성모바일디스플레이주식회사 유기전계발광표시장치
KR101748857B1 (ko) * 2010-10-28 2017-06-20 삼성디스플레이 주식회사 유기전계발광 표시장치
JP5795893B2 (ja) * 2011-07-07 2015-10-14 株式会社Ｊｏｌｅｄ 表示装置、表示素子、及び、電子機器
US8928650B2 (en) * 2012-04-20 2015-01-06 Optoelectronics Technology Co., Ltd Display panel and 3D display device
TWI481937B (zh) * 2012-08-27 2015-04-21 Au Optronics Corp 顯示面板
KR101992405B1 (ko) * 2012-12-13 2019-06-25 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
WO2014125752A1 (ja) * 2013-02-15 2014-08-21 シャープ株式会社 表示装置およびその駆動方法
KR20140140271A (ko) * 2013-05-29 2014-12-09 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR20140141373A (ko) * 2013-05-31 2014-12-10 삼성디스플레이 주식회사 유기발광 디스플레이 장치 및 그 제조방법
US9773443B2 (en) * 2013-06-06 2017-09-26 Intel Corporation Thin film transistor display backplane and pixel circuit therefor
CN103472644B (zh) * 2013-09-25 2015-11-25 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006309155A (ja) * 2005-01-31 2006-11-09 Toshiba Matsushita Display Technology Co Ltd 表示装置、アレイ基板、及び表示装置の駆動方法
CN102982766A (zh) * 2012-12-10 2013-03-20 友达光电股份有限公司 一种像素补偿电路
CN103218972A (zh) * 2013-04-15 2013-07-24 京东方科技集团股份有限公司 像素电路、像素电路驱动方法及显示装置
CN203689881U (zh) * 2013-12-27 2014-07-02 合肥京东方光电科技有限公司 像素驱动电路、阵列基板和显示装置
CN103927978A (zh) * 2013-12-31 2014-07-16 厦门天马微电子有限公司 Amoled显示面板及有机发光显示装置

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US20190073963A1 (en) 2019-03-07
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US10943545B2 (en) 2021-03-09
US20160163267A1 (en) 2016-06-09

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