WO2016002058A1 - Dispositif à semi-conducteur, son procédé de fabrication, module de puissance et dispositif de conversion de puissance - Google Patents

Dispositif à semi-conducteur, son procédé de fabrication, module de puissance et dispositif de conversion de puissance Download PDF

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WO2016002058A1
WO2016002058A1 PCT/JP2014/067841 JP2014067841W WO2016002058A1 WO 2016002058 A1 WO2016002058 A1 WO 2016002058A1 JP 2014067841 W JP2014067841 W JP 2014067841W WO 2016002058 A1 WO2016002058 A1 WO 2016002058A1
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epitaxial layer
semiconductor device
degrees
sic substrate
type
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PCT/JP2014/067841
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Japanese (ja)
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望月　和浩
宏行 松島
三木　浩史
廉一 山田
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株式会社日立製作所
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Priority to JP2016530773A priority patent/JP6282346B2/ja
Publication of WO2016002058A1 publication Critical patent/WO2016002058A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, a power module, a power conversion device, a three-phase motor system, an automobile, and a railway vehicle.
  • Patent Document 1 JP 2009-302436 A
  • carbonization is performed to form a p-type deep layer to a deeper position by implanting p-type impurities by oblique ion implantation inclined in a direction to cancel the off angle.
  • a method for manufacturing a silicon semiconductor device is described.
  • the present invention provides a silicon carbide semiconductor device having excellent breakdown voltage characteristics.
  • a p-type impurity is added to an n-type 4H—SiC substrate whose surface is turned off from the (0001) plane by 4 degrees in the [11-20] direction [
  • the ions are implanted in a direction inclined at an angle of 0 ° or more from the [000-1] direction to the [11-20] direction, or from 0 ° to less than 4 ° from the [000-1] direction to the [ ⁇ 1-120] direction, and n
  • An FLR is formed on the epitaxial layer of 4H—SiC formed on the surface of the mold 4H—SiC substrate.
  • the angle formed between the upper surface of the epitaxial layer and the metallurgical boundary of the FLR is less than 90 degrees at the end of the upper surface of the epitaxial layer opposite to the off direction of the FLR.
  • a silicon carbide semiconductor device having excellent breakdown voltage characteristics can be provided.
  • FIG. 6 is a cross-sectional view of a principal part of a Schottky barrier diode for explaining an embodiment of FLR formed by ion implantation of p-type impurities.
  • FIG. 5 is an enlarged cross-sectional view showing the surface warpage of an n-type 4H—SiC substrate having a substrate diameter of 6 inches. The simulation result of the FLR shape by Example 1 is shown.
  • (A) shows the simulation result of the FLR shape when Al ions are implanted in the [000-1] direction.
  • (B) shows the simulation results of the FLR shape when Al ions are implanted in a direction inclined by 4 degrees from the [000-1] direction to the [-1-120] direction.
  • (C) shows the simulation results of the FLR shape when Al ions are implanted in the direction inclined by 8 degrees from the [000-1] direction to the [-1-120] direction.
  • the simulation result of the FLR shape by Example 1 is shown.
  • (A) shows the simulation results of the FLR shape when Al ions are implanted in a direction inclined by 4 degrees from the [000-1] direction to the [11-20] direction.
  • (B) shows the simulation result of the FLR shape when Al ions are implanted in a direction inclined by 8 degrees from the [000-1] direction to the [11-20] direction.
  • (C) shows the simulation result of the FLR shape when Al ions are implanted in a direction inclined by 12 degrees from the [000-1] direction to the [11-20] direction.
  • (D) shows the simulation result of the FLR shape when Al ions are implanted in a direction inclined 16 degrees from the [000-1] direction to the [11-20] direction.
  • the avalanche breakdown voltage at room temperature of the pn diode formed on the n-type 4H—SiC substrate whose surface was turned off by 4 degrees from the (0001) plane in the [11-20] direction according to Example 1, and the FLR (metallurgical region) It is a graph explaining the relationship with depth.
  • FIG. 4 is a plan view of a principal part showing one example of a semiconductor device having a Schottky barrier diode formed on an n-type 4H—SiC substrate according to Example 1;
  • FIG. FIG. 6 is a main part sectional view showing an example of a semiconductor device having a Schottky barrier diode formed on an n-type 4H—SiC substrate according to Example 1 (main part sectional view taken along the line AA ′ in FIG. 9); is there. 6 is a process diagram illustrating an example of a method of manufacturing a semiconductor device according to Example 1.
  • FIG. FIG. 10 is a sectional view of a key portion showing one example of a manufacturing process of a semiconductor device according to Example 1.
  • FIG. 13 is a main part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 12;
  • FIG. 14 is an essential part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 13;
  • FIG. 15 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 14;
  • FIG. 16 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 15;
  • FIG. 17 is a main part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 16;
  • FIG. 6 is a cross-sectional view of a principal part showing one example of a MOSFET formed on an n-type 4H—SiC substrate constituting a switching element according to Example 2.
  • FIG. 6 is a cross-sectional view of a principal part showing one example of a MOSFET formed on an n-type 4H—SiC substrate constituting a switching element according to Example 2.
  • FIG. 6 is a
  • FIG. 6 is a circuit diagram showing an example of a power conversion device (inverter) in which a Schottky barrier diode formed on an n-type 4H—SiC substrate according to Example 3 is connected to a switching element as a freewheeling diode.
  • FIG. 6 is a schematic diagram illustrating an example of a configuration of an electric vehicle according to a fourth embodiment.
  • FIG. 10 is a circuit diagram illustrating an example of a boost converter according to a fourth embodiment.
  • FIG. 10 is a circuit diagram illustrating an example of a converter and an inverter provided in a railway vehicle according to a fifth embodiment.
  • the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
  • the present inventors use an n-type 4H—SiC substrate whose surface is turned off by 4 degrees from the (0001) plane in the [11-20] direction, and uses a guard ring made of a p-type semiconductor region and one or more of them.
  • a Schottky barrier diode having an FLR was fabricated and its breakdown voltage was measured.
  • the guard ring and the FLR are provided on the outer periphery of the semiconductor device, the guard ring alleviates the electric field concentration at the end of the anode electrode, and the FLR is the end of the guard ring or, in the case of a plurality of FLRs, the inner FLR. It has a function to alleviate electric field concentration at the end.
  • a patterned mask material layer 20 is formed on the surface of an n-type 4H—SiC substrate 10, and p-type impurities are ionized into the n-type 4H—SiC substrate 10 exposed from the mask material layer 20.
  • a guard ring 30 and three FLRs 40 spaced apart from each other were formed.
  • p-type impurities are ion-implanted in a direction inclined from 0 ° to 4 ° from the [000-1] direction to the [-1-120] direction.
  • the standard deviation in the substrate surface was equal to or less than 20% of the average value.
  • the breakdown voltage at room temperature of a pn diode provided with one FLR was obtained by simulation.
  • the pn diode is used because it is difficult to accurately model the reverse leakage current of the Schottky barrier diode.
  • the results are shown in FIG. 3 when the FLR width is 5 ⁇ m and the distance from the guard ring to the FLR is 2.5 ⁇ m.
  • the vertical axis in FIG. 3 is the avalanche breakdown voltage at room temperature of a pn diode in which one FLR having a width of 5 ⁇ m is provided 2.5 ⁇ m apart from the guard ring, and the horizontal axis is from the [000-1] direction to [ ⁇ 1 -120] direction ion implantation tilt angle and [000-1] direction to [11-20] direction ion implantation tilt angle.
  • the off-angle specification of a commercially available n-type 4H-SiC substrate is usually ⁇ 0.5 degrees, but as schematically shown in FIG. 4, the n-type 4H-SiC with a large substrate diameter up to 6 inches is used.
  • the substrate 10 has a large warp on its surface. For this reason, when the ion implantation tilt angle from the [000-1] direction to the [-1-120] direction is in the range of 0 ° or more and 4 ° or less, the effective variation in the off-angle increases.
  • the measured avalanche pressure resistance is considered to vary greatly.
  • the ion implantation tilt angle from the [000-1] direction to the [11-20] direction is not less than 0 degrees and not more than 4 degrees (in other words, the ion implantation from the [000-1] direction to the [-1-120] direction. Also in the case where the tilt angle is in the range of ⁇ 4 degrees or more and 0 degrees or less, the avalanche breakdown voltage decreases as the ion implantation tilt angle increases, and the avalanche breakdown voltage takes a value in the range of 900V to 200V.
  • the n-type 4H-SiC substrate having a substrate diameter of up to 6 inches has a large warp on the surface, so that the effective variation in the off angle increases, resulting in a measured avalanche breakdown voltage. Are considered to vary greatly.
  • the ion implantation tilt angle from the [000-1] direction to the [11-20] direction is not less than 4 degrees and not more than 12 degrees (in other words, the ion implantation from the [000-1] direction to the [-1-120] direction.
  • the avalanche breakdown voltage is as low as 200 V, but the value hardly depends on the ion implantation tilt angle.
  • n-type 4H—SiC in the actual measurement of the Schottky barrier diode shown in FIG. 2 in which the ion implantation tilt angle from the [000-1] direction to the [11-20] direction is set to 8 degrees. This means that the avalanche breakdown voltage does not vary even if the effective variation of the off angle due to the warpage of the substrate surface is ⁇ 4 degrees at the maximum. With this effect, as described above, it is considered that a uniform withstand voltage was obtained in an n-type 4H—SiC substrate having a substrate diameter of 6 inches.
  • the absolute value of the avalanche breakdown voltage can be increased by increasing the number of FLRs, a low avalanche breakdown voltage of 200 V when there is one FLR is not a practical obstacle. That is, by increasing the number of FLRs, it is possible to increase the breakdown voltage of the Schottky barrier diode.
  • FIG. 5 and FIG. 6 show a case where Al is ion-implanted from various directions into an n-type 4H—SiC substrate 10 whose surface is turned off by 4 degrees from the (0001) plane to the [11-20] direction using Monte Carlo simulation.
  • This is a result of obtaining the metallurgical boundary (the boundary (pn junction surface) between the n-type 4H—SiC substrate 10 and the FLR 40) of the FLR 40 in the case.
  • the donor density in the n-type 4H—SiC substrate 10 is 3 ⁇ 10 15 cm ⁇ 3
  • the range of Al ion implantation energy is 30 keV to 150 keV
  • the total amount of Al ion implantation is 2 ⁇ 10 14 cm ⁇ 2 .
  • the cross-sectional shape of the ion implantation mask 50 is such that its side surface has an inclination of 86 degrees with respect to the surface of the n-type 4H—SiC substrate 10.
  • FIG. 5 (a) shows the simulation result when Al ions are implanted in the [000-1] direction.
  • a certain proportion of Al ions penetrates through the gaps of the lattice and penetrates deep into the crystal (channeling), and the depth of the metallurgical boundary of FLR 40 reaches 1.58 ⁇ m.
  • the horizontal extent of the metallurgical boundary of the FLR 40 is substantially symmetric in the [11-20] direction and the [ ⁇ 1-120] direction, and the metallurgical engineering of the FLR 40 on the surface of the n-type 4H—SiC substrate 10.
  • the horizontal extent of the boundary is equal to 0.27 ⁇ m in both directions from the end of the ion implantation mask 50.
  • FIG. 5B shows a case where Al ions are implanted in a direction inclined by 4 degrees from the [000-1] direction to the [-1-120] direction, that is, perpendicularly implanted on the surface of the n-type 4H—SiC substrate 10.
  • the simulation result is shown.
  • the channeling seen in FIG. 5 (a) is suppressed.
  • the horizontal expansion of the metallurgical boundary of FLR 40 on the surface of the n-type 4H—SiC substrate 10 is asymmetrical with the [ ⁇ 1-120] direction being 0.28 ⁇ m and the [11-20] direction being 0.17 ⁇ m. .
  • FIG. 5 (c) shows a simulation result when Al ions are implanted in the direction inclined by 8 degrees from the [000-1] direction to the [-1-120] direction.
  • the asymmetry of the horizontal extension of the metallurgical boundary of the FLR 40 on the surface of the n-type 4H—SiC substrate 10 is further expanded as compared with FIG.
  • the horizontal extent of the metallurgical boundary of FLR 40 is 0.28 ⁇ m in the [ ⁇ 1-120] direction and 0.10 ⁇ m in the [11-20] direction.
  • directions in which Al ions are inclined from the [000-1] direction to the [11-20] direction by 4 degrees, 8 degrees, and 12 degrees. are respectively restored to the symmetry of the horizontal extension of the metallurgical boundary of the FLR 40 on the surface of the n-type 4H—SiC substrate 10, and the horizontal of the metallurgical boundary of the FLR 40 on the surface of the n-type 4H—SiC substrate 10 is restored.
  • the direction spread is 0.27 ⁇ m in both the [ ⁇ 1-120] direction and the [11-20] direction.
  • the symmetry of the horizontal extension of the metallurgical boundary of FLR 40 on the surface of the n-type 4H—SiC substrate 10 is that Al ions are [11-1] from the [000-1] direction. 20] direction disappears when implanted in a direction inclined 16 degrees, and the horizontal extension of the metallurgical boundary of FLR 40 on the surface of the n-type 4H—SiC substrate 10 is 0.31 ⁇ m in the [ ⁇ 1-120] direction, 11-20] direction is 0.05 ⁇ m.
  • the horizontal axis in FIG. 7 indicates that the horizontal extent of the metallurgy boundary of the FLR on the surface of the n-type 4H—SiC substrate whose surface is off by 4 degrees from the (0001) plane in the [11-20] direction is opposite to the off direction.
  • the ratio of the depth of the metallurgical boundary of the FLR to the horizontal extent of the metallurgical boundary of the FLR in the case of being approximately symmetric in direction.
  • a pn diode is realized by realizing an Al concentration distribution in which the ratio of the depth of the metallurgical boundary of the FLR to the horizontal extent of the metallurgical boundary of the FLR is 4.4 or less.
  • the variation in the avalanche breakdown voltage is reduced. That is, in the FLR, by realizing an Al concentration distribution in which the ratio of the depth of the metallurgical boundary of the FLR to the horizontal spread of the metallurgical boundary of the FLR is 4.4 or less, in the Schottky barrier diode, In addition, variations in breakdown voltage can be reduced.
  • FIG. 7 shows the result in the case of one FLR, but the same tendency is shown in the case of having a plurality of FLRs, except that the absolute value of the vertical axis increases.
  • the shape of the FLR is such that the horizontal spread of the metallurgical boundary of the FLR on the surface of the n-type 4H—SiC substrate is substantially symmetric in the off direction and the opposite direction, and the horizontal of the metallurgical boundary of the FLR.
  • the ratio of the depth of the metallurgical boundary of the FLR to the direction spread is characterized by being a predetermined value or less, and 4.4 or less in Example 1.
  • the shape of the FLR is the same as the surface of the n-type 4H—SiC substrate at the horizontally expanded end (the end of the FLR) of the metallurgical boundary of the FLR on the surface of the n-type 4H—SiC substrate in the direction opposite to the off direction. It is characterized in that the angle formed by the metallurgical boundary of FLR is less than 90 degrees.
  • This withstand voltage variation is, for example, the direction inclined from the [000-1] direction to the [-1-120] direction in the range of 0 degree to 4 degrees, or the [000-1] direction, as exemplified in FIG.
  • the variation of the avalanche breakdown voltage observed when Al ions are implanted in the direction inclined from 0 ° to [11-20] in the range of 0 ° to 4 ° is shown. In this case, it is desirable to implant Al ions in the [000-1] direction in order to achieve the maximum breakdown voltage.
  • Al ions should be implanted deep into the n-type 4H—SiC substrate by channeling, and the depth of the FLR (metallurgical region) accompanying the implantation of Al ions should be 1 ⁇ m or more. . This is based on a simulation result shown in FIG.
  • FIG. 8 shows the avalanche breakdown voltage at room temperature of the pn diode formed on the n-type 4H—SiC substrate whose surface is turned off by 4 degrees from the (0001) plane in the [11-20] direction, and the depth of the FLR (metallurgical region). It is a graph explaining the relationship.
  • the vertical axis of FIG. 8 is the avalanche breakdown voltage at room temperature of a pn diode in which one FLR having a width of 5 ⁇ m is provided 2.5 ⁇ m apart from the guard ring, and the horizontal axis is the n-type of FLR (metallurgical region). This is the depth from the surface of the 4H—SiC substrate.
  • the avalanche breakdown voltage in the case where the maximum value of the implantation energy is four types of 35 keV, 65 keV, 95 keV and 145 keV is simulated, and the avalanche breakdown voltage obtained at other energy is obtained using the avalanche breakdown voltage obtained at 95 keV. Is standardized.
  • the maximum avalanche breakdown voltage is obtained when the maximum value of the implantation energy is 145 keV, but the avalanche breakdown voltage decreases as the maximum value of the implantation energy decreases.
  • the maximum value of the implantation energy at which the depth of the FLR (metallurgical region) is less than 1 ⁇ m is 35 keV and 65 keV, the avalanche breakdown voltage decreases rapidly.
  • the FLR (metallurgical region) depth is about 1.0 ⁇ m, 80% or more of the avalanche breakdown voltage when the maximum value of the implantation energy is 145 keV is obtained.
  • Al ions are implanted in the [000-1] direction, which is a direction perpendicular to the crystal main surface, and Al ions are n-type 4H—SiC by channeling. It is considered that the depth of the FLR (metallurgical region) should be 1 ⁇ m or more by implanting deep into the substrate.
  • Al ions may deviate from the [000-1] direction due to manufacturing variations such as variations in tilt angle of ion implantation or variations in shape of the ion implantation mask.
  • Al ions can be implanted in a direction inclined from the [000-1] direction to the [11-20] direction. preferable. This is because, even when Al ions are implanted in a direction inclined from the [000-1] direction to the [11-20] direction, the above-mentioned “(1). Improving the uniformity of the breakdown voltage of the Schottky barrier diode” is described. This is because a uniform withstand voltage can be obtained as described in FIG.
  • Al ions may be implanted in a direction inclined from the [000-1] direction to the [-1-120] direction.
  • the horizontal spread of the FLR metallurgical boundary on the surface of the n-type 4H—SiC substrate is increased.
  • Asymmetry occurs between the off direction and the opposite direction (see FIGS. 5B and 5C), and it is difficult to obtain a uniform breakdown voltage. Therefore, when Al ions are implanted in the direction inclined from the [000-1] direction to the [-1-120] direction, the inclination angle inclined from the [000-1] direction to the [-1-120] direction is 4 Make it smaller than degree.
  • Al ions are 4 degrees or more from the [000-1] direction to the [11-20] direction, 12 degrees or more.
  • the FLR is formed by injecting in an inclined direction within a range of less than or equal to degrees. Thereby, it is possible to reduce variations in the breakdown voltage of the Schottky barrier diode.
  • the horizontal spread of the FLR metallurgical boundary on the surface of the n-type 4H—SiC substrate is made substantially symmetric in the off direction and the opposite direction, and the FLR with respect to the horizontal spread of the metallurgical boundary of the FLR
  • the depth ratio of the metallurgical boundary is set to a predetermined value or less, and 4.4 or less in Example 1.
  • the angle formed by the boundary is less than 90 degrees. In this case, the high breakdown voltage of the Schottky barrier diode can be realized by increasing the number of FLRs.
  • Al ions are [000] to the n-type 4H—SiC substrate whose surface is turned off by 4 degrees from the (0001) plane in the [11-20] direction. -1] direction to [11-20] direction 0 degree or more, or [000-1] direction [1-1-120] direction 0 degree or more and less than 4 degrees, injecting in a direction inclined to form FLR To do.
  • variations in the breakdown voltage of the Schottky barrier diode can be reduced, and a high breakdown voltage can be obtained.
  • a high breakdown voltage of the Schottky barrier diode can be realized even if the number of FLRs is small, so that the semiconductor chip can be miniaturized, and the number of chips obtained from a large-diameter 4H-SiC substrate increases. As a result, the chip cost is reduced.
  • Example 1 it is possible to realize a silicon carbide semiconductor device having excellent breakdown voltage characteristics.
  • FIG. 9 is a principal plan view showing an example of a semiconductor device having a Schottky barrier diode formed on an n-type 4H—SiC substrate according to the first embodiment.
  • FIG. 10 is a fragmentary cross-sectional view showing an example of a semiconductor device having a Schottky barrier diode formed on an n-type 4H—SiC substrate according to Example 1 (major portion along the line AA ′ in FIG. 9).
  • FIG. 10 is a fragmentary cross-sectional view showing an example of a semiconductor device having a Schottky barrier diode formed on an n-type 4H—SiC substrate according to Example 1 (major portion along the line AA ′ in FIG. 9).
  • the semiconductor device is composed of a Schottky barrier diode and a guard ring and FLR formed around the Schottky barrier diode, and is formed in one semiconductor chip.
  • the semiconductor chip 101 has an n + type 4H ⁇ whose surface is inclined at an off angle of 4 degrees in the [11-20] direction from the (0001) plane of the crystal main surface.
  • An n ⁇ -type 4H—SiC epitaxial layer 103 is formed on the surface of the SiC substrate 102.
  • the epitaxial layer 103 functions as an n ⁇ type drift layer.
  • the impurity concentration of the n + -type 4H—SiC substrate 102 is, for example, about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the impurity concentration of the epitaxial layer 103 is lower than the impurity concentration of the n + -type 4H—SiC substrate 102, for example, about 1 ⁇ 10 15 to 4 ⁇ 10 16 cm ⁇ 3 . Further, the thickness of the epitaxial layer 103 is, for example, about 3 to 80 ⁇ m.
  • the semiconductor chip 101 has a quadrangular shape of 6 mm ⁇ 6 mm, for example. In Example 1, the off angle is 4 degrees, but an n + type 4H—SiC substrate having another off angle may be used.
  • a central region on the upper surface of the epitaxial layer 103 is an active region, and a guard ring 109 which is a p-type annular semiconductor region is formed around the active region. Further, a plurality of FLRs 107a, 107b, and 107c, which are p-type annular semiconductor regions, are formed on the upper surface of the epitaxial layer 103 so as to surround the guard ring 109.
  • the guard ring 109 and the FLR 107a are formed with an interval 104
  • the FLR 107a and the FLR 107b are formed with an interval 105
  • the FLR 107b and the FLR 107c are formed with an interval 106.
  • the p-type impurity of the guard ring 109 and the FLRs 107a, 107b, and 107c is, for example, Al.
  • the width of the FLRs 107a, 107b, and 107c is, for example, about 5 ⁇ m.
  • the depth of the FLRs 107a, 107b, and 107c from the upper surface of the epitaxial layer 103 is, for example, about 0.8 to 1.2 ⁇ m.
  • the impurity concentration of the guard ring 109 and the FLRs 107a, 107b, and 107c is, for example, 6 ⁇ 10 17 cm ⁇ 3 .
  • the impurity concentration of the guard ring 109 can be higher than the impurity concentration of the FLRs 107a, 107b, and 107c, and can be set to 2 ⁇ 10 19 cm ⁇ 3 , for example.
  • the shapes of the guard ring 109 and the FLRs 107a, 107b, and 107c are, for example, metallurgical boundaries on the upper surface of the epitaxial layer 103 (boundaries between the epitaxial layer 103 and the guard ring 109 or FLRs 107a, 107b, and 107c (pn junction surfaces)).
  • the guard ring 109 and the FLRs 107a, 107b, and 107c have, for example, an Al concentration distribution shown in 6 (a), (b), or (c).
  • FIGS. 9 and 10 schematically show the positional relationship between the guard ring 109 and the FLRs 107a, 107b, and 107c in an easy-to-understand manner.
  • the anode electrode 111 is a Schottky electrode that is in Schottky junction with the upper surface of the epitaxial layer 103 in the active region that is the central region. Further, the end portion of the electrode of the anode electrode 111 is located on the guard ring 109.
  • a cathode electrode 110 is electrically connected to the back surface of the n + -type 4H—SiC substrate 102. As described above, a Schottky barrier diode is formed in the semiconductor chip 101.
  • an interlayer insulating film is formed on the semiconductor chip 101 in order to protect the upper surface of the epitaxial layer 103.
  • the interlayer insulating film is provided with an opening for exposing the anode electrode 111.
  • the AA ′ line shown in FIG. 9 is along a direction substantially orthogonal to the [1-100] direction of the n + -type 4H—SiC substrate 102.
  • the “A” side in FIG. 9 corresponds to the [ ⁇ 1 ⁇ 120] direction of the n + -type 4H—SiC substrate 102
  • “A ′” in FIG. The side corresponds to the [11-20] direction of the n + -type 4H—SiC substrate 102. That is, the A ′ direction corresponds to the off direction with the active region as the center.
  • the substantially orthogonal and approximately parallel degrees refer to the degree of accuracy with respect to the crystal orientation of wafer dicing.
  • the shapes of the FLRs 107a, 107b, and 107c are opposite to the [11-20] direction in which the horizontal spread of the metallurgical boundary on the upper surface of the epitaxial layer 103 is the off direction [- Although the ratio of the depth of the metallurgical boundary to the horizontal expansion of the metallurgical boundary is set to 4.4 or less, it is not limited to this.
  • the shape of the FLRs 107a, 107b, and 107c is changed to the [11-20] direction in which the horizontal spread of the metallurgical boundary on the upper surface of the epitaxial layer 103 is the off direction. It may be substantially symmetric with the [ ⁇ 1-120] direction, which is the opposite direction, and the depth of the metallurgical region may be 1 ⁇ m or more.
  • the FLRs 107a, 107b, and 107c have the Al concentration distribution shown in FIG.
  • FIG. 11 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment.
  • 11 to 17 are cross-sectional views of main parts of the semiconductor device during the manufacturing process according to the first embodiment.
  • an n + type 4H—SiC substrate 102 whose surface is inclined from the (0001) plane of the crystal main surface in the [11-20] direction at an off angle of 4 degrees is prepared.
  • the n-type impurity of the n + -type 4H—SiC substrate 102 is, for example, nitrogen.
  • the impurity concentration of the n + -type 4H—SiC substrate 102 is, for example, about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
  • n + -type 4H-SiC on a surface of the substrate 102 n - is formed by epitaxial growth type 4H-SiC epitaxial layer 103 - n which functions as type drift layer.
  • the n-type impurity of the epitaxial layer 103 is, for example, nitrogen.
  • the impurity concentration of the epitaxial layer 103 is lower than that of the n + -type 4H—SiC substrate 102 and is, for example, about 1 ⁇ 10 15 to 4 ⁇ 10 16 cm ⁇ 3 .
  • the thickness of the epitaxial layer 103 is, for example, about 3 to 80 ⁇ m.
  • Each condition of the above epitaxial layer 103 is set according to a required breakdown voltage.
  • a mask material layer 112a is formed on the upper surface of the epitaxial layer 103, and the mask material layer 112a is patterned by a lithography technique. Then, an n-type impurity is ion-implanted into the upper surface of the outer peripheral portion of the epitaxial layer 103 exposed from the mask material layer 112 a, thereby forming a channel stopper 108 on the upper surface of the epitaxial layer 103.
  • the implantation angle may be arbitrary, for example, perpendicular incidence to the surface of the epitaxial layer 103.
  • the n-type impurity of the channel stopper 108 is, for example, nitrogen.
  • the impurity concentration of the channel stopper 108 is, for example, 8 ⁇ 10 19 cm ⁇ 3 , and the ion implantation depth is, for example, 0.2 ⁇ m.
  • a mask material layer 112b made of, for example, silicon oxide is formed on the upper surface of the epitaxial layer 103, and the mask material layer 112b is patterned by a lithography technique. . Then, p-type impurities are obliquely ion-implanted into the upper surface of the epitaxial layer 103 exposed from the mask material layer 112b, thereby forming FLRs 107a, 107b, and 107c on the upper surface of the epitaxial layer 103.
  • the injection angle is set to an angle of 4 degrees or more and 12 degrees or less from the [000-1] direction to the [11-20] direction.
  • the p-type impurity of the FLRs 107a, 107b, and 107c is, for example, Al.
  • the impurity concentration of the FLRs 107a, 107b, and 107c is, for example, 6 ⁇ 10 17 cm ⁇ 3 , and the ion implantation depth is, for example, about 0.8 to 1.2 ⁇ m.
  • a mask material layer 112c made of, for example, silicon oxide is formed on the upper surface of the epitaxial layer 103, and the mask material layer 112c is patterned by a lithography technique. .
  • a guard ring 109 is formed on the upper surface of the epitaxial layer 103 by obliquely implanting p-type impurities into the upper surface of the epitaxial layer 103 exposed from the mask material layer 112c.
  • the injection angle is an angle inclined from 4 ° to 12 ° from the [000-1] direction to the [11-20] direction.
  • the p-type impurity of the guard ring 109 is, for example, Al.
  • the impurity concentration of the guard ring 109 is 2 ⁇ 10 19 cm ⁇ 3 , for example, and the ion implantation depth is, for example, about 0.8 to 1.2 ⁇ m.
  • annealing is performed to activate the implanted impurities.
  • illustration of a protective film covering the front and back surfaces during annealing is omitted.
  • an anode electrode 111 is formed on the upper surface of the epitaxial layer 103 so as to be in contact with the guard ring 109, for example, by sputtering. Further, the cathode electrode 110 is formed on the back surface of the n + -type 4H—SiC substrate 102 by, for example, a sputtering method. Subsequently, an interlayer insulating film (not shown) is formed on the upper surface of the epitaxial layer 103 so that the upper surface of the anode electrode 111 is exposed. As described above, the semiconductor device having the Schottky barrier diode formed on the n-type 4H—SiC substrate according to Example 1 is substantially completed.
  • the implantation angle is inclined by 4 degrees or more and 12 degrees or less from the [000-1] direction to the [11-20] direction.
  • the present invention is not limited to this.
  • the FLRs 107a, 107b, and 107c may be formed by implanting Al ions in a direction inclined by 0 degree or more and less than 4 degrees from the [000-1] direction to the [-1-120] direction. Good.
  • the Schottky barrier diode formed on the n-type 4H—SiC substrate has been described.
  • the present invention is not limited to this, and other carbonization formed on the n-type 4H—SiC substrate.
  • the present invention can also be applied to a silicon semiconductor device.
  • FIG. 18 is a cross-sectional view of an essential part showing an example of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (hereinafter referred to as SiC-MOSFET) formed on an n-type 4H—SiC substrate constituting a switching element. A large number of MOSFETs are connected in parallel to form one switching element. A plurality of FLRs are provided around the SiC-MOSFET according to the second embodiment. 18 is a cross-sectional view of the n + -type 4H—SiC substrate 102 in a direction substantially perpendicular to the [1-100] direction, similar to the cross section taken along the line AA ′ of FIG.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the semiconductor chip 101a has an n + type 4H—SiC substrate 102 whose surface is inclined from the (0001) plane of the crystal main surface in the [11-20] direction at an off angle of 4 degrees.
  • An n ⁇ type 4H—SiC epitaxial layer 103 is formed on the surface.
  • the thickness of the epitaxial layer 103 is, for example, about 5 to 40 ⁇ m.
  • the epitaxial layer 103 functions as an n ⁇ type drift layer that plays a role of securing a breakdown voltage.
  • a p-type body layer 1604 having a predetermined depth from the upper surface of the epitaxial layer 103 is formed in the epitaxial layer 103. Further, in the p-type body layer 1604, an n + -type source layer 1603 having a predetermined depth from the upper surface of the epitaxial layer 103 and spaced from the end of the p-type body layer 1604 is formed. Yes.
  • the n + -type source layer 1603 has a predetermined distance from the upper surface of the epitaxial layer 103 in the p-type body layer 1604 between the end of the p-type body layer 1604 and the n + -type source layer 1603.
  • the n ⁇ type drift layer is connected through a channel formed in this manner.
  • a gate insulating film 1606 is formed on the p-type body layer 1604 in which a channel between the end of the p-type body layer 1604 and the n + -type source layer 1603 is formed.
  • a gate electrode 1607 is formed.
  • a source electrode 1601 that is electrically connected to part of the surface of the n + -type source layer 1603 is formed, and a drain electrode 1602 is electrically connected to the back surface of the n + -type 4H—SiC substrate 102.
  • the SiC-MOSFET is formed in the central region of the semiconductor chip 101a.
  • a plurality of FLRs 107a, 107b, 107c which are p-type annular semiconductor regions, are spaced apart from each other on the upper surface of the epitaxial layer 103 so as to surround the active region where the SiC-MOSFET is formed. Is formed.
  • the p-type body layer 1604 located on the outermost side of the active region and the FLR 107a are formed with an interval 104
  • the FLR 107a and the FLR 107b are formed with an interval 105
  • the FLR 107b and the FLR 107c have an interval 106. It is formed apart.
  • a channel stopper 108 which is an n + type semiconductor region is provided on the upper surface of the epitaxial layer 103 outside the FLRs 107a, 107b and 107c.
  • An interlayer insulating film (not shown) is provided on the FLRs 107a, 107b, and 107c.
  • Al ions are applied to the n-type 4H-SiC substrate whose surface is turned off by 4 degrees from the (0001) plane in the [11-20] direction.
  • the FLR is formed by injecting from the [000-1] direction to the [11-20] direction in an inclined direction in the range of 4 degrees to 12 degrees.
  • Al ions are [000] to the n-type 4H—SiC substrate whose surface is turned off by 4 degrees from the (0001) plane in the [11-20] direction.
  • an example of a SiC-MOSFET is shown, but in addition to this, an FLR similar to that of the second embodiment may be formed in a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a junction FET. .
  • a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a junction FET.
  • FIG. 19 is a circuit diagram illustrating an example of a power converter (inverter) in which the 4H—SiC Schottky barrier diode according to the first embodiment is connected to a switching element as a free wheel diode.
  • the inverter according to the third embodiment includes a control circuit 1701 and a power module 1702.
  • the control circuit 1701 and the power module 1702 are connected by terminals 1703 and 1704.
  • the power module 1702 is connected to the power supply potential (Vcc) via a terminal 1705 and to the ground potential (GND) via a terminal 1706.
  • the output of the power module 1702 is connected to a three-phase motor 1710 via terminals 1707, 1708 and 1709.
  • an IGBT 1711 is mounted as a switching element. Further, a semiconductor chip having a 4H—SiC Schottky barrier diode according to the first embodiment is mounted as a free-wheeling diode 1712 connected to each IGBT.
  • an IGBT 1711 and a freewheeling diode 1712 are connected in antiparallel between the power supply potential (Vcc) and the input potential of the three-phase motor 1710, and the input potential of the three-phase motor 1710 and the ground potential (GND).
  • the IGBT 1711 and the freewheeling diode 1712 are also connected in reverse parallel to each other. That is, two IGBTs 1711 and two free wheeling diodes 1712 are provided in each single phase of the three-phase motor 1710, and six IGBTs 1711 and six free wheeling diodes 1712 are provided in three phases.
  • a control circuit 1701 is connected to the gate electrode of each IGBT 1711, and the IGBT 1711 is controlled by the control circuit 1701. Therefore, the three-phase motor 1710 can be driven by controlling the current flowing through the IGBT 1711 of the power module 1702 by the control circuit 1701.
  • the semiconductor chip 101 according to the first embodiment has excellent withstand voltage uniformity as described above. Therefore, the number of chips obtained from a large-diameter wafer such as 6 inches increases, and the chip cost is reduced. As a result, the power module 1702 is reduced in cost. Can be Therefore, the power module 1702 and the inverter according to the third embodiment, and further, the three-phase motor system including the three-phase motor 1710 in the inverter according to the third embodiment can be manufactured at low cost.
  • the IGBT is used as the switching element.
  • the SiC-MOSFET according to the second embodiment can be used instead of the IGBT.
  • the switching element is also a SiC element, it is possible to operate at a higher temperature and to realize a high current density.
  • the SiC-MOSFET according to Example 2 has excellent withstand voltage uniformity as described above, the number of chips obtained from a large-diameter wafer of 6 inches or the like is increased, and the chip cost is reduced.
  • the cost of the module 1702 can be reduced. Further, by performing synchronous rectification or the like, it is possible to omit the return diode and reduce the size and cost of the power module 1702.
  • FIG. 20 is a schematic diagram illustrating an example of a configuration of an electric vehicle according to the fourth embodiment
  • FIG. 21 is a circuit diagram illustrating an example of a boost converter according to the fourth embodiment.
  • the electric vehicle according to the fourth embodiment drives a three-phase motor 1803 and a three-phase motor 1803 that allow power to be input / output to / from a drive shaft 1802 to which the drive wheels 1801a and 1801b are connected.
  • An inverter 1804 and a battery 1805 are provided.
  • the electric vehicle according to the fourth embodiment includes a boost converter 1808, a relay 1809, and an electronic control unit 1810.
  • the boost converter 1808 includes a power line 1806 to which an inverter 1804 is connected and power to which a battery 1805 is connected. It is connected to the line 1807.
  • the three-phase motor 1803 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil.
  • the inverter 1804 the inverter according to the third embodiment is used.
  • the boost converter 1808 has a configuration in which a reactor 1911 and a smoothing capacitor 1912 are connected to an inverter 1913.
  • the inverter 1913 is the same as the inverter described in the third embodiment, and the configuration of the switching element 1914 and the diode 1915 in the inverter is the same as that described in the third embodiment.
  • the electronic control unit 1810 includes a microprocessor, a storage device, and an input / output port, and receives a signal from a sensor that detects the rotor position of the three-phase motor 1803, a charge / discharge value of the battery 1805, and the like. Then, a signal for controlling inverter 1804, boost converter 1808, and relay 1809 is output.
  • Example 4 an automobile having a low-cost power conversion device can be realized by a semiconductor device having excellent breakdown voltage characteristics.
  • the electric vehicle has been described in the fourth embodiment, the three-phase motor system according to the third embodiment can be similarly applied to a hybrid vehicle that also uses an engine.
  • the three-phase motor system according to the third embodiment can be used for a railway vehicle.
  • a railway vehicle using the three-phase motor system according to the third embodiment will be described with reference to FIG.
  • a railway vehicle having a low-cost power conversion device can be realized by a semiconductor device having excellent withstand voltage characteristics.
  • FIG. 22 is a circuit diagram illustrating an example of a converter and an inverter provided in the railway vehicle according to the fifth embodiment.
  • electric power is supplied from the overhead line OW (for example, 25 kV) to the railway vehicle according to the fifth embodiment via the panda graph PG.
  • the voltage is stepped down to 1.5 kV through the transformer 2009, and the converter 2007 converts alternating current into direct current.
  • the inverter 2002 converts the direct current input via the capacitor 2008 into alternating current, and drives the wheel WH with a three-phase motor that is the load 2001.
  • the configuration of the switching element 2004 and the diode 2005 in the converter 2007 and the configuration of the switching element 2004 and the diode 2005 in the inverter 2002 are the configurations described in the third embodiment.
  • the control circuit 1701 described in the third embodiment is omitted.
  • the symbol RT indicates a line.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur au carbure de silicium possédant d'excellentes caractéristiques de tension de tenue. Dans un mode de réalisation de la présente invention, des ions Al sont injectés dans un substrat 4H-SiC du type n, ayant une surface qui est décalée de 4 degrés par rapport au plan (0001) dans la direction [11-20], dans une direction inclinée d'au moins 0 degrés de la direction [000-1] vers la direction [11-20] ou d'au moins 0 degrés et de moins de 4 degrés de la direction [000-1] vers la direction [-1-120], formant un FLR au niveau d'une couche épitaxiale du 4H-SiC formé au niveau de la surface du substrat 4H-SiC du type n. Dans la forme du FLR, au niveau de l'extrémité dans le sens opposé au sens d'inclinaison du FLR au niveau de la surface supérieure de la couche épitaxiale, l'angle formé par la surface supérieure de la couche épitaxiale et la limite métallurgique du FLR est inférieur à 90 degrés.
PCT/JP2014/067841 2014-07-03 2014-07-03 Dispositif à semi-conducteur, son procédé de fabrication, module de puissance et dispositif de conversion de puissance WO2016002058A1 (fr)

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JP7476915B2 (ja) 2020-09-17 2024-05-01 住友電気工業株式会社 六方晶化合物半導体の歪評価装置、および炭化珪素エピタキシャル基板の製造方法

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