Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/04026—Bonding areas specifically adapted for layer connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/05001—Internal layers
  • H01L2224/05099—Material
  • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/05155—Nickel [Ni] as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
  • H01L2224/05599—Material
  • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/05639—Silver [Ag] as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/27—Manufacturing methods
  • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
  • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
  • H01L2224/27418—Spray coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/27—Manufacturing methods
  • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
  • H01L2224/2746—Plating
  • H01L2224/27462—Electroplating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/27—Manufacturing methods
  • H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
  • H01L2224/27505—Sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
  • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
  • H01L2224/29001—Core members of the layer connector
  • H01L2224/2901—Shape
  • H01L2224/29011—Shape comprising apertures or cavities
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
  • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
  • H01L2224/29001—Core members of the layer connector
  • H01L2224/29075—Plural core members
  • H01L2224/2908—Plural core members being stacked
  • H01L2224/29082—Two-layer arrangements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
  • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
  • H01L2224/29001—Core members of the layer connector
  • H01L2224/29099—Material
  • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
  • H01L2224/29111—Tin [Sn] as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
  • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
  • H01L2224/29001—Core members of the layer connector
  • H01L2224/29099—Material
  • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/29139—Silver [Ag] as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/3201—Structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/325—Material
  • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
  • H01L2224/32507—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an intermetallic compound
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
  • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
  • H01L2224/7525—Means for applying energy, e.g. heating means
  • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8319—Arrangement of the layer connectors prior to mounting
  • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/832—Applying energy for connecting
  • H01L2224/83201—Compression bonding
  • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
  • H01L2224/83399—Material
  • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/83455—Nickel [Ni] as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/838—Bonding techniques
  • H01L2224/83801—Soldering or alloying
  • H01L2224/8381—Soldering or alloying involving forming an intermetallic compound at the bonding interface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/838—Bonding techniques
  • H01L2224/83801—Soldering or alloying
  • H01L2224/8382—Diffusion bonding
  • H01L2224/83825—Solid-liquid interdiffusion

Definitions

• the present invention generally relates to the permanent assembly of two elements by interdiffusion in the transient liquid phase. More particularly, the invention relates to the assembly of electronic structures composed by the vertical stack of at least two elements to be assembled.
• the transient liquid phase assembly process is known in the state of the art and is used for the assembly of electronic components, using the interdiffusion between silver in the solid state and the tin to the liquid state.
• the two parts to be assembled 1, 1 ' are each coated with a thin layer of silver (Ag) 2, 2', between which is placed a thin layer of tin ( Sn) 4 in the form of a solid strip typically having a thickness of the order of 5 ⁇ .
• the silver layers 2, 2 ' are made in a flat and compact form and typically have a thickness of the order of 15 ⁇ .
• a pressure of the order of 75 to 120 kilo-Pascal (kPa) is generally exerted on the stack of layers Ag / Sn / Ag and it is heated up to 300 ° C during a duration that can vary from a few minutes to several hours depending on the application. With the rise in temperature, the tin strip 4 melts and moistens the surfaces of the layers of silver 2, 2 '. A phenomenon of germination and intermetallic growth then occurs on sites of heterogeneous germination arising on microscopic size defects present on the surfaces of the silver layers 2, 2 '.
• FIGS. 1b and 1c This classic mechanism of germination and growth is represented in FIGS. 1b and 1c.
• the liquid tin 4 wets the surfaces of the silver layers 2, 2 'and, according to what is provided for by the binary phase diagram SnAg, a solid Ag 3 Sn intermetallic layer is formed, by isotropic growth. 6 intermetallic germs 5, which coexists with a tin-rich liquid phase 4 whose composition depends on temperature and whose melting point is that of eutectic Sn96.2% Ag3.8% which is substantially lower (221, 3 ° C) than that of pure tin (232 ° C).
• the Ag 3 Sn intermetallic phase increases by diffusion of silver, through the intermetallic, up to the interface with the liquid tin phase.
• the grains 6 of the intermetallic phase are therefore grown from the two silver layers 2, 2 '. These grains 6 preferentially grow equi-axially and perpendicularly to the Ag / Sn interface, this growth producing oriented grain boundaries 7 shown in FIG. It will be noted that the diffusion length of the silver through the intermetallic layer increases as and when the grains grow.
• the assembly of the two elements 1, 1 ' is carried out once all the tin-rich liquid phase has been consumed and replaced by the intermetallic grains.
• a disadvantage of this known assembly method is that at the end of the assembly the intermetallic seal consists of large elongated grains oriented perpendicularly to the junction plane. This type of crystalline structure is known to alter the mechanical properties of the intermetallic seal, with a lowering of the yield point and the breaking force. Furthermore, it would be desirable to reduce the duration of the assembly operation.
• the method according to the invention for assembling a first element and a second element by interdiffusion of a first metal and a second metal, the second metal having a substantially lower melting temperature than that of the first metal comprises the successive steps of depositing at least one layer of the first metal on first and second surfaces to join first and second members, respectively; sandwiching a layer of the second metal between the first and second surfaces to be bonded coated with the first metal; exerting pressure on the first and second elements so as to bring closer to the first and second surfaces to be assembled; and heating for a predetermined time the assembly thus formed with the first and second members so as to cause a melting of the second metal layer and a production by germination and growth of a first metal-second metal intermetallic layer ensuring assembly of the first and second elements.
• the lacunated silver layer allows a higher growth rate of the intermetallic grains and, correspondingly, a reduction in the duration of the assembly operation. . This results from a reduction of the exchange surface between silver and tin in the liquid state and a reduced diffusion length of silver to the liquid phase of the tin, through the intermetallic.
• the lacunary structure of the silver layer is at least partly porous and / or granular.
• the tin layer is a solid tin strip.
• the pressure applied to the first and second elements is between substantially 9 kPa and 55 kPa.
• the set of first and second elements is heated to a temperature between substantially 250 ° C and 350 ° C for a period of time substantially between 2 minutes and 15 minutes.
• the first element is a substrate comprising at least one trace of copper and the second element is an electronic chip to be assembled on the copper trace.
• the invention also relates to an assembly comprising first and second elements assembled by means of the assembly method as briefly described below.
• FIGS. 1a, 1b and 1c relate to the prior art and show, in the known transient liquid phase assembly process, a step before assembly of two elements, a step of germination of the intermetallic phase. and a step of growing the intermetallic grains, respectively;
• FIGS. 2a, 2b and 2c relate to the invention and show, in a particular embodiment of the assembly method according to the invention, a step before assembly of the two elements, a step of melting the second metal ( Sn) which enters the lacunary layer of the first metal (Ag), and an end-of-assembly step with the intermetallic seal formed between the two elements, respectively; and
• Figs.3a, 3b and 3c relate to the invention and show the process of creating the intermetallic seal in the particular embodiment of Figs.2a, 2b and 2c.
• the substrate 8 comprises a copper trace 8 'having for example here a thickness of 1 to 2 mm.
• the copper trace 8 ' is covered by a nickel layer 9 having for example here a thickness of the order of 4 ⁇ and obtained by electrolytic deposition.
• a silver layer 10, having a thickness of about 500 nm in this application, is then deposited on the nickel layer 9, for example by "flash" type deposition.
• the chip 1 1 is here a silicon chip having for example a thickness of about 200 ⁇ . Its surface to be assembled is coated with a nickel layer 12 having for example here a thickness of the order of 500 nm.
• a silver layer 13, similar to the silver layer 10, is then deposited on the nickel layer 12, for example by "flash" type deposit.
• a porous silver layer 14 having here a thickness of the order of 20 ⁇ is deposited on the silver layer 10 of the substrate 8.
• porous silver layer 14 may be used in the assembly method according to the invention, according to the embodiments thereof.
• the porous silver layer 14 is deposited by the so-called "cold spray” method, by projecting onto the surface of the silver layer 9 silver particles of which the diameter is between 2 ⁇ and 5 ⁇ .
• porous silver layer 14 may be used according to the embodiments of the process according to the invention, such as, for example, partial sintering of silver powder and powdery plasma deposition.
• the assembly comprising the substrate 8, 8 ', 9, 10, the porous silver layer 14 and the compact tin layer 15 is deposited on a heating plate 16.
• the electronic chip 1 1, 12, 13 is then sucked by a gripping tool 17 fixed on an actuator 18 and is deposited and held against the surface of the porous silver layer 14.
• the actuator 18 then exerts and maintains a controlled pressure on the entire structure, of the order 25 kPa in this embodiment of the method according to the invention. It will be noted that according to the applications this pressure can vary and will typically be between substantially 9 kPa and 55 kPa.
• the temperature of the heating plate 16 is increased here up to 300 ° C with a heating rate of the order of 60 ° C per second.
• this temperature may vary and will typically be between substantially 250 ° C. and 350 ° C.
• the melting temperature of the second metal in this case tin Sn
• the first metal here silver Ag
• the temperature of the heating plate 16 is maintained at 300 ° C for about 3 minutes, and then the plate is cooled.
• the pressure exerted by the actuator 18 is maintained until the temperature of the plate 16 passes below 200 ° C.
• the assembly of the electronic chip 1 1 on the substrate 8 then has the final structure shown in Fig.2b.
• the assembly method according to the invention makes it possible to create an Ag 3 Sn 19 intermetallic seal with a metallurgical continuity between the substrate 8 and the electronic chip 11 which is ensured by layers of NiAg binary alloy 20. These NiAg alloy layers 20 were formed from the layers 9, 10 and 12, 13.
• the intermetallic joint 19 has a large number of isotropic, unoriented and small sized grains which provide good elasticity and good tensile strength. These grains are typically of a size ranging from a few ⁇ to a few tens of ⁇ .
• a porous, lacunary or even granular metal layer here Ag
• this porosity of the silver layer 14 allows penetration of the tin-rich liquid phase at the heart of the silver layer, by infiltrating the channels created by the networks of gaps. of the silver layer.
• the porous layer has a very high density of micrometric structures constituting preferential sites for the heterogeneous germination of the intermetallic phase.
• the liquid tin 15 wets the intermetallic seeds 21.
• Silver 22 diffuses through the intermetallic phase to the interface with the liquid tin phase.
• the growth of the seed is isotropic and leads, as shown in Fig.3c, to the formation of an intermetallic seal formed of a large number of isotropic grains 23, undirected and small (a few ⁇ a few tens of ⁇ ).
• This intermetallic seal has a high yield strength and a high tensile strength.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Die Bonding (AREA)
• Pressure Welding/Diffusion-Bonding (AREA)
• Other Surface Treatments For Metallic Materials (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=51417450

Family Applications (1)

Country Status (4)

Families Citing this family (2)

Citations (3)

Family Cites Families (2)

• 2014
  • 2014-06-02 FR FR1454951A patent/FR3021670B1/fr active Active
• 2015
  • 2015-04-08 JP JP2016570808A patent/JP6636465B2/ja active Active
  • 2015-04-08 WO PCT/FR2015/050912 patent/WO2015185812A1/fr not_active Ceased
  • 2015-04-08 DE DE112015002600.2T patent/DE112015002600T5/de not_active Withdrawn

Patent Citations (3)

Also Published As

Similar Documents

Legal Events