WO2015180225A1 - 阵列基板、制作方法及液晶显示面板 - Google Patents

阵列基板、制作方法及液晶显示面板 Download PDF

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Publication number
WO2015180225A1
WO2015180225A1 PCT/CN2014/080794 CN2014080794W WO2015180225A1 WO 2015180225 A1 WO2015180225 A1 WO 2015180225A1 CN 2014080794 W CN2014080794 W CN 2014080794W WO 2015180225 A1 WO2015180225 A1 WO 2015180225A1
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Prior art keywords
layer
metal layer
array substrate
thickness
transparent electrode
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PCT/CN2014/080794
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English (en)
French (fr)
Inventor
徐向阳
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深圳市华星光电技术有限公司
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Priority to US14/386,721 priority Critical patent/US9625774B2/en
Publication of WO2015180225A1 publication Critical patent/WO2015180225A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method, and a liquid crystal display panel.
  • Thin film transistor liquid crystal display panels have been widely used in people's production and life as low-carbon green environment-friendly display devices. With the development of display technology, product quality and product cost have become the competitive power of manufacturing companies of liquid crystal display panels.
  • the number of driver chips in the panel is generally reduced as much as possible.
  • each driver chip can drive as many components as possible, so in large size
  • the design of the double metal trace is generally adopted to reduce the technical problem that the line resistance is too large due to the long trace length.
  • FIG. 1 is a schematic structural diagram of an array substrate of a conventional liquid crystal display panel.
  • 101 is a substrate
  • 102 is a first insulating layer
  • 103 is a second insulating layer
  • 104 is a first metal layer
  • 105 is a second metal layer
  • 106 is a pixel electrode layer, wherein 106 can also be used for Internally connected electrodes (such as connecting the first metal layer 104 and the second metal layer 105, etc.) or electrodes for external connection (such as connection to a driver chip, etc.).
  • the array substrate is divided into five parts according to the function of each part of the array substrate, wherein the A area is a thin film field effect transistor, the B area is a pixel electrode, and the C area is a jumper area (ie, the connection of two metal layers is realized)
  • the D area is a fan-out area of the trace, and the E area is a connection area connected to the drive chip.
  • the D region is routed through the first metal layer 104 and the second metal layer 105, which can well avoid the problem of excessive line resistance of the trace.
  • the second metal layer 105 is generally disposed on the non-planar film, that is, the lower portion of the second metal layer 105 tends to be uneven, which easily causes the second metal layer 105 to be broken, thereby causing the D-zone trace to fail to transmit signals normally. This defect is difficult to find in the fabrication process of the array substrate, which greatly affects the display quality of the liquid crystal display panel.
  • An object of the present invention is to provide an array substrate, a manufacturing method, and a liquid crystal display panel, which can solve the problem that the second metal layer as a trace in the existing array substrate is easily broken, thereby causing the display quality of the corresponding liquid crystal display panel to be degraded. problem.
  • An embodiment of the present invention provides an array substrate, including:
  • a first metal layer located on the substrate substrate, including a scan line and a gate region of the thin film field effect transistor;
  • a second metal layer on the semiconductor layer including a source region of the thin film field effect transistor, a drain region of the thin film field effect transistor, a data line, and a trace;
  • Transparent electrode layer including:
  • a pixel electrode for connecting to the drain region
  • a second insulating layer is disposed on the transparent electrode layer and the thin film field effect transistor.
  • the transparent electrode layer further includes:
  • An internal connection electrode is used to connect the first metal layer and the second metal layer.
  • the transparent electrode layer further includes:
  • An external connection electrode for connecting the first metal layer and the driving chip, and connecting the second metal layer and the driving chip.
  • the first metal layer has a thickness of 0.1 ⁇ m to 0.6 ⁇ m
  • the second metal layer has a thickness of 0.1 ⁇ m to 0.6 ⁇ m.
  • the first insulating layer has a thickness of 0.2 ⁇ m to 0.5 ⁇ m
  • the semiconductor layer has a thickness of 0.1 ⁇ m to 0.3 ⁇ m
  • the second insulating layer has a thickness of 0.2 ⁇ m to 0.5 micron.
  • the transparent electrode layer has a thickness of 0.01 ⁇ m to 0.1 ⁇ m.
  • the embodiment of the invention further provides a method for fabricating an array substrate, which comprises:
  • A forming a layered structure on the substrate substrate, the layered structure is a first metal layer
  • the step E further includes:
  • the internal connection electrode is used to connect the first metal layer and the second metal layer.
  • the step E further includes:
  • the external connection electrode is configured to connect the first metal layer and the driving chip, and connect the second metal layer and the driving chip.
  • the first metal layer has a thickness of 0.1 ⁇ m to 0.6 ⁇ m
  • the second metal layer has a thickness of 0.1 ⁇ m to 0.6 ⁇ m.
  • the first insulating layer has a thickness of 0.2 ⁇ m to 0.5 ⁇ m
  • the semiconductor layer has a thickness of 0.1 ⁇ m to 0.3 ⁇ m
  • the second insulating layer has a thickness of 0.2 microns to 0.5 microns.
  • the thickness of the transparent electrode layer is from 0.01 micrometers to 0.1 micrometers.
  • An embodiment of the present invention further provides a liquid crystal display panel including a film substrate, an array substrate, and a liquid crystal layer disposed between the color film substrate and the array substrate;
  • the array substrate comprises:
  • a first metal layer located on the substrate substrate, including a scan line and a gate region of the thin film field effect transistor;
  • a second metal layer on the semiconductor layer including a source region of the thin film field effect transistor, a drain region of the thin film field effect transistor, a data line, and a trace;
  • Transparent electrode layer including:
  • a pixel electrode for connecting to the drain region
  • a second insulating layer is disposed on the transparent electrode layer and the thin film field effect transistor.
  • the transparent electrode layer further includes:
  • An internal connection electrode is used to connect the first metal layer and the second metal layer.
  • the transparent electrode layer further includes:
  • An external connection electrode for connecting the first metal layer and the driving chip, and connecting the second metal layer and the driving chip.
  • the liquid crystal display panel of the present invention is a twisted nematic display panel or a vertical alignment type display panel.
  • the first metal layer has a thickness of 0.1 ⁇ m to 0.6 ⁇ m
  • the second metal layer has a thickness of 0.1 ⁇ m to 0.6 ⁇ m.
  • the first insulating layer has a thickness of 0.2 ⁇ m to 0.5 ⁇ m
  • the semiconductor layer has a thickness of 0.1 ⁇ m to 0.3 ⁇ m
  • the second insulating layer has a thickness of 0.2 ⁇ m. Up to 0.5 microns.
  • the transparent electrode layer has a thickness of 0.01 ⁇ m to 0.1 ⁇ m.
  • the manufacturing method, and the liquid crystal display panel are provided with a reinforcing portion on the trace through the transparent electrode layer, so that the trace on the second metal layer is further It is firm and not easy to break, thus ensuring the display quality of the corresponding liquid crystal display panel; solving the technical problem that the second metal layer as a trace in the existing array substrate is easily broken, thereby causing the display quality of the corresponding liquid crystal display panel to be degraded. .
  • FIG. 1 is a schematic structural view of an array substrate of a conventional liquid crystal display panel
  • FIG. 2 is a schematic structural view of a first preferred embodiment of an array substrate of a liquid crystal display panel of the present invention
  • FIG. 3 is a flow chart showing the fabrication of a first preferred embodiment of an array substrate of a liquid crystal display panel of the present invention
  • FIG. 4 is a schematic structural view of a second preferred embodiment of an array substrate of a liquid crystal display panel of the present invention.
  • FIG. 2 is a schematic structural view of a first preferred embodiment of an array substrate of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel of the preferred embodiment is a twisted nematic display panel (Twisted Nematic)
  • the array substrate 20 of the liquid crystal display panel includes a substrate substrate 201, a first metal layer 202, a first insulating layer 203, a semiconductor layer 204, a second metal layer, a transparent electrode layer, and a second insulating layer 207.
  • the first metal layer 202 is located on the substrate substrate 201, including the scan line and the gate region of the thin film field effect transistor; the first insulating layer 203 is partially located on the first metal layer 202; the semiconductor layer 204 is located on the first insulating layer 203; The second metal layer is located on the semiconductor layer 204, including the source region 2051 of the thin film field effect transistor, the drain region 2052 of the thin film field effect transistor (not shown) and the trace 2053; and the transparent electrode layer includes The pixel electrode 2061 connected to the drain region 2052 of the thin film field effect transistor and the reinforcing portion 2062 overlying the trace 2053; the second insulating layer 207 is located on the transparent electrode layer and the thin film field effect transistor.
  • the transparent electrode layer 206 further includes an internal connection electrode 2063 and an external connection electrode 2064.
  • the internal connection electrode 2063 is used to connect the first metal layer 202 and the second metal layer 205.
  • the external connection electrode 2064 is used to connect the first metal layer 202 and the drive. The chip and the second metal layer 205 and the driving chip are connected.
  • the size of the area division of the array substrate in FIG. 2 is not the actual size of the area in the array substrate.
  • the A region of the array substrate 20 includes a thin film field effect transistor
  • the B region of the array substrate includes a pixel electrode 2061 formed by a transparent electrode layer
  • the C region of the array substrate includes an internal connection electrode 2063 formed by a transparent electrode layer
  • the D region of the array substrate includes A trace 2053 formed by the second metal layer and a reinforcing portion 2062 formed by the transparent electrode layer
  • the E region of the array substrate includes an external connection electrode 2064 formed of a transparent electrode layer.
  • the thin film field effect transistor of the A region of the array substrate 20 is similar in structure to the thin film field effect transistor of the A region of FIG. 1, and the working principle is the same.
  • the pixel electrode 2061 of the B region of the array substrate 20 is different from the pixel electrode of the B region of FIG. 1 in that the pixel electrode 2061 in the preferred embodiment is disposed under the second insulating layer 207, but the second insulating layer 207 is generally The transparent silicon nitride film does not affect the normal function of the pixel electrode 2061. Therefore, the working principle of the pixel electrode 2061 of the B region in the preferred embodiment is also the same as that of the pixel electrode of the B region of FIG.
  • the internal connection electrode 2063 of the C region of the array substrate is different from the jumper region of the C region in FIG. 1 in that the internal connection electrode 2063 in the preferred embodiment is disposed under the second insulating layer 207, but also due to the second insulating layer. 207 is a transparent silicon nitride film, which does not affect the normal function of the internal connection electrode 2063. Therefore, in the preferred embodiment, the internal connection electrode 2063 of the C region works also with the jumper region of the C region of FIG. It works the same way.
  • the difference between the trace 2053 of the D area of the array substrate and the fan-out area of the trace of the D area in FIG. 1 is that the trace 2053 in the preferred embodiment is covered with the reinforcement portion 2062 formed by the transparent electrode layer, such that the reinforcement portion 2062 can enhance the stability of the trace 2053 on the second metal layer, so that the trace 2053 on the second metal layer is not easily broken, and since the reinforcement portion 2062 is also made of a conductive material, the conductivity of the trace 2053 can be further enhanced.
  • the specific working principle of the trace 2053 of the D area is the same as that of the trace of the D area of FIG.
  • the external connection electrode 2064 of the E region of the array substrate can well realize the connection of the driving chip to the first metal layer 202 and the second metal layer, respectively, and thus also has the same function and working principle as the E region in FIG.
  • FIG. 3 is a flow chart showing the fabrication of a first preferred embodiment of an array substrate of a liquid crystal display panel of the present invention.
  • the manufacturing method of the array substrate comprises:
  • Step S301 forming a layered structure on the substrate substrate, the layered structure being a first metal layer.
  • the first metal layer may be formed on the substrate substrate by a thickness of 0.1 ⁇ m to 0.6 ⁇ m, and the material of the metal layer may be chromium, molybdenum, aluminum or copper. Then it proceeds to step S302.
  • Step S302 performing image processing on the layered structure to form a scan line and a gate region of the thin film field effect transistor.
  • the first metal layer may be wet-etched by a photomask process to form a scan line and a gate region of the thin film field effect transistor. Then it proceeds to step S303.
  • Step S303 sequentially forming a first insulating layer, a semiconductor layer, and a second metal layer on the layered structure.
  • the first insulating layer such as a silicon nitride layer
  • the semiconductor layer such as an amorphous silicon layer
  • a second metal layer is formed from 0.1 micron to 0.6 micron. Then it proceeds to step S304.
  • Step S304 patterning the layered structure to form a source region of the thin film field effect transistor, a drain region of the thin film field effect transistor, a data line, and a trace. Specifically: using a gray scale mask process (gray Tone) patterning the above-described layered structure, wet etching the second metal layer, dry etching the semiconductor layer, and drying the first insulating layer in the C and E regions of the array substrate Etching forms a via connected to the first metal layer.
  • gray scale mask process gray Tone
  • the second metal layer is wet etched, and the semiconductor layer is dry etched to form a pixel electrode region.
  • the second metal layer is wet etched, and the semiconductor layer is dry etched to form a source region of the thin film field effect transistor, a drain region and a source region of the thin film field effect transistor, and The channel between the drain regions also forms the data line of the liquid crystal display panel.
  • the second metal layer is wet etched, and the semiconductor layer is dry etched to form a trace of the liquid crystal display panel. Then it proceeds to step S305.
  • Step S305 forming a transparent electrode layer on the layered structure, and patterning the layered structure to form a pixel electrode and a reinforcing portion covering the trace.
  • a transparent electrode layer such as indium tin oxide or indium zinc oxide
  • the layered structure is patterned by a photomask process to form a pixel electrode in the B region of the array substrate, and an internal connection electrode (through a via hole located in the C region) is formed in the C region of the array substrate, in the D region of the array substrate.
  • a reinforcing portion covering the trace is formed, and an external connection electrode (through a via located in the E region) is formed in the E region of the array substrate. Then it proceeds to step S306.
  • Step S306 forming a second insulating layer on the layered structure, and patterning the layered structure to cover the transparent electrode layer and the thin film field effect transistor.
  • the second insulating layer can be formed on the layered structure with a thickness of 0.2 micrometers to 0.5 micrometers.
  • the layered structure is patterned by a photomask process to cover and protect the transparent electrode layer and the thin film field effect transistor.
  • the array substrate, the manufacturing method and the liquid crystal display panel of the preferred embodiment are provided with a reinforcing portion on the trace through the transparent electrode layer, so that the traces on the ground metal layer are more firm and not easily broken, thereby ensuring the corresponding liquid crystal display panel. Display quality.
  • FIG. 4 is a schematic structural view of a second preferred embodiment of an array substrate of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel of the preferred embodiment is a vertical alignment type display panel (Vertical
  • the array substrate 40 of the liquid crystal display panel includes a substrate substrate 401, a first metal layer 402, a first insulating layer 403, a semiconductor layer 404, a second metal layer, a transparent electrode layer, and a second insulating layer 407.
  • the difference between the array substrate 40 of the preferred embodiment and the array substrate 20 of the first preferred embodiment is that since the liquid crystal display panel of the preferred embodiment is a vertical alignment type display panel, the transparent electrode layer of the array substrate 40 has many
  • the separated pixel electrodes 4061 are such that the power lines between the array substrate 40 and the color filter substrate (not shown) are bent, so that the liquid crystal molecules in each pixel have different deflection angles at the same driving voltage, so that the liquid crystals The viewing angle of the display panel is better.
  • the A region of the array substrate 40 includes a thin film field effect transistor
  • the B region of the array substrate 40 includes a pixel electrode 4061 formed of a transparent electrode layer
  • the C region of the array substrate 40 includes an internal connection electrode 4063 formed by a transparent electrode layer
  • the array substrate The D region of 40 includes a trace 4053 formed by the second metal layer 405 and a reinforcement portion 4062 formed by the transparent electrode layer 406.
  • the E region of the array substrate 40 includes an external connection electrode 4064 formed by the transparent electrode layer 406.
  • the working principle of the liquid crystal display panel of the preferred embodiment is the same as or similar to that of the first preferred embodiment. For details, refer to the related description in the first preferred embodiment.
  • the manufacturing process of the array substrate of the liquid crystal display panel of the preferred embodiment is the same as or similar to that of the first preferred embodiment of the array substrate. For details, refer to the related description in the first preferred embodiment.
  • the array substrate, the manufacturing method and the liquid crystal display panel of the invention are provided with reinforcing portions on the traces through the transparent electrode layer, so that the traces located in the second metal layer are more firm and not easily broken, thereby ensuring the display quality of the corresponding liquid crystal display panel.
  • the invention solves the technical problem that the second metal layer as the trace in the existing array substrate is easily broken, thereby causing the display quality of the corresponding liquid crystal display panel to be degraded.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、制作方法及液晶显示面板。阵列基板（20）包括：基板衬底（201）、第一金属层（202）、第一绝缘层（203）、半导体层（204）、第二金属层、透明电极层以及第二绝缘层（207）；其中透明电极层包括像素电极（2061）以及加固部（2062）。通过透明电极在走线上设置加固部，使位于第二金属层的走线更加牢固、不易断裂。

Description

阵列基板、制作方法及液晶显示面板 技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板、制作方法及液晶显示面板。
 背景技术
薄膜晶体管液晶显示面板作为低碳绿色环保型显示器件，已广泛应用到人们的生产生活中。随着显示技术的发展，产品质量与产品成本成为液晶显示面板的制造企业的竞争动力。
对于面板厂商而言，为了降低产品的生产成本，一般会尽可能的减少面板中驱动芯片的使用数量，如通过增加走线长度使得每个驱动芯片可以驱动尽可能多的元件，因此在大尺寸液晶显示面板中，一般会采用双层金属走线的设计来降低走线长度过长带来的线电阻过大的技术问题。
现有的双层金属走线的具体结构请参照图1，图1为现有的液晶显示面板的阵列基板的结构示意图。为了便于说明，图中的结构的具体尺寸按说明的需要进行了修改。其中图1中的101为基板，102为第一绝缘层，103为第二绝缘层，104为第一金属层，105为第二金属层，106为像素电极层，其中106也可为用于内部连接的电极（如连接第一金属层104和第二金属层105等）或用于与外部连接的电极（如与驱动芯片连接等）。
按该阵列基板的各部分的功能将该阵列基板分为五个部分，其中A区为薄膜场效应晶体管，B区为像素电极，C区为跳线区（即实现两个金属层的连接），D区为走线的扇出区域，E区为与驱动芯片连接的连接区域。
D区通过第一金属层104和第二金属层105进行走线，可很好的避免走线的线电阻过大的问题。但是由于第二金属层105一般设置非平面膜上，即第二金属层105的下方往往不平整，这样容易导致第二金属层105的断裂，从而导致D区的走线无法正常传输信号，同时该缺陷在阵列基板的制作过程中难以发现影响，大大影响了液晶显示面板的显示品质。
故，有必要提供一种阵列基板、制作方法及液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板、制作方法及液晶显示面板，以解决现有的阵列基板中作为走线的第二金属层易断裂，从而导致相应的液晶显示面板的显示品质下降的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种阵列基板，其包括：
基板衬底；
第一金属层，位于在所述基板衬底上，包括扫描线以及薄膜场效应晶体管的栅极区；
第一绝缘层，部分位于所述第一金属层上；
半导体层，位于所述第一绝缘层上；
第二金属层，位于所述半导体层上，包括所述薄膜场效应晶体管的源极区、所述薄膜场效应晶体管的漏极区、数据线以及走线；
透明电极层，包括：
像素电极，用于与所述漏极区连接；以及
加固部，覆盖在所述走线上；以及
第二绝缘层，位于所述透明电极层以及所述薄膜场效应晶体管上。
在本发明所述的阵列基板中，所述透明电极层还包括：
内部连接电极，用于连接所述第一金属层和所述第二金属层。
在本发明所述的阵列基板中，所述透明电极层还包括：
外部连接电极，用于连接所述第一金属层与所述驱动芯片，以及连接所述第二金属层与所述驱动芯片。
在本发明所述的阵列基板中，所述第一金属层的厚度为0.1微米至0.6微米，所述第二金属层的厚度为0.1微米至0.6微米。
在本发明所述的阵列基板中，所述第一绝缘层的厚度为0.2微米至0.5微米，所述半导体层的厚度为0.1微米至0.3微米，所述第二绝缘层的厚度为0.2微米至0.5微米。
在本发明所述的阵列基板中，所述透明电极层的厚度为0.01微米至0.1微米。
本发明实施例还提供一种阵列基板的制作方法，其包括：
A、形成分层结构于基板衬底上，所述分层结构为第一金属层；
B、对所述分层结构进行图形化处理，以形成扫描线以及薄膜场效应晶体管的栅极区；
C、在所述分层结构上依次形成第一绝缘层、半导体层以及第二金属层；
D、对所述分层结构进行图形化处理，以形成所述薄膜场效应晶体管的源极区、所述薄膜场效应晶体管的漏极区、数据线以及走线；
E、在所述分层结构上形成透明电极层；并对所述分层结构进行图形化处理，以形成像素电极以及覆盖在所述走线上的所述加固部；以及
F、在所述分层结构上形成第二绝缘层，并对所述分层结构进行图形化处理，以对透明电极层和所述薄膜场效应晶体管进行覆盖。
在本发明所述的阵列基板的制作方法中，所述步骤E还包括：
在所述分层结构上形成透明电极层；并对所述分层结构进行图形化处理，以形成内部连接电极；
其中所述内部连接电极用于连接所述第一金属层和所述第二金属层。
在本发明所述的阵列基板的制作方法中，所述步骤E还包括：
在所述分层结构上形成透明电极层；并对所述分层结构进行图形化处理，以形成外部连接电极；
其中所述外部连接电极用于连接所述第一金属层与所述驱动芯片，以及连接所述第二金属层与所述驱动芯片。
在本发明所述的阵列基板的制作方法中，所述第一金属层的厚度为0.1微米至0.6微米，所述第二金属层的厚度为0.1微米至0.6微米。
在本发明所述的阵列基板的制作方法中，所述第一绝缘层的厚度为0.2微米至0.5微米，所述半导体层的厚度为0.1微米至0.3微米，所述第二绝缘层的厚度为0.2微米至0.5微米。
在本发明所述的阵列基板的制作方法中，所述透明电极层的厚度为0.01微米至0.1微米。
本发明实施例还提供一种液晶显示面板，其包括膜基板、阵列基板以及设置在所述彩膜基板和所述阵列基板之间的液晶层；
其中所述阵列基板包括：
基板衬底；
第一金属层，位于在所述基板衬底上，包括扫描线以及薄膜场效应晶体管的栅极区；
第一绝缘层，部分位于所述第一金属层上；
半导体层，位于所述第一绝缘层上；
第二金属层，位于所述半导体层上，包括所述薄膜场效应晶体管的源极区、所述薄膜场效应晶体管的漏极区、数据线以及走线；
透明电极层，包括：
像素电极，用于与所述漏极区连接；以及
加固部，覆盖在所述走线上；以及
第二绝缘层，位于所述透明电极层以及所述薄膜场效应晶体管上。
在本发明所述的液晶显示面板中，所述透明电极层还包括：
内部连接电极，用于连接所述第一金属层和所述第二金属层。
在本发明所述的液晶显示面板中，所述透明电极层还包括：
外部连接电极，用于连接所述第一金属层与所述驱动芯片，以及连接所述第二金属层与所述驱动芯片。
在本发明所述的液晶显示面板中，所述液晶显示面板为扭曲向列型显示面板或垂直配向型显示面板。
在本发明所述的液晶显示面板中，所述第一金属层的厚度为0.1微米至0.6微米，所述第二金属层的厚度为0.1微米至0.6微米。
在本发明所述的液晶显示面板中，所述第一绝缘层的厚度为0.2微米至0.5微米，所述半导体层的厚度为0.1微米至0.3微米，所述第二绝缘层的厚度为0.2微米至0.5微米。
在本发明所述的液晶显示面板中，所述透明电极层的厚度为0.01微米至0.1微米。
 有益效果
相较于现有的阵列基板、制作方法及液晶显示面板，本发明的阵列基板、制作方法及液晶显示面板通过透明电极层在走线上设置加固部，使得位于第二金属层的走线更加牢固，不易断裂，从而保证了相应的液晶显示面板的显示品质；解决了现有的阵列基板中作为走线的第二金属层易断裂，从而导致相应的液晶显示面板的显示品质下降的技术问题。
附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图 1 为现有的液晶显示面板的阵列基板的结构示意图；
图 2 为本发明的液晶显示面板的阵列基板的第一优选实施例的结构示意图；
图 3 为本发明的液晶显示面板的阵列基板的第一优选实施例的制作流程图；
图4 为本发明的液晶显示面板的阵列基板的第二优选实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的液晶显示面板的阵列基板的第一优选实施例的结构示意图。本优选实施例的液晶显示面板为扭曲向列型显示面板（Twisted Nematic），该液晶显示面板的阵列基板20包括基板衬底201、第一金属层202、第一绝缘层203、半导体层204、第二金属层、透明电极层以及第二绝缘层207。
第一金属层202位于基板衬底201上，包括扫描线以及薄膜场效应晶体管的栅极区；第一绝缘层203部分位于第一金属层202上；半导体层204位于第一绝缘层203上；第二金属层位于半导体层204上，包括薄膜场效应晶体管的源极区2051、薄膜场效应晶体管的漏极区2052、数据线（图中未示出）以及走线2053；透明电极层包括用于与薄膜场效应晶体管的漏极区2052连接的像素电极2061以及覆盖在走线2053上的加固部2062；第二绝缘层207位于透明电极层以及薄膜场效应晶体管上。其中透明电极层206还包括内部连接电极2063以及外部连接电极2064，内部连接电极2063用于连接第一金属层202以及第二金属层205；外部连接电极2064用于连接第一金属层202与驱动芯片以及连接第二金属层205与驱动芯片。
请参照图2，为了便于对阵列基板20的功能进行说明，图2中阵列基板的区域划分的尺寸并非该区域在阵列基板中的实际尺寸。其中阵列基板20的A区包括薄膜场效应晶体管，阵列基板的B区包括透明电极层形成的像素电极2061，阵列基板的C区包括透明电极层形成的内部连接电极2063，阵列基板的D区包括第二金属层形成的走线2053以及透明电极层形成的加固部2062，阵列基板的E区包括透明电极层形成的外部连接电极2064。
本优选实施例的液晶显示面板的阵列基板20使用时，阵列基板20的A区的薄膜场效应晶体管与图1中的A区的薄膜场效应晶体管的结构相似，工作原理相同。
阵列基板20的B区的像素电极2061与图1中的B区的像素电极的区别在于，本优选实施例中的像素电极2061设置在第二绝缘层207下，但是第二绝缘层207一般为透明的氮化硅薄膜，不会影响到像素电极2061的正常功能，因此本优选实施例中B区的像素电极2061的工作原理也与图1中的B区的像素电极的工作原理相同。
阵列基板的C区的内部连接电极2063与图1中的C区的跳线区的区别在于本优选实施例中的内部连接电极2063设置在第二绝缘层207下，但是同样由于第二绝缘层207为透明的氮化硅薄膜，不会影响到内部连接电极2063的正常功能，因此本优选实施例中，C区的内部连接电极2063的工作原理也与图1中的C区的跳线区的工作原理相同。
阵列基板的D区的走线2053与图1中的D区的走线的扇出区域的区别在于本优选实施例中的走线2053上覆盖有透明电极层形成的加固部2062，这样加固部2062可以加强第二金属层上走线2053的稳定性，使得第二金属层上的走线2053不易断裂，且由于加固部2062也有导电材料制成，因此可进一步加强走线2053的导电性。D区的走线2053的具体工作原理与图1中的D区的走线的工作原理相同。
阵列基板的E区的外部连接电极2064可很好实现驱动芯片分别与第一金属层202和第二金属层的连接，因此也与图1中的E区的作用和工作原理相同。
下面通过图3详细说明本优选实施例的液晶显示面板的阵列基板的制作流程。图3为本发明的液晶显示面板的阵列基板的第一优选实施例的制作流程图。该阵列基板的制作方法包括：
步骤S301，形成分层结构于基板衬底上，该分层结构为第一金属层。具体可为：在基板衬底上按0.1微米至0.6微米的厚度制作第一金属层，该金属层的材料可为铬、钼、铝或铜等。随后转到步骤S302。
步骤S302，对分层结构进行图像化处理，以形成扫描线以及薄膜场效应晶体管的栅极区。具体可为：采用光罩工艺对第一金属层进行湿刻处理，以形成扫描线以及薄膜场效应晶体管的栅极区。随后转到步骤S303。
步骤S303，在分层结构上依次形成第一绝缘层、半导体层以及第二金属层。具体可为：在分层结构上按0.2微米至0.5微米的厚度制作第一绝缘层（如氮化硅层），然后按0.1微米至0.3微米的厚度制作中作半导体层（如非晶硅层），随后按0.1微米至0.6微米制作第二金属层。随后转到步骤S304。
步骤S304，对分层结构进行图形化处理，以形成薄膜场效应晶体管的源极区、薄膜场效应晶体管的漏极区、数据线以及走线。具体可为：采用灰阶光罩工艺（gray tone）对上述分层结构进行图形化处理，在阵列基板的C区和E区，对第二金属层进行湿法刻蚀、对半导体层进行干法刻蚀以及对第一绝缘层进行干法刻蚀，形成连接到第一金属层的过孔。
在阵列基板的B区，对第二金属层进行湿法刻蚀，对半导体层进行干法刻蚀，形成像素电极区域。
在阵列基板的A区，对第二金属层进行湿法刻蚀，对半导体层进行干法刻蚀，形成薄膜场效应晶体管的源极区、薄膜场效应晶体管的漏极区以及源极区和漏极区之间的沟道，同时也形成了液晶显示面板的数据线。
在阵列基板的D区，对第二金属层进行湿法刻蚀，对半导体层进行干法刻蚀，形成了液晶显示面板的走线。随后转到步骤S305。
步骤S305，在分层结构上形成透明电极层，并对分层结构进行图形化处理，以形成像素电极以及覆盖在走线上的加固部。具体可为：在分层结构上按0.01微米至0.1微米的厚度制作透明电极层（如氧化铟锡或氧化铟锌等）。采用光罩工艺对上述分层结构进行图形化处理，在阵列基板的B区形成像素电极，在阵列基板的C区形成内部连接电极（通过位于C区的过孔），在阵列基板的D区形成覆盖在走线上的加固部，在阵列基板的E区形成外部连接电极（通过位于E区的过孔）。随后转到步骤S306。
步骤S306，在分层结构上形成第二绝缘层，并对分层结构进行图形化处理，以对透明电极层和薄膜场效应晶体管进行覆盖。具体可为：在分层结构上按0.2微米至0.5微米的厚度制作第二绝缘层。采用光罩工艺对上述分层结构进行图形化处理，以对透明电极层和薄膜场效应晶体管进行覆盖保护。
这样即完成了本优选实施例的液晶显示面板的阵列基板的制作流程。
本优选实施例的阵列基板、制作方法及液晶显示面板通过透明电极层在走线上设置加固部，使得位于地二金属层的走线更加牢固，不易断裂，从而保证了相应的液晶显示面板的显示品质。
请参照图4，图4为本发明的液晶显示面板的阵列基板的第二优选实施例的结构示意图。本优选实施例的液晶显示面板为垂直配向型显示面板（Vertical Alignment），该液晶显示面板的阵列基板40包括基板衬底401、第一金属层402、第一绝缘层403、半导体层404、第二金属层、透明电极层以及第二绝缘层407。
本优选实施例的阵列基板40与第一优选实施例中的阵列基板20的区别在于，由于本优选实施例的液晶显示面板为垂直配向型显示面板，因此该阵列基板40的透明电极层具有多个分离的像素电极4061，使得阵列基板40和彩膜基板（图中未示出）之间的电力线产生弯曲，从而使得每个像素中的液晶分子同一驱动电压下的偏转角度不同，使得该液晶显示面板的视角特性较好。
同样，该阵列基板40的A区包括薄膜场效应晶体管，阵列基板40的B区包括透明电极层形成的像素电极4061，阵列基板40的C区包括透明电极层形成的内部连接电极4063，阵列基板40的D区包括第二金属层405形成的走线4053以及透明电极层406形成的加固部4062，阵列基板40的E区包括透明电极层406形成的外部连接电极4064。
本优选实施例的液晶显示面板的工作原理与上述的第一优选实施例的工作原理相同或相似，具体请参见上述第一优选实施例中的相关描述。
本优选实施例的液晶显示面板的阵列基板的制作流程与上述的阵列基板的第一优选实施例的制作流程相同或相似，具体请参见上述第一优选实施例中的相关描述。
本发明的阵列基板、制作方法及液晶显示面板通过透明电极层在走线上设置加固部，使得位于第二金属层的走线更加牢固，不易断裂，从而保证了相应的液晶显示面板的显示品质；解决了现有的阵列基板中作为走线的第二金属层易断裂，从而导致相应的液晶显示面板的显示品质下降的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
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Claims (19)

  1. 一种阵列基板，其包括：
    基板衬底；
    第一金属层，位于在所述基板衬底上，包括扫描线以及薄膜场效应晶体管的栅极区；
    第一绝缘层，部分位于所述第一金属层上；
    半导体层，位于所述第一绝缘层上；
    第二金属层，位于所述半导体层上，包括所述薄膜场效应晶体管的源极区、所述薄膜场效应晶体管的漏极区、数据线以及走线；
    透明电极层，包括：
    像素电极，用于与所述漏极区连接；以及
    加固部，覆盖在所述走线上；以及
    第二绝缘层，位于所述透明电极层以及所述薄膜场效应晶体管上。
  2. 根据权利要求1所述的阵列基板，其中所述透明电极层还包括：
    内部连接电极，用于连接所述第一金属层和所述第二金属层。
  3. 根据权利要求1所述的阵列基板，其中所述透明电极层还包括：
    外部连接电极，用于连接所述第一金属层与所述驱动芯片，以及连接所述第二金属层与所述驱动芯片。
  4. 根据权利要求1所述的阵列基板，其中所述第一金属层的厚度为0.1微米至0.6微米，所述第二金属层的厚度为0.1微米至0.6微米。
  5. 根据权利要求1所述的阵列基板，其中所述第一绝缘层的厚度为0.2微米至0.5微米，所述半导体层的厚度为0.1微米至0.3微米，所述第二绝缘层的厚度为0.2微米至0.5微米。
  6. 根据权利要求1所述的阵列基板，其中所述透明电极层的厚度为0.01微米至0.1微米。
  7. 一种阵列基板的制作方法，其包括：
    A、形成分层结构于基板衬底上，所述分层结构为第一金属层；
    B、对所述分层结构进行图形化处理，以形成扫描线以及薄膜场效应晶体管的栅极区；
    C、在所述分层结构上依次形成第一绝缘层、半导体层以及第二金属层；
    D、对所述分层结构进行图形化处理，以形成所述薄膜场效应晶体管的源极区、所述薄膜场效应晶体管的漏极区、数据线以及走线；
    E、在所述分层结构上形成透明电极层；并对所述分层结构进行图形化处理，以形成像素电极以及覆盖在所述走线上的所述加固部；以及
    F、在所述分层结构上形成第二绝缘层，并对所述分层结构进行图形化处理，以对透明电极层和所述薄膜场效应晶体管进行覆盖。
  8. 根据权利要求7所述的阵列基板的制作方法，其中所述步骤E还包括：
    在所述分层结构上形成透明电极层；并对所述分层结构进行图形化处理，以形成内部连接电极；
    其中所述内部连接电极用于连接所述第一金属层和所述第二金属层。
  9. 根据权利要求7所述的阵列基板的制作方法，其中所述步骤E还包括：
    在所述分层结构上形成透明电极层；并对所述分层结构进行图形化处理，以形成外部连接电极；
    其中所述外部连接电极用于连接所述第一金属层与所述驱动芯片，以及连接所述第二金属层与所述驱动芯片。
  10. 根据权利要求7所述的阵列基板的制作方法，其中所述第一金属层的厚度为0.1微米至0.6微米，所述第二金属层的厚度为0.1微米至0.6微米。
  11. 根据权利要求7所述的阵列基板的制作方法，其中所述第一绝缘层的厚度为0.2微米至0.5微米，所述半导体层的厚度为0.1微米至0.3微米，所述第二绝缘层的厚度为0.2微米至0.5微米。
  12. 根据权利要求7所述的阵列基板的制作方法，其中所述透明电极层的厚度为0.01微米至0.1微米。
  13. 一种液晶显示面板，其包括彩膜基板、阵列基板以及设置在所述彩膜基板和所述阵列基板之间的液晶层；
    其中所述阵列基板包括：
    基板衬底；
    第一金属层，位于在所述基板衬底上，包括扫描线以及薄膜场效应晶体管的栅极区；
    第一绝缘层，部分位于所述第一金属层上；
    半导体层，位于所述第一绝缘层上；
    第二金属层，位于所述半导体层上，包括所述薄膜场效应晶体管的源极区、所述薄膜场效应晶体管的漏极区、数据线以及走线；
    透明电极层，包括：
    像素电极，用于与所述漏极区连接；以及
    加固部，覆盖在所述走线上；以及
    第二绝缘层，位于所述透明电极层以及所述薄膜场效应晶体管上。
  14. 根据权利要求13所述的液晶显示面板，其中所述透明电极层还包括：
    内部连接电极，用于连接所述第一金属层和所述第二金属层。
  15. 根据权利要求13所述的液晶显示面板，其中所述透明电极层还包括：
    外部连接电极，用于连接所述第一金属层与所述驱动芯片，以及连接所述第二金属层与所述驱动芯片。
  16. 根据权利要求13所述的液晶显示面板，其中所述液晶显示面板为扭曲向列型显示面板或垂直配向型显示面板。
  17. 根据权利要求13所述的液晶显示面板，其中所述第一金属层的厚度为0.1微米至0.6微米，所述第二金属层的厚度为0.1微米至0.6微米。
  18. 根据权利要求13所述的液晶显示面板，其中所述第一绝缘层的厚度为0.2微米至0.5微米，所述半导体层的厚度为0.1微米至0.3微米，所述第二绝缘层的厚度为0.2微米至0.5微米。
  19. 根据权利要求13所述的液晶显示面板，其中所述透明电极层的厚度为0.01微米至0.1微米。
PCT/CN2014/080794 2014-05-30 2014-06-26 阵列基板、制作方法及液晶显示面板 WO2015180225A1 (zh)

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