WO2015176597A1 - Procédé et système de communication basée sur ebpsk - Google Patents

Procédé et système de communication basée sur ebpsk Download PDF

Info

Publication number
WO2015176597A1
WO2015176597A1 PCT/CN2015/077852 CN2015077852W WO2015176597A1 WO 2015176597 A1 WO2015176597 A1 WO 2015176597A1 CN 2015077852 W CN2015077852 W CN 2015077852W WO 2015176597 A1 WO2015176597 A1 WO 2015176597A1
Authority
WO
WIPO (PCT)
Prior art keywords
ebpsk
return
bit synchronization
zero code
synchronization clock
Prior art date
Application number
PCT/CN2015/077852
Other languages
English (en)
Chinese (zh)
Inventor
夏树强
冯熳
吴乐南
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2015176597A1 publication Critical patent/WO2015176597A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying

Definitions

  • the present invention relates to a digital communication system, and more particularly to a transmitter for extended Binary Phase Shift Keying (EBPSK) coded modulation communication and a corresponding fast bit synchronization and demodulation decoding method, belonging to a digital The field of information modulation and demodulation in communications.
  • EBPSK Binary Phase Shift Keying
  • a process of moving a baseband signal representing a transmitted data to a desired transmission band is called modulation, and vice versa.
  • modulation a process of moving a baseband signal representing a transmitted data to a desired transmission band.
  • a binary data symbol “0" "1” can be used to change a certain parameter of the sinusoidal carrier in the symbol period, such as amplitude, frequency or phase, to obtain corresponding amplitude keying (2ASK), frequency.
  • Shift keying (2FSK) and phase shift keying (2PSK) modulation If the modulation period t ⁇ T, an asymmetrical binary offset keying modulation is obtained.
  • a typical asymmetric binary phase shift keying modulation, called EBPSK has a uniform expression:
  • f 0 (t) and f 1 (t) represent modulation waveforms of symbols "0" and "1", respectively.
  • f c denotes the modulation carrier frequency
  • A B is the amplitude of the carrier keying
  • N is the ratio of the symbol period to the carrier period, that is, the number of carrier periods in one symbol;
  • K(K ⁇ N) is the number of hopping carrier periods in the symbol period
  • ⁇ is the hopping angle.
  • Spread spectrum is to modulate signal information with signal-independent spreading symbols and to modulate The signal is spread into a frequency band that is much larger than the minimum bandwidth required for the original signal, and despread at the receiving end with the same spreading symbol to recover the original signal.
  • Spread spectrum communication greatly expands the bandwidth required to transmit information. According to Shannon's formula, bandwidth can be exchanged for signal-to-noise ratio to make the system work in a more severe channel environment.
  • the receiving end needs the PN code synchronization module for despreading.
  • the traditional synchronous implementation is divided into two modules: PN code acquisition and PN code tracking.
  • Pseudo code capture generally uses a matched filter.
  • the choice of matched filter number is a compromise between capture time and system complexity. The more the number, the shorter the capture time, but the higher the complexity.
  • Pseudo-code tracking is transferred to pseudo-code tracking.
  • Pseudo-code tracking generally uses a delay-locked loop. Due to the feedback and constant adjustment process of the closed-loop pseudo-code tracking structure, it will directly affect its speed of error elimination.
  • Channel coding is to add redundant symbols at the transmitting end to protect data during data transmission and to perform error detection and error correction at the receiving end.
  • Currently mature channel coding has a block code, a convolutional code, and the like.
  • the existing bit synchronization techniques can generally be divided into two major categories, the external synchronization method and the self-synchronization method.
  • the external synchronization method is a method for synchronizing auxiliary information, and a pilot or data sequence containing symbol timing information is additionally added to the signal to achieve the purpose of extracting bit synchronization information.
  • the advantage of this method is that the device is relatively simple, but The disadvantages are also obvious, requiring a certain frequency band and transmission power. At present, there are not many external synchronization methods used in digital communication systems.
  • the self-synchronization method usually adopts a closed-loop bit synchronization method, which is characterized in that the received signal is compared with a locally generated symbol timing signal to keep the locally generated timing signal and the transition point of the received symbol waveform synchronized, and a widely used research method
  • the closed loop synchronizer is called the lead/lag gate synchronizer. This method is similar to the traditional phase-locked loop method of carrier frequency synchronization. Due to the feedback link and the continuous adjustment process in the closed-loop method, it will directly affect its speed of elimination.
  • the object of the present invention is to provide an EBPSK-based communication method and system for the special asymmetric modulation mode of EBPSK modulation, which aims to solve the anti-interference performance of the simple EBPSK modulation system, and can combine EBPSK modulation.
  • the advantages and features of the system enhance the anti-jamming capability of the EBPSK communication system.
  • an EBPSK-based communication method including:
  • the transmitting end encodes the information sequence and performs EBPSK modulation processing to obtain an EBPSK modulated signal
  • the receiving end performs EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.
  • the transmitting end encodes and modulates the information sequence
  • the step of obtaining the EBPSK modulated signal specifically includes:
  • the transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and saves;
  • Corresponding f0 waveform samples and f1 waveform samples are selected for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • the step of encoding the information sequence to obtain the coding sequence comprises:
  • the receiving end performs demodulation and decoding processing on the EBPSK modulated signal, and the step of obtaining the information sequence includes:
  • the correlation integral value is subjected to sampling decision processing to obtain a sequence of information.
  • the step of determining a chip bit synchronization clock according to the obtained first return-to-zero code comprises:
  • the delay amount of the impact envelope is obtained according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1";
  • the delay of the impact envelope is adjusted so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.
  • the step of adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code comprises:
  • the symbol bit synchronization clock is reset.
  • an EBPSK-based code modulation method including:
  • the transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and saves;
  • Corresponding f0 waveform samples and f1 waveform samples are selected for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • the step of encoding the information sequence to obtain the coding sequence comprises:
  • an EBPSK-based decoding and demodulation method including:
  • the correlation integral value is subjected to sampling decision processing to obtain a sequence of information.
  • the step of determining a chip bit synchronization clock according to the obtained first return-to-zero code comprises:
  • the delay amount of the impact envelope is obtained according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1";
  • the delay of the impact envelope is adjusted so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.
  • the step of adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code comprises:
  • the symbol bit synchronization clock is reset.
  • an EBPSK based communication system comprising a transmitter and a receiver, wherein:
  • the transmitter is configured to perform coding and EBPSK modulation processing on the information sequence to obtain an extended binary phase shift keying EBPSK modulated signal;
  • the receiver is configured to perform EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.
  • the transmitter specifically includes:
  • a sampling module configured to discretize EBPSK modulated waveforms f0 and f1 respectively corresponding to symbols 0 and 1, to obtain f0 waveform samples and f1 waveform samples and save;
  • An encoding module configured to encode the information sequence to obtain a coding sequence
  • a modulation module configured to select a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • said encoding module obtains a coded sequence by multiplying said sequence of information with said pseudo-random sequence.
  • the receiver comprises:
  • a demodulation module configured to input an EBPSK modulation signal to the digital impulse filter, and perform an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, obtaining an impact envelope integral value;
  • a decoding module configured to perform correlation and integration processing on the integrated value of the impact envelope and the local pseudo-random sequence by using the chip bit synchronization clock to obtain a correlation integral value; and performing a second threshold detection on the correlation integral value Obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code; using the symbol-bit synchronous clock to sample the relevant integral value The decision is processed to obtain a sequence of information.
  • the demodulation module determines whether the generated first return-to-zero code is "1", and if the generated first return-to-zero code is "1", according to the highest point of the impact envelope and the first return-to-zero code The relative position relationship of the falling edge of "1", the delay amount of the impact envelope is obtained, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock and the impact packet The highest point of the network is aligned.
  • the decoding module determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol bit synchronization clock.
  • an EBPSK-based transmitter comprising:
  • a sampling module configured to discretize EBPSK modulated waveforms f0 and f1 respectively corresponding to symbols 0 and 1, to obtain f0 waveform samples and f1 waveform samples and save;
  • An encoding module configured to encode the information sequence to obtain a coding sequence
  • a modulation module configured to select a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • the sampling module obtains a coding sequence by multiplying the information sequence with the pseudo random sequence.
  • an EBPSK-based receiver comprising:
  • a demodulation module configured to input an EBSK modulation signal to the digital impulse filter, and perform an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, obtaining an impact envelope integral value;
  • a decoding module configured to perform correlation and integration processing on the integrated value of the impact envelope and the local pseudo-random sequence by using the chip bit synchronization clock to obtain a correlation integral value; and performing a second threshold detection on the correlation integral value , obtaining a second return-to-zero code, and according to the obtained second return-to-zero code, Adjusting the symbol bit synchronization clock; using the symbol bit synchronization clock, performing sampling decision processing on the correlation integral value to obtain an information sequence.
  • the demodulation module determines whether the generated first return-to-zero code is "1", and if the generated first return-to-zero code is "1", according to the highest point of the impact envelope and the first return-to-zero code The relative position relationship of the falling edge of "1", the delay amount of the impact envelope is obtained, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock and the impact packet The highest point of the network is aligned.
  • the decoding module determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol bit synchronization clock.
  • chip bit synchronization can be realized in two chip periods, and symbol bit synchronization can be realized in two symbol periods, because the occurrence of symbol “0” “1” in the communication system is equal probability. .
  • the receiver is simpler.
  • the receiver of the present invention adopts an open loop system, which replaces the classical digital phase-locked loop bit synchronization and delay phase-locked loop PN code synchronization system, which greatly simplifies the structure of the receiver.
  • the transmitter adopts the "1+1" structure, that is, the encoder and the modulator, the implementation of the receiver is also simpler while improving the anti-interference performance of the system, and the effect of "1+1>2" is achieved.
  • the receiver can be fully digitally integrated and at a lower cost.
  • the demodulator and decoder circuit structures of the EBPSK coded modulated signals shown in Fig. 6 and Fig. 7 respectively can be seen. Not only the demodulator and the decoder can be digitally integrated, but the whole receiver can be fully digitally integrated from below the intermediate frequency, and the structure is easier. Realized, the cost is lower.
  • FIG. 1 is a schematic block diagram of an EBPSK-based communication method provided by the present invention.
  • FIG. 2 is a schematic block diagram of an EBPSK-based code modulation method provided by the present invention.
  • FIG. 3 is a schematic block diagram of an EBPSK-based transmitter provided by the present invention.
  • FIG. 4 is a schematic block diagram of an EBPSK-based demodulation and decoding method provided by the present invention.
  • FIG. 5 is a schematic block diagram of an EBPSK-based receiver provided by the present invention.
  • FIG. 6 is a block diagram of a transmitter implementation according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a transmitter operation according to an embodiment of the present invention.
  • FIG. 8 is a block diagram of an EBPSK-based communication receiving end module according to an embodiment of the present invention.
  • FIG. 9 is a general block diagram of a conventional EBPSK modulated receiver
  • FIG. 10 is a block diagram of an implementation of digital demodulation of a receiver of an EBPSK coded modulation system according to an embodiment of the present invention, which is characterized in that an analog phase locked loop and a digital phase locked loop are removed;
  • FIG. 11 is a block diagram of an implementation of digital decoding of a receiver of an EBPSK coded modulation system according to an embodiment of the present invention, wherein the correlation integrator is generally implemented by a series matched filter;
  • FIG. 12 is a flowchart showing the operation of a receiver of an EBPSK code modulation system according to an embodiment of the present invention.
  • Figure 13 is an EBPSK encoded waveform
  • Figure 14 is a time-domain waveform diagram of the EBPSK coded modulated signal before and after passing through the digital impulse filter;
  • Figure 15 is a relative positional relationship diagram of the falling edge of the highest value of the impact envelope of the EBPSK modulation coefficient and the return-to-zero code "1";
  • 16 is an effect diagram of demodulating and decoding an EBPSK coded modulation waveform by the novel receiver proposed by the present invention
  • Figure 17 is an EBPSK modulated power spectrum estimate
  • Figure 18 is an EBPSK coded modulation power spectrum estimate
  • Figure 19 is an anti-interference performance curve of an uncoded EBPSK communication system
  • Figure 20 is an anti-interference performance curve of an EBPSK coded modulation communication system.
  • FIG. 1 is a schematic block diagram of an EBPSK-based communication method according to an embodiment of the present invention. As shown in FIG. 1, the steps include:
  • Step S101 The transmitting end encodes the information sequence and EBPSK modulation processing to obtain an extended binary phase shift keying EBPSK modulated signal.
  • the transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and stores them; and encodes the information sequence to obtain a coding sequence, specifically
  • the coding sequence is obtained by multiplying the information sequence with the pseudo-random sequence; selecting corresponding f0 waveform samples and f1 waveform samples for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • Step S102 The receiving end performs EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.
  • the EBSK modulation signal is input to the digital impulse filter, and the signal outputted by the digital impulse filter is subjected to a low-pass filtering process to obtain an impact envelope of the output signal; Performing the first threshold detection to obtain the first return-to-zero code, and Determining, according to the obtained first return-to-zero code, a chip bit synchronization clock; using the chip bit synchronization clock, performing integral processing on the impact envelope to obtain an impact envelope integral value, and using the impact envelope
  • the integral value is correlated and integrated with the local pseudo-random sequence to obtain a correlation integral value; the second threshold detection is performed on the correlation integral value to obtain a second return-to-zero code, and adjusted according to the obtained second return-to-zero code
  • a symbol bit synchronization clock using the symbol bit synchronization clock, performing a sampling decision process on the correlation integral value to obtain an information sequence.
  • the receiving end determines whether the first return-to-zero code generated is “1”, and if the generated first return-to-zero code is “1”, then the highest point of the impact envelope and the first return-to-zero code “1” are decreased.
  • the relative position relationship of the edge obtains the delay amount of the impact envelope, otherwise the delay amount is zero; according to the obtained delay amount, the delay of the impact envelope is adjusted to make the rising edge of the chip bit synchronous clock and The highest point of the impact envelope is aligned.
  • the receiving end determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol-bit synchronous clock.
  • the present invention also provides a communication system that implements the method of Figure 1, comprising a transmitter and a receiver.
  • the transmitter is configured to encode the information sequence and EBPSK modulation processing to obtain an extended binary phase shift keying EBPSK modulated signal, which includes each module shown in FIG.
  • the receiver is configured to perform EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence, which includes the modules shown in FIG.
  • FIG. 2 is a schematic block diagram of an EBPSK-based code modulation method provided by the present invention. As shown in FIG. 2, the steps include:
  • Step S1011 The transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, to obtain the f0 waveform sample and the f1 waveform sample and save.
  • Step S1012 Encoding the information sequence to obtain a coding sequence, specifically, obtaining a coding sequence by multiplying the information sequence by the pseudo random sequence.
  • Step S1013 Select corresponding f0 waveform samples and f1 waveform samples for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • the present invention provides a transmitter for implementing the method of FIG. 2, as shown in FIG.
  • the radiographer encodes the information sequence (ie, the source sequence) and EBPSK modulation to obtain an EBPSK modulated signal.
  • the transmitter specifically includes: a module 21, an encoding module 22, and a modulation module 23.
  • the sampling module 21 discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, to obtain the f0 waveform samples and the f1 waveform samples and save them.
  • the encoding module 22 encodes the information sequence to obtain a coding sequence, specifically, by multiplying the information sequence by the pseudo random sequence to obtain a coding sequence.
  • the modulation module 23 selects a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.
  • FIG. 4 is a schematic block diagram of an EBPSK-based demodulation and decoding method provided by the present invention. As shown in FIG. 4, the steps include:
  • Step S1021 Input the EBPSK modulation signal to the digital impulse filter, and take an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal.
  • Step S1022 Perform a first threshold detection on the impact envelope of the output signal to obtain a first return-to-zero code, and determine a chip bit synchronization clock according to the obtained first return-to-zero code.
  • the step of determining the chip bit synchronization clock according to the obtained first return-to-zero code includes: determining whether the generated first return-to-zero code is “1”, and if the generated first return-to-zero code is “1” Then, according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1", the delay amount of the impact envelope is obtained, and the impact package is adjusted according to the obtained delay amount.
  • the delay of the network is such that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.
  • Step S1023 Integrating the impact envelope with the chip bit synchronization clock to obtain an impact envelope integral value, and correlating and integrating the impact envelope integral value with a local pseudo random sequence. Get the relevant integral value.
  • Step S1024 Perform a second threshold detection on the correlation integral value to obtain a second return-to-zero code. And adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code.
  • the step of adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code includes: determining whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1" ", then reset the symbol bit synchronization clock.
  • Step S1025 Perform sampling decision processing on the correlation integral value by using the symbol bit synchronization clock to obtain a sequence of information.
  • the present invention provides a receiver for implementing the method of FIG. 4. As shown in FIG. 5, the receiver performs EBPSK demodulation and decoding processing on an EBPSK modulated signal to obtain an information sequence.
  • the receiver specifically includes a demodulation module 31 and a decoding module 32.
  • the demodulation module 31 inputs the EBSK modulation signal to the digital impulse filter, and takes an absolute value of the signal output by the digital impulse filter, and then performs low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, the impact envelope integral value is obtained.
  • the demodulation module 31 determines whether the generated first return-to-zero code is "1", and if the generated first return-to-zero code is "1", according to the highest impact envelope and the first return-to-zero code The relative position relationship of the falling edge of "1", the delay amount of the impact envelope is obtained, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock and the impact packet The highest point of the network is aligned.
  • the decoding module 32 uses the chip bit synchronization clock to correlate and integrate the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral value; and perform a second threshold detection on the correlation integral value. Obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code; using the symbol-bit synchronization clock, performing a sampling decision process on the correlation integral value to obtain an information sequence. The decoding module 32 determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol-bit synchronization clock.
  • the EBPSK coded modulation based transmission method and fast bit synchronization side of the present invention The method and the corresponding receiving method, the expression of the EBPSK modulation data is:
  • the signal transmission method of the present invention is divided into coding and modulation.
  • the coding is to multiply the sequence to be transmitted and the output sequence of the PN code generator to generate a code sequence, which is called a chip; the modulation is obtained by applying a unit symbol period waveform expressed by the equation (1) at a given sampling rate.
  • the discrete waveform samples are pre-stored in the local memory, and then output a one-to-one correspondence with the discrete waveform samples according to the predetermined coding sequence, and corresponding waveform samples, such as symbols, are selected according to the sampling frequency provided by the clock generator under the control of the coding sequence. “0” corresponds to the f 0 (t) waveform sample, and the symbol “1” corresponds to the f 1 (t) waveform sample, and the selected waveform sample is converted into an analog signal, which is sent by the RF transmitter.
  • the receiver of the present invention adopts an open-loop structure.
  • the specific step of receiving is: taking the absolute value of the output of the digital impact filter and then low-pass filtering to obtain an envelope of the output signal:
  • the transmitting device of the present invention is composed of an encoder and a modulator; the receiving device is decoded by a demodulator and a delay detector, an integrator, a correlation integrator, a clock generator, a PN code generator and two threshold detectors. Composition.
  • the receiver replaces the traditional digital phase-locked loop synchronization with a new chip bit synchronization.
  • the new symbol bit synchronization replaces the traditional delay-locked loop PN code synchronization, and a digital impulse filter is provided as a demodulator.
  • the impulse filter is a special type of Infinite Impulse Response (IIR) narrowband digital bandpass filter consisting of a pair of conjugate zeros with very close resonant frequencies and at least two pairs of conjugate poles. Zero and pole components
  • IIR Infinite Impulse Response
  • the zero point frequency is lower than the carrier frequency of the input signal, and the zero point is located on the unit circle of the Z plane or as close as possible to the unit circle;
  • pole frequencies are all higher than the carrier frequency of the input signal, and the poles and poles are very close to exhibit the notch-frequency selection characteristic in the extremely narrow neighborhood of the filter center frequency;
  • the peak frequency of the filter is inconsistent with the carrier frequency of the EBPSK signal, and the offset is determined by the modulation degree ⁇ of the EBSK signal and the phase frequency characteristic of the filter.
  • FIG. 6 is a block diagram of a transmitter implementation of an EBPSK code modulation system according to an embodiment of the present invention
  • FIG. 7 is a flowchart of a transmitter operation of an EBPSK code modulation system according to an embodiment of the present invention, as shown in FIG. 6 and FIG.
  • the sequence to be transmitted is converted into a binary information sequence (ie, a source sequence), and a simple "1" "0" sequence is transmitted as shown in FIG. 13(a), and a corresponding PN code is generated at the local PN code generator.
  • PN code generally takes m sequence because it has approximate white noise characteristics And good autocorrelation performance, a length 7 PN code sequence is shown in Figure 13 (b), the period length is the same as the symbol period; then the multiplier will phase the information sequence with an integer multiple of the PN chip Multiply, complete the encoding process of the information sequence, the corresponding coding sequence is shown in Figure 13 (c), that is, the correlation value of the transmitted symbol and the PN code sequence; finally, the coding sequence is EBPSK modulated, and the corresponding baseband waveform is as shown in Figure 13 ( d), specifically, determining whether the chip is "1", if "1", selecting the f1 waveform sample corresponding to the chip "1", otherwise, selecting f0 corresponding to the chip "0" The waveform sample obtains a digital modulated signal; the digital modulated signal formed by the selected waveform sample is sent to the DAC for digital-to-analog conversion to obtain an analog modulated signal (ie, an analog EBPSK coded modulated signal
  • the EBPSK communication system is easy to implement in full digitalization: directly, the sampled values of the modulated waveforms f 0 (t) and f 1 (t) of one symbol period expressed by equation (1) are given in advance, given the sampling rate. It is stored in the memory, and then according to the clock frequency provided by the clock generator under the control of the information sequence to be transmitted, the corresponding waveform sample is selected (the information bit is “0”, then the f 0 (t) waveform sample is selected, and the information bit is “ 1” selects the f 1 (t) waveform sample), and the digital sample of the selected modulation waveform is directly converted into the analog EBPSK modulated signal output by a digital to analog converter (DAC, Digital to Analog Converter).
  • DAC Digital to Analog Converter
  • an extended binary phase shift keying (EBPSK) code modulated transmitter has a modulation expression of:
  • the transmitter is divided into two steps of encoding and modulation: the encoding is to multiply the information sequence by a pseudo-random (PN, Pseudo-Noise) code to obtain a coding sequence; the modulation is to give the unit symbol period waveform expressed by the above formula
  • PN pseudo-random
  • the discrete waveform samples obtained by the sampling rate are pre-stored in the local memory, and then output a one-to-one correspondence with the discrete waveform samples according to the predetermined coding sequence, and the corresponding waveform is selected according to the sampling frequency provided by the clock generator under the control of the coding sequence.
  • symbol “0” corresponds to f 0 (t) waveform samples
  • symbol “1” corresponds to f 1 (t) waveform samples
  • selected waveform samples are converted into analog signals by digital-to-analog converters, which are sent by RF transmitters. .
  • FIG. 8 is a block diagram of an EBPSK-based communication receiving end module according to an embodiment of the present invention.
  • the receiver is provided with a digital impulse filter as a demodulator.
  • the specific step of receiving is to take the absolute value of the output of the digital impulse filter and then pass through low-pass filtering to obtain an impact envelope:
  • the chip bit synchronization clock is reset, and the duration of the high level is measured by the delay calculator, according to the highest point of the impact envelope and the return edge of the return-to-zero code "1" Relative positional relationship, the delay amount of the impact envelope is obtained, otherwise the delay amount is assigned to 0, and the delay of the impact envelope is dynamically adjusted according to the obtained delay amount, so that the rising edge and the impact envelope of the chip bit synchronization clock Aligned at the highest point;
  • the threshold detector When the threshold detector has a return-to-zero code "1", the symbol-bit synchronization clock is reset, and a zero-threshold threshold sampling decision is taken under the guidance of the symbol-bit synchronization clock, that is, the received data sequence is demodulated.
  • variable delay is implemented by an addressable shift register.
  • the receiver of the present invention employs a super narrowband receiver based on a digital impulse filter.
  • the impact filter exhibits a class of excellent notch selection characteristics at the modulation center frequency, which can filter out the out-of-band noise of the received signal to the greatest extent, highlighting the difference between the symbols “0” and “1”, thus greatly improving The demodulation performance of EBPSK modulation.
  • Figure 9 is a typical EBPSK receiver in which a bit-synchronization implementation typically employs a digital phase-locked loop, such as a lead/lag gate synchronizer, which is similar to the conventional carrier-frequency-synchronized phase-locked loop method. Due to the feedback loop and the process of constant adjustment in the closed-loop method, it directly affects its error. Eliminate speed. Moreover, it is hoped that the promotion of the advantages of asymmetric modulation and the application will continue to simplify its hardware structure to meet the low-cost requirements for remote meter reading based on Power Line Communication (Smart Line Communication) in the smart grid, and the Internet of Things application for wireless Network Sensor (WSN: Wireless Sensor Network) node low power requirements.
  • Power Line Communication Smart Line Communication
  • WSN Wireless Sensor Network
  • the present invention proposes a complete hardware structure of the EBPSK coded modulation receiver as shown in FIGS. 10 and 11, including using the impact filter output signal for fast chip bit synchronization, and using the chip bit synchronization signal for fast code. Modules such as meta-synchronization.
  • the specific implementation of this embodiment is directed to an EBPSK modulated transmitter and a corresponding digital impulse filter based EBPSK receiver.
  • Figure 13 is an EBPSK encoded waveform, wherein: Figure 13(a) is a transmission symbol; Figure 13(b) is a PN code sequence; Figure 13(c) is a coding sequence; Figure 13(d) is an EBPSK corresponding to an EBPSK coding sequence.
  • Baseband waveform diagram. 14 is a time-domain waveform diagram of the EBPSK coded modulated signal before and after passing through the digital impulse filter, wherein: FIG. 14(a) is an EBPSK coded modulation waveform; and FIG. 14(b) is an output waveform of the digital impulse filter.
  • FIG. 16 is an effect diagram of demodulation and decoding of an EBPSK coded modulation waveform by the novel receiver proposed by the present invention, wherein: FIG. 16(a) is a time-delay-adjusted impact filter output envelope of an EBPSK coded modulation waveform; FIG. (b) a delay of half a chip period for synchronizing chip bits as a new bit synchronization signal; FIG. 16(c) is an integral value of an output envelope in a chip period, taking a threshold value as a relative zero point; 16(d) is the output value of the associated integrator of FIG. 12; FIG. 16(e) is a schematic diagram of the reset symbol bit; FIG. 16(f) is the output symbol of the demodulated decoding; The coordinates are time.
  • the impact filter as a core component is a narrowband bandpass filter that exhibits a very narrow notch selection characteristic at the center frequency in the passband, enabling asymmetric binary keying represented by EBPSK modulation.
  • the filtered output waveform of the signal produces a strong parasitic amplitude-modulated impact at the modulation of the symbol "1", ie at the phase transition.
  • the transfer function of a digital impulse filter with a single zero-point three pole is as follows:
  • the impact filter has a notch-frequency selection characteristic for the EBPSK modulated signal, and converts the phase jump of the modulated waveform into a strong parasitic amplitude modulation.
  • a single zero-point three-pole filter scheme is adopted as the demodulation filter.
  • the transfer function and the coefficients of the filter are as shown in equation (2).
  • the sampling frequency of the ADC is 100MHz, that is, 10 points per carrier cycle:
  • the digital impulse filter can be implemented with a multiplier and a shift register, and is generally cascaded.
  • a typical EBPSK modulation receiver is shown in Figure 9.
  • the EBPSK modulated signal received by the antenna is subjected to a preamplifier and then subjected to a mixer, downconverted to an intermediate frequency and amplified by an intermediate frequency to be converted into a digital digital signal by the ADC;
  • the mixer realizes carrier synchronization through the analog phase-locked loop;
  • the basic reference crystal is provided by the phase-locked loop, and is sent to the clock generator to provide the system clock and the sampling pulse for each function module of the EBPSK demodulator, that is, the sampling of the receiver is realized. Synchronization; bit synchronization is also required for the demodulation decision result of the EBPSK signal.
  • the implementation block diagram is shown in Figure 10.
  • the threshold envelope is used to shape the impact envelope to obtain a return-to-zero code as shown in Fig. 15(b).
  • the detection threshold can be directly set to a fixed value or automatically adjusted.
  • There are many ways to implement the adaptive threshold Generally, the arithmetic mean value of the peak of the impact envelope and its reference level value shown in Figure 15(a) can be taken. For convenience, the threshold is taken as 60;
  • the return-to-zero code is sent to the clock generator and the variable delay unit, respectively.
  • the return to zero code "1" appears:
  • This example uses an addressable shift register to implement a variable delay.
  • the address of the shift register is the delay amount of the impact envelope.
  • the output of the shift register is the content of the register pointed to by the address.
  • the chip bit synchronization signal is delayed by half a chip period (this example uses a shift register) as a bit synchronization signal of the chip integration value, as shown in FIG. 16 ( b) shown.
  • this example uses a shift register
  • the integral value is sent to the correlation integrator shown in Fig. 9, and the integrated integral is integrated with the chip integral value and the local PN code, and the output is as shown in Fig. 16(d);
  • the output value of the relevant integrator is absolutely worth its size, and is sent to the entry limit detector for shaping.
  • the symbol bit synchronization clock is reset, so that the rising edge of the symbol bit synchronization clock Align with the falling edge of the return-to-zero code, as shown in Figure 16(e), where the threshold is taken as 2000;
  • the delay amount dynamically adjusts the delay of the impact envelope, so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope; at the rising edge of the chip bit synchronization pulse, the impact envelope is integrated to obtain an integral output.
  • the chip bit sync pulse is delayed by half a chip period as a new clock, the integral output is guided to correlate and integrate with the local PN code, and the correlation value is threshold-detected, and the return is determined according to the given threshold value.
  • Figure 19 is an anti-interference performance curve of an uncoded EBPSK communication system.
  • the interference signal takes the BPSK modulation signal, and the code rate is the same as the EBPSK signal.
  • Figure 20 is an anti-interference performance curve of an EBPSK coded modulation communication system.
  • the coding length can be flexibly set, especially suitable for working in a bad channel environment. in.
  • the present invention has the following technical effects:
  • the transmitter of the invention adopts EBPSK-based code modulation, and the receiver fully utilizes the output signal of the modulated signal through the digital impulse filter to generate strong parasitic amplitude modulation at the information modulation of the data "1", and the structure does not require a phase-locked loop and a complicated structure.
  • the fast demodulation and decoding method of the pseudo-code synchronization structure can end the transition process in a few digital elements, realize accurate chip bit synchronization and symbol bit synchronization, which makes the EBPSK receiver fully digitalized and greatly simplifies EBPSK demodulation.
  • Decoder hard
  • the structure is suitable for high-efficiency digital communication systems based on asymmetric binary offset keying code modulation, especially for fast demodulation and decoding of bad channels.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the steps of the foregoing method embodiments are included; and the foregoing storage medium includes: a mobile storage device, a read only memory (ROM, Read-Only Memory), random access memory (RAM), disk or optical disk, and other media that can store program code.

Abstract

La présente invention concerne un procédé et un système de communication basée sur EBPSK, qui se rapportent au domaine des communications numériques. Le procédé comprend les opérations suivantes : une extrémité de transmission réalise un codage et une modulation EBPSK pour une séquence d'informations afin d'obtenir un signal de modulation EBPSK; et une extrémité de réception réalise une démodulation EBPSK et un décodage pour le signal de modulation EBPSK afin d'obtenir la séquence d'informations. La présente invention peut améliorer la capacité anti-brouillage du système de communication EBPSK.
PCT/CN2015/077852 2014-05-23 2015-04-29 Procédé et système de communication basée sur ebpsk WO2015176597A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410221951.1 2014-05-23
CN201410221951.1A CN105099977A (zh) 2014-05-23 2014-05-23 一种基于ebpsk的通信方法及系统

Publications (1)

Publication Number Publication Date
WO2015176597A1 true WO2015176597A1 (fr) 2015-11-26

Family

ID=54553402

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/077852 WO2015176597A1 (fr) 2014-05-23 2015-04-29 Procédé et système de communication basée sur ebpsk

Country Status (2)

Country Link
CN (1) CN105099977A (fr)
WO (1) WO2015176597A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115037431A (zh) * 2022-06-03 2022-09-09 深圳市纽瑞芯科技有限公司 一种二进制数字调制中的码元同步方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105681240B (zh) * 2015-12-25 2020-12-22 上海物联网有限公司 一种适应于低信噪比环境下的高精度频偏估计方法
CN105915482B (zh) * 2016-04-08 2018-12-28 东南大学 一种基于扩展二元相移键控传输系统的多径分离方法
CN109391574B (zh) * 2017-08-04 2021-05-04 深圳市中兴微电子技术有限公司 一种基于ebpsk的调制解调方法及通信系统
CN115208730B (zh) * 2022-06-30 2023-08-18 南京工程学院 一种对码元信号进行临频差分调制解调的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101895387A (zh) * 2010-07-15 2010-11-24 东南大学 扩展的二元相移键控调制突发通信快速同步方法
CN102684744A (zh) * 2012-05-18 2012-09-19 苏州东奇信息科技有限公司 用于电力线通信的电源自同步反相调制解调器
CN102904849A (zh) * 2011-07-25 2013-01-30 苏州东奇信息科技有限公司 利用瞬态峰值能量的猝发通信系统

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103501211A (zh) * 2013-10-08 2014-01-08 苏州东奇信息科技股份有限公司 一种兼容中波模拟调幅广播的复合调制系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101895387A (zh) * 2010-07-15 2010-11-24 东南大学 扩展的二元相移键控调制突发通信快速同步方法
CN102904849A (zh) * 2011-07-25 2013-01-30 苏州东奇信息科技有限公司 利用瞬态峰值能量的猝发通信系统
CN102684744A (zh) * 2012-05-18 2012-09-19 苏州东奇信息科技有限公司 用于电力线通信的电源自同步反相调制解调器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115037431A (zh) * 2022-06-03 2022-09-09 深圳市纽瑞芯科技有限公司 一种二进制数字调制中的码元同步方法
CN115037431B (zh) * 2022-06-03 2023-07-21 深圳市纽瑞芯科技有限公司 一种二进制数字调制中的码元同步方法

Also Published As

Publication number Publication date
CN105099977A (zh) 2015-11-25

Similar Documents

Publication Publication Date Title
US6064695A (en) Spread spectrum communication system utilizing differential code shift keying
CN108234376B (zh) 无线数据通信方法及装置
WO2015176597A1 (fr) Procédé et système de communication basée sur ebpsk
US10728853B2 (en) Wake up radio frame with spectrum spreading based single carrier
CN101262467B (zh) 数字基带跳频调制系统实现方法及实现装置
CN107769816B (zh) 一种Chirp扩频通信系统接收机时间同步系统及方法
CN101895387B (zh) 扩展的二元相移键控调制突发通信快速同步方法
US7796686B2 (en) Adaptive ultrawideband receiver and method of use
EA031912B1 (ru) Комбинированная амплитудно-временная и фазовая модуляция
WO2011035493A1 (fr) Procédé de communication sans fil pulsée en bande ultra-large avec échantillonnage à grande vitesse et quantification à basse précision
WO2001093444A1 (fr) Systeme de bande ultralarge et procede de synchronisation rapide
US6671311B1 (en) Receiver for use in a code shift keying spread spectrum communications system
US6616254B1 (en) Code shift keying transmitter for use in a spread spectrum communications system
CN102075472A (zh) 一种扩频oqpsk中频及解扩解调方法
JP2004260774A (ja) 移動通信システムにおける伝搬路推定方法
US20050111569A1 (en) Data code transmission device
CN112653642A (zh) 基于ebpsk调制峰值能量猝发通信实现方法
JP4557486B2 (ja) 差分符号シフトキーイングを利用するスペクトラム拡散通信システム
US20050249264A1 (en) Wireless communication system, wireless transmitter, wireless receiver, wireless communication method, wireless transmission method and wireless reception method
KR100534592B1 (ko) 디지털 통신 시스템의 수신 장치 및 그 방법
CN109428679B (zh) ZigBee自适应多速率传输方法
CN114039623B (zh) 一种低载噪比的短突发扩频信号跟踪方法
CN110049545B (zh) G比特量级宽带接收信号的同步方法
JPH08331098A (ja) Ｐｄｉ受信機
CN113904905A (zh) 一种动态直扩gmsk信号的捕获装置及方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15795466

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15795466

Country of ref document: EP

Kind code of ref document: A1