WO2015176597A1 - Ebpsk-based communication method and system - Google Patents

Abstract

An EBPSK-based communication method and system are disclosed in the present invention, relating to the field of digital communications. The method includes: a transmitting end performs encoding and EBPSK modulation for an information sequence to obtain an EBPSK modulation signal; and a receiving end performs EBPSK demodulation and decoding for the EBPSK modulation signal to obtain the information sequence. The present invention can enhance the anti-interference ability of the EBPSK communication system.

Description

EBPSK-based communication method and system Technical field

The present invention relates to a digital communication system, and more particularly to a transmitter for extended Binary Phase Shift Keying (EBPSK) coded modulation communication and a corresponding fast bit synchronization and demodulation decoding method, belonging to a digital The field of information modulation and demodulation in communications.

Background technique

1, EBPSK modulation

In a digital communication system, a process of moving a baseband signal representing a transmitted data to a desired transmission band is called modulation, and vice versa. For binary digital modulation, a binary data symbol "0" "1" can be used to change a certain parameter of the sinusoidal carrier in the symbol period, such as amplitude, frequency or phase, to obtain corresponding amplitude keying (2ASK), frequency. Shift keying (2FSK) and phase shift keying (2PSK) modulation. If the modulation period t < T, an asymmetrical binary offset keying modulation is obtained. A typical asymmetric binary phase shift keying modulation, called EBPSK, has a uniform expression:

f ₀ (t)=Asin2πf _c t, 0≤t<T

Where f ₀ (t) and f ₁ (t) represent modulation waveforms of symbols "0" and "1", respectively. f _c denotes the modulation carrier frequency, A, B is the amplitude of the carrier keying, the symbol period is T=N/f _c , and N is the ratio of the symbol period to the carrier period, that is, the number of carrier periods in one symbol; The hop duration is τ=K/f _c , K(K<N) is the number of hopping carrier periods in the symbol period, and θ is the hopping angle. N and K are integers to guarantee the modulation of the whole period, and τ/T=K/N is called the modulation duty ratio.

2. Spread spectrum and channel coding

Spread spectrum is to modulate signal information with signal-independent spreading symbols and to modulate The signal is spread into a frequency band that is much larger than the minimum bandwidth required for the original signal, and despread at the receiving end with the same spreading symbol to recover the original signal. Spread spectrum communication greatly expands the bandwidth required to transmit information. According to Shannon's formula, bandwidth can be exchanged for signal-to-noise ratio to make the system work in a more severe channel environment. The receiving end needs the PN code synchronization module for despreading. The traditional synchronous implementation is divided into two modules: PN code acquisition and PN code tracking.

Pseudo code capture generally uses a matched filter. The choice of matched filter number is a compromise between capture time and system complexity. The more the number, the shorter the capture time, but the higher the complexity. Pseudo-code tracking is transferred to pseudo-code tracking. Pseudo-code tracking generally uses a delay-locked loop. Due to the feedback and constant adjustment process of the closed-loop pseudo-code tracking structure, it will directly affect its speed of error elimination.

Channel coding is to add redundant symbols at the transmitting end to protect data during data transmission and to perform error detection and error correction at the receiving end. Currently mature channel coding has a block code, a convolutional code, and the like.

Both of the above communication technologies sacrifice bandwidth or code rate to improve the anti-interference performance of the communication system.

3, bit synchronization technology

The existing bit synchronization techniques can generally be divided into two major categories, the external synchronization method and the self-synchronization method.

The external synchronization method is a method for synchronizing auxiliary information, and a pilot or data sequence containing symbol timing information is additionally added to the signal to achieve the purpose of extracting bit synchronization information. The advantage of this method is that the device is relatively simple, but The disadvantages are also obvious, requiring a certain frequency band and transmission power. At present, there are not many external synchronization methods used in digital communication systems.

The self-synchronization method usually adopts a closed-loop bit synchronization method, which is characterized in that the received signal is compared with a locally generated symbol timing signal to keep the locally generated timing signal and the transition point of the received symbol waveform synchronized, and a widely used research method The closed loop synchronizer is called the lead/lag gate synchronizer. This method is similar to the traditional phase-locked loop method of carrier frequency synchronization. Due to the feedback link and the continuous adjustment process in the closed-loop method, it will directly affect its speed of elimination.

Summary of the invention

The object of the present invention is to provide an EBPSK-based communication method and system for the special asymmetric modulation mode of EBPSK modulation, which aims to solve the anti-interference performance of the simple EBPSK modulation system, and can combine EBPSK modulation. The advantages and features of the system enhance the anti-jamming capability of the EBPSK communication system.

According to an aspect of the present invention, an EBPSK-based communication method is provided, including:

The transmitting end encodes the information sequence and performs EBPSK modulation processing to obtain an EBPSK modulated signal;

The receiving end performs EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.

Preferably, the transmitting end encodes and modulates the information sequence, and the step of obtaining the EBPSK modulated signal specifically includes:

The transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and saves;

Encoding the information sequence to obtain a coding sequence;

Corresponding f0 waveform samples and f1 waveform samples are selected for each symbol in the coding sequence to obtain an EBPSK modulated signal.

Preferably, the step of encoding the information sequence to obtain the coding sequence comprises:

Multiplying the information sequence by the pseudo-random sequence to obtain a coding sequence.

Preferably, the receiving end performs demodulation and decoding processing on the EBPSK modulated signal, and the step of obtaining the information sequence includes:

Inputting the EBSK modulation signal to the digital impulse filter, and taking an absolute value of the signal output by the digital impulse filter, and performing low-pass filtering processing to obtain an impact envelope of the output signal;

Performing a first threshold detection on the impact envelope of the output signal, obtaining a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code;

Using the chip bit synchronization clock, integrating the impact envelope to obtain an impact envelope integral value, and correlating and integrating the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral. value;

Performing a second threshold detection on the correlation integral value, obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code;

Using the symbol bit synchronization clock, the correlation integral value is subjected to sampling decision processing to obtain a sequence of information.

Preferably, the step of determining a chip bit synchronization clock according to the obtained first return-to-zero code comprises:

Determining whether the generated first return-to-zero code is "1";

If the generated first return-to-zero code is "1", the delay amount of the impact envelope is obtained according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1";

According to the obtained delay amount, the delay of the impact envelope is adjusted so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.

Preferably, the step of adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code comprises:

Determining whether the generated second return-to-zero code is "1";

If the generated second return code is "1", the symbol bit synchronization clock is reset.

According to another aspect of the present invention, an EBPSK-based code modulation method is provided, including:

The transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and saves;

Encoding the information sequence to obtain a coding sequence;

Corresponding f0 waveform samples and f1 waveform samples are selected for each symbol in the coding sequence to obtain an EBPSK modulated signal.

Preferably, the step of encoding the information sequence to obtain the coding sequence comprises:

Multiplying the information sequence by the pseudo-random sequence to obtain a coding sequence.

According to another aspect of the present invention, an EBPSK-based decoding and demodulation method is provided, including:

Inputting the EBPSK modulation signal to the digital impulse filter, and taking an absolute value of the signal output by the digital impulse filter, and performing low-pass filtering processing to obtain an impact envelope of the output signal;

Performing a first threshold detection on the impact envelope of the output signal, obtaining a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code;

Using the chip bit synchronization clock, integrating the impact envelope to obtain an impact envelope integral value, and correlating and integrating the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral. value;

Performing a second threshold detection on the correlation integral value, obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code;

Using the symbol bit synchronization clock, the correlation integral value is subjected to sampling decision processing to obtain a sequence of information.

Preferably, the step of determining a chip bit synchronization clock according to the obtained first return-to-zero code comprises:

Determining whether the generated first return-to-zero code is "1";

If the generated first return-to-zero code is "1", the delay amount of the impact envelope is obtained according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1";

According to the obtained delay amount, the delay of the impact envelope is adjusted so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.

Preferably, the step of adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code comprises:

Determining whether the generated second return-to-zero code is "1";

If the generated second return code is "1", the symbol bit synchronization clock is reset.

According to another aspect of the present invention, an EBPSK based communication system is provided, comprising a transmitter and a receiver, wherein:

The transmitter is configured to perform coding and EBPSK modulation processing on the information sequence to obtain an extended binary phase shift keying EBPSK modulated signal;

The receiver is configured to perform EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.

Preferably, the transmitter specifically includes:

a sampling module, configured to discretize EBPSK modulated waveforms f0 and f1 respectively corresponding to symbols 0 and 1, to obtain f0 waveform samples and f1 waveform samples and save;

An encoding module, configured to encode the information sequence to obtain a coding sequence;

And a modulation module, configured to select a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.

Advantageously, said encoding module obtains a coded sequence by multiplying said sequence of information with said pseudo-random sequence.

Preferably, the receiver comprises:

a demodulation module, configured to input an EBPSK modulation signal to the digital impulse filter, and perform an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, obtaining an impact envelope integral value;

a decoding module, configured to perform correlation and integration processing on the integrated value of the impact envelope and the local pseudo-random sequence by using the chip bit synchronization clock to obtain a correlation integral value; and performing a second threshold detection on the correlation integral value Obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code; using the symbol-bit synchronous clock to sample the relevant integral value The decision is processed to obtain a sequence of information.

Preferably, the demodulation module determines whether the generated first return-to-zero code is "1", and if the generated first return-to-zero code is "1", according to the highest point of the impact envelope and the first return-to-zero code The relative position relationship of the falling edge of "1", the delay amount of the impact envelope is obtained, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock and the impact packet The highest point of the network is aligned.

Preferably, the decoding module determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol bit synchronization clock.

According to another aspect of the present invention, an EBPSK-based transmitter is provided, comprising:

a sampling module, configured to discretize EBPSK modulated waveforms f0 and f1 respectively corresponding to symbols 0 and 1, to obtain f0 waveform samples and f1 waveform samples and save;

An encoding module, configured to encode the information sequence to obtain a coding sequence;

And a modulation module, configured to select a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.

Preferably, the sampling module obtains a coding sequence by multiplying the information sequence with the pseudo random sequence.

According to another aspect of the present invention, an EBPSK-based receiver is provided, comprising:

a demodulation module, configured to input an EBSK modulation signal to the digital impulse filter, and perform an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, obtaining an impact envelope integral value;

a decoding module, configured to perform correlation and integration processing on the integrated value of the impact envelope and the local pseudo-random sequence by using the chip bit synchronization clock to obtain a correlation integral value; and performing a second threshold detection on the correlation integral value , obtaining a second return-to-zero code, and according to the obtained second return-to-zero code, Adjusting the symbol bit synchronization clock; using the symbol bit synchronization clock, performing sampling decision processing on the correlation integral value to obtain an information sequence.

Preferably, the demodulation module determines whether the generated first return-to-zero code is "1", and if the generated first return-to-zero code is "1", according to the highest point of the impact envelope and the first return-to-zero code The relative position relationship of the falling edge of "1", the delay amount of the impact envelope is obtained, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock and the impact packet The highest point of the network is aligned.

Preferably, the decoding module determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol bit synchronization clock.

Compared with the prior art, the beneficial effects of the present invention are:

1) Accurate and fast. Since the relative positional relationship between the highest point of the impact envelope and the falling edge of the return-to-zero code "1" is fully utilized, accurate chip bit synchronization is achieved; the open-loop control structure of the method is more than the bit-synchronous structure of the closed-loop control. Fast, more cost-effective for fast communication of small packets. Statistically speaking, chip bit synchronization can be realized in two chip periods, and symbol bit synchronization can be realized in two symbol periods, because the occurrence of symbol “0” “1” in the communication system is equal probability. .

2) Strong anti-interference ability. Due to the large amount of noise and interference in the actual communication channel, the amplitude and duration of the envelope are not stable. However, the relative positional relationship between the highest point of the impact envelope and the falling edge of the return-to-zero code "1" is relatively stable. This relative relationship hardly changes much with the size of the code rate or threshold, so the fast bit synchronization algorithm of the chip has strong anti-interference performance.

3) The receiver is simpler. The receiver of the present invention adopts an open loop system, which replaces the classical digital phase-locked loop bit synchronization and delay phase-locked loop PN code synchronization system, which greatly simplifies the structure of the receiver. Moreover, since the transmitter adopts the "1+1" structure, that is, the encoder and the modulator, the implementation of the receiver is also simpler while improving the anti-interference performance of the system, and the effect of "1+1>2" is achieved.

4) The receiver can be fully digitally integrated and at a lower cost. The demodulator and decoder circuit structures of the EBPSK coded modulated signals shown in Fig. 6 and Fig. 7 respectively can be seen. Not only the demodulator and the decoder can be digitally integrated, but the whole receiver can be fully digitally integrated from below the intermediate frequency, and the structure is easier. Realized, the cost is lower.

5) The performance of the system is more obvious for narrowband interference channels, and the coding length can be flexibly set. It is especially suitable for working in a harsh channel environment, and the spectrum is not much different from the unencoded EBPSK communication system. It is a normalized magnitude that increases slightly.

DRAWINGS

1 is a schematic block diagram of an EBPSK-based communication method provided by the present invention;

2 is a schematic block diagram of an EBPSK-based code modulation method provided by the present invention;

3 is a schematic block diagram of an EBPSK-based transmitter provided by the present invention;

4 is a schematic block diagram of an EBPSK-based demodulation and decoding method provided by the present invention;

5 is a schematic block diagram of an EBPSK-based receiver provided by the present invention;

6 is a block diagram of a transmitter implementation according to an embodiment of the present invention;

7 is a flowchart of a transmitter operation according to an embodiment of the present invention;

8 is a block diagram of an EBPSK-based communication receiving end module according to an embodiment of the present invention;

Figure 9 is a general block diagram of a conventional EBPSK modulated receiver;

10 is a block diagram of an implementation of digital demodulation of a receiver of an EBPSK coded modulation system according to an embodiment of the present invention, which is characterized in that an analog phase locked loop and a digital phase locked loop are removed;

11 is a block diagram of an implementation of digital decoding of a receiver of an EBPSK coded modulation system according to an embodiment of the present invention, wherein the correlation integrator is generally implemented by a series matched filter;

FIG. 12 is a flowchart showing the operation of a receiver of an EBPSK code modulation system according to an embodiment of the present invention; FIG.

Figure 13 is an EBPSK encoded waveform;

Figure 14 is a time-domain waveform diagram of the EBPSK coded modulated signal before and after passing through the digital impulse filter;

Figure 15 is a relative positional relationship diagram of the falling edge of the highest value of the impact envelope of the EBPSK modulation coefficient and the return-to-zero code "1";

16 is an effect diagram of demodulating and decoding an EBPSK coded modulation waveform by the novel receiver proposed by the present invention;

Figure 17 is an EBPSK modulated power spectrum estimate;

Figure 18 is an EBPSK coded modulation power spectrum estimate;

Figure 19 is an anti-interference performance curve of an uncoded EBPSK communication system;

Figure 20 is an anti-interference performance curve of an EBPSK coded modulation communication system.

detailed description

The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

1 is a schematic block diagram of an EBPSK-based communication method according to an embodiment of the present invention. As shown in FIG. 1, the steps include:

Step S101: The transmitting end encodes the information sequence and EBPSK modulation processing to obtain an extended binary phase shift keying EBPSK modulated signal.

Specifically, the transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and stores them; and encodes the information sequence to obtain a coding sequence, specifically The coding sequence is obtained by multiplying the information sequence with the pseudo-random sequence; selecting corresponding f0 waveform samples and f1 waveform samples for each symbol in the coding sequence to obtain an EBPSK modulated signal.

Step S102: The receiving end performs EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.

Specifically, the EBSK modulation signal is input to the digital impulse filter, and the signal outputted by the digital impulse filter is subjected to a low-pass filtering process to obtain an impact envelope of the output signal; Performing the first threshold detection to obtain the first return-to-zero code, and Determining, according to the obtained first return-to-zero code, a chip bit synchronization clock; using the chip bit synchronization clock, performing integral processing on the impact envelope to obtain an impact envelope integral value, and using the impact envelope The integral value is correlated and integrated with the local pseudo-random sequence to obtain a correlation integral value; the second threshold detection is performed on the correlation integral value to obtain a second return-to-zero code, and adjusted according to the obtained second return-to-zero code A symbol bit synchronization clock; using the symbol bit synchronization clock, performing a sampling decision process on the correlation integral value to obtain an information sequence. Wherein, the receiving end determines whether the first return-to-zero code generated is “1”, and if the generated first return-to-zero code is “1”, then the highest point of the impact envelope and the first return-to-zero code “1” are decreased. The relative position relationship of the edge obtains the delay amount of the impact envelope, otherwise the delay amount is zero; according to the obtained delay amount, the delay of the impact envelope is adjusted to make the rising edge of the chip bit synchronous clock and The highest point of the impact envelope is aligned. The receiving end determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol-bit synchronous clock.

The present invention also provides a communication system that implements the method of Figure 1, comprising a transmitter and a receiver. The transmitter is configured to encode the information sequence and EBPSK modulation processing to obtain an extended binary phase shift keying EBPSK modulated signal, which includes each module shown in FIG. The receiver is configured to perform EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence, which includes the modules shown in FIG.

2 is a schematic block diagram of an EBPSK-based code modulation method provided by the present invention. As shown in FIG. 2, the steps include:

Step S1011: The transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, to obtain the f0 waveform sample and the f1 waveform sample and save.

Step S1012: Encoding the information sequence to obtain a coding sequence, specifically, obtaining a coding sequence by multiplying the information sequence by the pseudo random sequence.

Step S1013: Select corresponding f0 waveform samples and f1 waveform samples for each symbol in the coding sequence to obtain an EBPSK modulated signal.

The present invention provides a transmitter for implementing the method of FIG. 2, as shown in FIG. The radiographer encodes the information sequence (ie, the source sequence) and EBPSK modulation to obtain an EBPSK modulated signal. The transmitter specifically includes: a module 21, an encoding module 22, and a modulation module 23.

The sampling module 21 discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, to obtain the f0 waveform samples and the f1 waveform samples and save them.

The encoding module 22 encodes the information sequence to obtain a coding sequence, specifically, by multiplying the information sequence by the pseudo random sequence to obtain a coding sequence.

The modulation module 23 selects a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.

4 is a schematic block diagram of an EBPSK-based demodulation and decoding method provided by the present invention. As shown in FIG. 4, the steps include:

Step S1021: Input the EBPSK modulation signal to the digital impulse filter, and take an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal.

Step S1022: Perform a first threshold detection on the impact envelope of the output signal to obtain a first return-to-zero code, and determine a chip bit synchronization clock according to the obtained first return-to-zero code.

The step of determining the chip bit synchronization clock according to the obtained first return-to-zero code includes: determining whether the generated first return-to-zero code is “1”, and if the generated first return-to-zero code is “1” Then, according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1", the delay amount of the impact envelope is obtained, and the impact package is adjusted according to the obtained delay amount. The delay of the network is such that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.

Step S1023: Integrating the impact envelope with the chip bit synchronization clock to obtain an impact envelope integral value, and correlating and integrating the impact envelope integral value with a local pseudo random sequence. Get the relevant integral value.

Step S1024: Perform a second threshold detection on the correlation integral value to obtain a second return-to-zero code. And adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code.

The step of adjusting the symbol bit synchronization clock according to the obtained second return-to-zero code includes: determining whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1" ", then reset the symbol bit synchronization clock.

Step S1025: Perform sampling decision processing on the correlation integral value by using the symbol bit synchronization clock to obtain a sequence of information.

The present invention provides a receiver for implementing the method of FIG. 4. As shown in FIG. 5, the receiver performs EBPSK demodulation and decoding processing on an EBPSK modulated signal to obtain an information sequence. The receiver specifically includes a demodulation module 31 and a decoding module 32.

The demodulation module 31 inputs the EBSK modulation signal to the digital impulse filter, and takes an absolute value of the signal output by the digital impulse filter, and then performs low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, the impact envelope integral value is obtained. The demodulation module 31 determines whether the generated first return-to-zero code is "1", and if the generated first return-to-zero code is "1", according to the highest impact envelope and the first return-to-zero code The relative position relationship of the falling edge of "1", the delay amount of the impact envelope is obtained, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock and the impact packet The highest point of the network is aligned.

The decoding module 32 uses the chip bit synchronization clock to correlate and integrate the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral value; and perform a second threshold detection on the correlation integral value. Obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code; using the symbol-bit synchronization clock, performing a sampling decision process on the correlation integral value to obtain an information sequence. The decoding module 32 determines whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", resets the symbol-bit synchronization clock.

In summary, the EBPSK coded modulation based transmission method and fast bit synchronization side of the present invention The method and the corresponding receiving method, the expression of the EBPSK modulation data is:

f ₀ (t)=Asin2πf _c t, 0≤t<T

The signal transmission method of the present invention is divided into coding and modulation. The coding is to multiply the sequence to be transmitted and the output sequence of the PN code generator to generate a code sequence, which is called a chip; the modulation is obtained by applying a unit symbol period waveform expressed by the equation (1) at a given sampling rate. The discrete waveform samples are pre-stored in the local memory, and then output a one-to-one correspondence with the discrete waveform samples according to the predetermined coding sequence, and corresponding waveform samples, such as symbols, are selected according to the sampling frequency provided by the clock generator under the control of the coding sequence. “0” corresponds to the f ₀ (t) waveform sample, and the symbol “1” corresponds to the f ₁ (t) waveform sample, and the selected waveform sample is converted into an analog signal, which is sent by the RF transmitter.

Since the transmitter adopts PN code coding and EBPSK modulation, the correct demodulation and decoding of the receiver needs to complete two synchronizations, and chip bit synchronization and symbol bit synchronization. Considering that any closed-loop system has a feedback link and a continuously adjusted process, which directly affects the speed of error cancellation, the receiver of the present invention adopts an open-loop structure. The specific step of receiving is: taking the absolute value of the output of the digital impact filter and then low-pass filtering to obtain an envelope of the output signal:

1) performing threshold detection on the envelope of the output signal to obtain a corresponding return-to-zero code;

2) When the return-to-zero code "1" appears, reset the chip bit synchronization clock, and according to the duration of the high level and the relative positional relationship between the highest point of the impact envelope and the falling edge of the return-to-zero code "1", The delay is calculated to obtain the delay amount, and the delay amount is maintained until the arrival of the next return-to-zero code "1"; the delay of the impact envelope is dynamically adjusted according to the delay amount, so that the rising edge of the chip-bit synchronous clock and the impact envelope are Align at the highest point;

3) At the rising edge of the chip bit sync pulse, integrate the impact envelope to obtain the integral output; delay the chip bit sync pulse by half a chip period as a new clock, and guide the integral output to correlate with the local PN code. And integral, and the threshold value of the relevant integral value is detected, and the return-to-zero code is determined according to the given threshold value;

4) When the threshold detection output exhibits a return-to-zero code of "1", the correlation peak is captured, the symbol-bit synchronization clock is reset, and a zero-threshold threshold sampling decision is taken under the guidance of the symbol-bit synchronization clock, that is, the demodulation is received. The sequence of data.

The transmitting device of the present invention is composed of an encoder and a modulator; the receiving device is decoded by a demodulator and a delay detector, an integrator, a correlation integrator, a clock generator, a PN code generator and two threshold detectors. Composition.

The receiver replaces the traditional digital phase-locked loop synchronization with a new chip bit synchronization. The new symbol bit synchronization replaces the traditional delay-locked loop PN code synchronization, and a digital impulse filter is provided as a demodulator. The impulse filter is a special type of Infinite Impulse Response (IIR) narrowband digital bandpass filter consisting of a pair of conjugate zeros with very close resonant frequencies and at least two pairs of conjugate poles. Zero and pole components The principles are as follows:

1) The zero point frequency is lower than the carrier frequency of the input signal, and the zero point is located on the unit circle of the Z plane or as close as possible to the unit circle;

2) The pole frequencies are all higher than the carrier frequency of the input signal, and the poles and poles are very close to exhibit the notch-frequency selection characteristic in the extremely narrow neighborhood of the filter center frequency;

3) The more poles, the greater the impact energy, but the inter-symbol interference also increases, so the poles are not as good as possible, and the phase angles of multiple poles are kept as similar as possible;

4) The peak frequency of the filter is inconsistent with the carrier frequency of the EBPSK signal, and the offset is determined by the modulation degree θ of the EBSK signal and the phase frequency characteristic of the filter.

The present invention will be further described below in conjunction with FIGS. 6 to 20.

6 is a block diagram of a transmitter implementation of an EBPSK code modulation system according to an embodiment of the present invention, and FIG. 7 is a flowchart of a transmitter operation of an EBPSK code modulation system according to an embodiment of the present invention, as shown in FIG. 6 and FIG. The sequence to be transmitted is converted into a binary information sequence (ie, a source sequence), and a simple "1" "0" sequence is transmitted as shown in FIG. 13(a), and a corresponding PN code is generated at the local PN code generator. Sequence, PN code generally takes m sequence because it has approximate white noise characteristics And good autocorrelation performance, a length 7 PN code sequence is shown in Figure 13 (b), the period length is the same as the symbol period; then the multiplier will phase the information sequence with an integer multiple of the PN chip Multiply, complete the encoding process of the information sequence, the corresponding coding sequence is shown in Figure 13 (c), that is, the correlation value of the transmitted symbol and the PN code sequence; finally, the coding sequence is EBPSK modulated, and the corresponding baseband waveform is as shown in Figure 13 ( d), specifically, determining whether the chip is "1", if "1", selecting the f1 waveform sample corresponding to the chip "1", otherwise, selecting f0 corresponding to the chip "0" The waveform sample obtains a digital modulated signal; the digital modulated signal formed by the selected waveform sample is sent to the DAC for digital-to-analog conversion to obtain an analog modulated signal (ie, an analog EBPSK coded modulated signal) and transmitted.

The EBPSK communication system is easy to implement in full digitalization: directly, the sampled values of the modulated waveforms f ₀ (t) and f ₁ (t) of one symbol period expressed by equation (1) are given in advance, given the sampling rate. It is stored in the memory, and then according to the clock frequency provided by the clock generator under the control of the information sequence to be transmitted, the corresponding waveform sample is selected (the information bit is “0”, then the f ₀ (t) waveform sample is selected, and the information bit is “ 1" selects the f ₁ (t) waveform sample), and the digital sample of the selected modulation waveform is directly converted into the analog EBPSK modulated signal output by a digital to analog converter (DAC, Digital to Analog Converter).

Specifically, an extended binary phase shift keying (EBPSK) code modulated transmitter has a modulation expression of:

f ₀ (t)=Asin2πf _c t, 0≤t<T

The transmitter is divided into two steps of encoding and modulation: the encoding is to multiply the information sequence by a pseudo-random (PN, Pseudo-Noise) code to obtain a coding sequence; the modulation is to give the unit symbol period waveform expressed by the above formula The discrete waveform samples obtained by the sampling rate are pre-stored in the local memory, and then output a one-to-one correspondence with the discrete waveform samples according to the predetermined coding sequence, and the corresponding waveform is selected according to the sampling frequency provided by the clock generator under the control of the coding sequence. For samples, such as symbol “0” corresponds to f ₀ (t) waveform samples, symbol “1” corresponds to f ₁ (t) waveform samples, and selected waveform samples are converted into analog signals by digital-to-analog converters, which are sent by RF transmitters. .

FIG. 8 is a block diagram of an EBPSK-based communication receiving end module according to an embodiment of the present invention. As shown in FIG. 8, the receiver is provided with a digital impulse filter as a demodulator. The specific step of receiving is to take the absolute value of the output of the digital impulse filter and then pass through low-pass filtering to obtain an impact envelope:

1) extracting the impact envelope and sending the entry limit detector and the variable delay device respectively, performing the threshold detection and shaping to obtain the corresponding return-to-zero code, and sending the obtained return-to-zero code to the clock generator and the delay calculator at the same time;

2) When the return-to-zero code "1" appears, the chip bit synchronization clock is reset, and the duration of the high level is measured by the delay calculator, according to the highest point of the impact envelope and the return edge of the return-to-zero code "1" Relative positional relationship, the delay amount of the impact envelope is obtained, otherwise the delay amount is assigned to 0, and the delay of the impact envelope is dynamically adjusted according to the obtained delay amount, so that the rising edge and the impact envelope of the chip bit synchronization clock Aligned at the highest point;

3) Under the time reference of the chip bit synchronization pulse, correlate and integrate the envelope integral value with the local PN code, perform threshold detection on the relevant integral value, and determine the return-to-zero code;

4) When the threshold detector has a return-to-zero code "1", the symbol-bit synchronization clock is reset, and a zero-threshold threshold sampling decision is taken under the guidance of the symbol-bit synchronization clock, that is, the received data sequence is demodulated.

Among them, the variable delay is implemented by an addressable shift register.

The receiver of the present invention employs a super narrowband receiver based on a digital impulse filter. The impact filter exhibits a class of excellent notch selection characteristics at the modulation center frequency, which can filter out the out-of-band noise of the received signal to the greatest extent, highlighting the difference between the symbols “0” and “1”, thus greatly improving The demodulation performance of EBPSK modulation.

Figure 9 is a typical EBPSK receiver in which a bit-synchronization implementation typically employs a digital phase-locked loop, such as a lead/lag gate synchronizer, which is similar to the conventional carrier-frequency-synchronized phase-locked loop method. Due to the feedback loop and the process of constant adjustment in the closed-loop method, it directly affects its error. Eliminate speed. Moreover, it is hoped that the promotion of the advantages of asymmetric modulation and the application will continue to simplify its hardware structure to meet the low-cost requirements for remote meter reading based on Power Line Communication (Smart Line Communication) in the smart grid, and the Internet of Things application for wireless Network Sensor (WSN: Wireless Sensor Network) node low power requirements.

Thus, the present invention proposes a complete hardware structure of the EBPSK coded modulation receiver as shown in FIGS. 10 and 11, including using the impact filter output signal for fast chip bit synchronization, and using the chip bit synchronization signal for fast code. Modules such as meta-synchronization.

The specific implementation of this embodiment is directed to an EBPSK modulated transmitter and a corresponding digital impulse filter based EBPSK receiver.

Figure 13 is an EBPSK encoded waveform, wherein: Figure 13(a) is a transmission symbol; Figure 13(b) is a PN code sequence; Figure 13(c) is a coding sequence; Figure 13(d) is an EBPSK corresponding to an EBPSK coding sequence. Baseband waveform diagram. 14 is a time-domain waveform diagram of the EBPSK coded modulated signal before and after passing through the digital impulse filter, wherein: FIG. 14(a) is an EBPSK coded modulation waveform; and FIG. 14(b) is an output waveform of the digital impulse filter. Figure 15 is a relative positional relationship between the highest point of the impact envelope and the falling edge of the return-to-zero code "1" when the EBPSK modulation coefficient τ/T = 2/20 = 1/10, where: Figure 15 (a) is the impact of EBPSK The output waveform of the filter and detector; Figure 15 (b) is a schematic diagram of the return-to-zero code; Figure 15 (c) is the delay-adjusted EBPSK output envelope; Figure 15 (d) is the reset Schematic diagram of chip bit synchronization. In the figure, the ordinate is the amplitude and the abscissa is the time. 16 is an effect diagram of demodulation and decoding of an EBPSK coded modulation waveform by the novel receiver proposed by the present invention, wherein: FIG. 16(a) is a time-delay-adjusted impact filter output envelope of an EBPSK coded modulation waveform; FIG. (b) a delay of half a chip period for synchronizing chip bits as a new bit synchronization signal; FIG. 16(c) is an integral value of an output envelope in a chip period, taking a threshold value as a relative zero point; 16(d) is the output value of the associated integrator of FIG. 12; FIG. 16(e) is a schematic diagram of the reset symbol bit; FIG. 16(f) is the output symbol of the demodulated decoding; The coordinates are time.

1. EBPSK coded modulation transmitter

For the EBPSK modulation method defined by the equation (1), take A=B=1, θ=π, K=2, N=20, the intermediate frequency f _c =10 MHz, and the number of chips of the PN code in the unit symbol. Taking L=2 ³ -1=7, the corresponding code rate is f _c /(N·L)=0.0714 Mbps. Firstly, the sequence to be transmitted is multiplied by the PN code to obtain a coded sequence, and then the code is sent to the EBPSK modulator. The specific implementation method is described in the previous "EBPSK modulation system". The actual coded waveform and the modulated waveform are respectively shown in Figure 13 and Figure 14 (a).

2, impact filter

The impact filter as a core component is a narrowband bandpass filter that exhibits a very narrow notch selection characteristic at the center frequency in the passband, enabling asymmetric binary keying represented by EBPSK modulation. The filtered output waveform of the signal produces a strong parasitic amplitude-modulated impact at the modulation of the symbol "1", ie at the phase transition. The transfer function of a digital impulse filter with a single zero-point three pole (actually a pair of conjugate zeros and three pairs of conjugate poles) is as follows:

When the normalized frequency f _c /f _s =1 /10 and the hop angle θ=π, a set of coefficients with excellent performance are as follows:

b ₀ = b ₂ =1, b ₁ = 1.6181733185991785

a ₁ =-4.578193199274645, a ₂ =9.654665924115726, a ₃ =-11.692079480819313a ₄ =8.5756341567768217, a ₅ =-3.6121554794765309, a ₆ =0.70084076007371199

The impact filter has a notch-frequency selection characteristic for the EBPSK modulated signal, and converts the phase jump of the modulated waveform into a strong parasitic amplitude modulation. Here, a single zero-point three-pole filter scheme is adopted as the demodulation filter. The transfer function and the coefficients of the filter are as shown in equation (2). In this implementation, the sampling frequency of the ADC is 100MHz, that is, 10 points per carrier cycle:

1) Fig. 14(a) is an EBPSK coded modulation waveform with θ = π, τ/T = 2/20, carrier frequency f _c = 10 MHz, and a code rate of 0.07 MHz, and the EBPSK coded modulated signal of Fig. 14(a) is After 100MHz sampling, the single-zero and three-pole digital impulse filter defined by equation (2) is sent to obtain the impulse waveform as shown in Fig. 14(b). The ordinate is the amplitude and the abscissa is the time. The digital impulse filter can be implemented with a multiplier and a shift register, and is generally cascaded.

2) For the impact filter output signal of Fig. 14(b), pass it through the detector, that is, the rectifier and the low-pass filter, and output as shown in Fig. 15(a).

3. Typical EBPSK Modulation Receiver

A typical EBPSK modulation receiver is shown in Figure 9. The EBPSK modulated signal received by the antenna is subjected to a preamplifier and then subjected to a mixer, downconverted to an intermediate frequency and amplified by an intermediate frequency to be converted into a digital digital signal by the ADC; The mixer realizes carrier synchronization through the analog phase-locked loop; the basic reference crystal is provided by the phase-locked loop, and is sent to the clock generator to provide the system clock and the sampling pulse for each function module of the EBPSK demodulator, that is, the sampling of the receiver is realized. Synchronization; bit synchronization is also required for the demodulation decision result of the EBPSK signal.

4. New EBPSK coded modulation receiver

1) Digital demodulator and chip bit synchronous clock implementation

The implementation block diagram is shown in Figure 10. The threshold envelope is used to shape the impact envelope to obtain a return-to-zero code as shown in Fig. 15(b). The detection threshold can be directly set to a fixed value or automatically adjusted. There are many ways to implement the adaptive threshold. Generally, the arithmetic mean value of the peak of the impact envelope and its reference level value shown in Figure 15(a) can be taken. For convenience, the threshold is taken as 60;

The return-to-zero code is sent to the clock generator and the variable delay unit, respectively. When the return to zero code "1" appears:

1 Use the delay calculator to measure the high-level duration, that is, to sample and count the sampling points exceeding the threshold, and obtain the impact envelope according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the return-to-zero code "1". Delay amount

2 dynamically adjust the delay of the impact envelope according to the delay amount measured by the variable delay calculator, dynamically adjust the delay of the impact envelope, so that the falling edge of the return-to-zero code is aligned with the highest point of the impact envelope, such as Figure 15 (c). This example uses an addressable shift register to implement a variable delay. The address of the shift register is the delay amount of the impact envelope. The output of the shift register is the content of the register pointed to by the address.

3 reset the clock generator on the falling edge of return-to-zero code 1, so that the start time of the clock generator is aligned with the falling edge of the return-to-zero code "1", and a bit-synchronous clock of a fixed frequency is generated, as shown in Fig. 15(d). This is shown to achieve chip bit synchronization to guide the integration of the chip envelope sample points.

2) Digital decoder and symbol bit synchronization clock implementation

The implementation block diagram is shown in Figure 11. According to the synchronization relationship between the chip bit synchronization and the delay envelope, the chip bit synchronization signal is delayed by half a chip period (this example uses a shift register) as a bit synchronization signal of the chip integration value, as shown in FIG. 16 ( b) shown. Under the guidance of the bit synchronous clock:

1 Integrate the delay envelope (in this example, take 10 sampling points from the rising edge of the bit synchronization to integrate), wherein the envelope integral takes the threshold as the relative zero point, and the integral value is shown in Figure 16(c);

2 The integral value is sent to the correlation integrator shown in Fig. 9, and the integrated integral is integrated with the chip integral value and the local PN code, and the output is as shown in Fig. 16(d);

3 The output value of the relevant integrator is absolutely worth its size, and is sent to the entry limit detector for shaping. When the return-to-zero code "1" appears, the symbol bit synchronization clock is reset, so that the rising edge of the symbol bit synchronization clock Align with the falling edge of the return-to-zero code, as shown in Figure 16(e), where the threshold is taken as 2000;

3) Demodulation and decoding output

Under the guidance of the symbol bit synchronization clock, the relevant integral output value is sampled and judged, and the threshold value is 0, and the output symbol is obtained, as shown in Fig. 16(f).

The overall working flow of the receiver is shown in Figure 12. After the absolute value of the output of the digital shock filter is taken, the low-pass filtering is performed to obtain the envelope of the output signal; the threshold detection of the envelope of the output signal is performed to obtain the corresponding return-to-zero code. When the return-to-zero code "1" appears, the chip bit synchronization clock is reset, and the delay calculation is performed according to the duration of the high level and the relative positional relationship between the highest point of the impact envelope and the falling edge of the return-to-zero code "1". Obtain the delay amount and keep the delay amount until the arrival of the next return-to-zero code "1"; The delay amount dynamically adjusts the delay of the impact envelope, so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope; at the rising edge of the chip bit synchronization pulse, the impact envelope is integrated to obtain an integral output. The chip bit sync pulse is delayed by half a chip period as a new clock, the integral output is guided to correlate and integrate with the local PN code, and the correlation value is threshold-detected, and the return is determined according to the given threshold value. Zero code; when the threshold detection output presents the return-to-zero code "1", the correlation peak is captured, the symbol bit synchronization clock is reset, and the zero-value threshold sampling decision is taken under the guidance of the symbol-bit synchronization clock, and the demodulated output is received. Source sequence.

5. Spectrum efficiency and anti-interference performance of EBPSK coded modulation system

Figure 17 is an EBPSK modulated power spectrum estimation with parameters A = B = 1, B = π, τ / T = 2 / 20, carrier frequency f _c = 10 MHz, Figure 18 is EBPSK coded modulation power spectrum estimation, chip length L = 7, the remaining parameters are the same as Figure 17. Comparing Fig. 17 and Fig. 18, compared with the unencoded EBPSK communication system, the spectrum is not much different, only the normalized amplitude is slightly increased.

Figure 19 is an anti-interference performance curve of an uncoded EBPSK communication system. The interference signal takes the BPSK modulation signal, and the code rate is the same as the EBPSK signal. The transmission shaping filter takes a raised cosine roll-off filter with a roll-off coefficient α=0.5, and f _c in the figure represents the modulation frequency of the BPSK modulation signal. Figure 20 is an anti-interference performance curve of an EBPSK coded modulation communication system. The chip length L=7, and the narrowband interference signal parameters are the same as those in FIG. Comparing Fig. 19 with Fig. 20, the EBPSK code modulation system can improve the anti-interference performance at the expense of the code rate, and the performance improvement is more obvious for the narrowband interference channel. The coding length can be flexibly set, especially suitable for working in a bad channel environment. in.

In summary, the present invention has the following technical effects:

The transmitter of the invention adopts EBPSK-based code modulation, and the receiver fully utilizes the output signal of the modulated signal through the digital impulse filter to generate strong parasitic amplitude modulation at the information modulation of the data "1", and the structure does not require a phase-locked loop and a complicated structure. The fast demodulation and decoding method of the pseudo-code synchronization structure can end the transition process in a few digital elements, realize accurate chip bit synchronization and symbol bit synchronization, which makes the EBPSK receiver fully digitalized and greatly simplifies EBPSK demodulation. Decoder hard The structure is suitable for high-efficiency digital communication systems based on asymmetric binary offset keying code modulation, especially for fast demodulation and decoding of bad channels.

Although the invention has been described in detail above, the invention is not limited thereto, and various modifications may be made by those skilled in the art in accordance with the principles of the invention. Therefore, modifications made in accordance with the principles of the invention are to be understood as falling within the scope of the invention.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.

The units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration The unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to the program instructions. The foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The steps of the foregoing method embodiments are included; and the foregoing storage medium includes: a mobile storage device, a read only memory (ROM, Read-Only Memory), random access memory (RAM), disk or optical disk, and other media that can store program code.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims (16)

1. An EBPSK-based communication method, comprising:

   The transmitting end encodes the information sequence and performs EBPSK modulation processing to obtain an EBPSK modulated signal;

   The receiving end performs EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.
2. The method according to claim 1, wherein the transmitting end encodes the information sequence and the EBPSK modulation process, and the step of obtaining the EBPSK modulated signal specifically includes:

   The transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and saves;

   Encoding the information sequence to obtain a coding sequence;

   Corresponding f0 waveform samples and f1 waveform samples are selected for each symbol in the coding sequence to obtain an EBPSK modulated signal.
3. The method according to claim 1 or 2, wherein the receiving end performs EBPSK demodulation and decoding processing on the EBPSK modulated signal, and the step of obtaining the information sequence comprises:

   Inputting the EBPSK modulation signal to the digital impulse filter, and taking an absolute value of the signal output by the digital impulse filter, and performing low-pass filtering processing to obtain an impact envelope of the output signal;

   Performing a first threshold detection on the impact envelope of the output signal, obtaining a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code;

   Using the chip bit synchronization clock, integrating the impact envelope to obtain an impact envelope integral value, and correlating and integrating the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral. value;

   Performing a second threshold detection on the correlation integral value, obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code;

   Using the symbol bit synchronization clock, performing sampling decision processing on the relevant integral value to obtain a letter Sequence of interest.
4. An EBPSK-based code modulation method includes:

   The transmitting end discretizes the EBPSK modulated waveforms f0 and f1 corresponding to the symbols 0 and 1, respectively, and obtains the f0 waveform sample and the f1 waveform sample and saves;

   Encoding the information sequence to obtain a coding sequence;

   Corresponding f0 waveform samples and f1 waveform samples are selected for each symbol in the coding sequence to obtain an EBPSK modulated signal.
5. The method of claim 4 wherein said step of encoding the sequence of information to obtain a coded sequence comprises:

   Multiplying the information sequence by the pseudo-random sequence to obtain a coding sequence.
6. An EBPSK-based decoding and demodulation method includes:

   Inputting the EBPSK modulation signal to the digital impulse filter, and taking an absolute value of the signal output by the digital impulse filter, and performing low-pass filtering processing to obtain an impact envelope of the output signal;

   Performing a first threshold detection on the impact envelope of the output signal, obtaining a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code;

   Using the chip bit synchronization clock, integrating the impact envelope to obtain an impact envelope integral value, and correlating and integrating the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral. value;

   Performing a second threshold detection on the correlation integral value, obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code;

   Using the symbol bit synchronization clock, the correlation integral value is subjected to sampling decision processing to obtain a sequence of information.
7. The method according to claim 6, wherein said step of determining a chip bit synchronization clock based on said obtained first return-to-zero code comprises:

   Determining whether the generated first return-to-zero code is "1";

   If the generated first return-to-zero code is "1", the delay amount of the impact envelope is obtained according to the relative positional relationship between the highest point of the impact envelope and the falling edge of the first return-to-zero code "1";

   According to the obtained delay amount, the delay of the impact envelope is adjusted so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.
8. The method according to claim 6, wherein said step of adjusting a symbol bit synchronization clock according to said obtained second return-to-zero code comprises:

   Determining whether the generated second return-to-zero code is "1";

   If the generated second return code is "1", the symbol bit synchronization clock is reset.
9. An EBPSK-based communication system including a transmitter and a receiver, wherein:

   a transmitter configured to encode the information sequence and EBPSK modulation to obtain an extended binary phase shift keying EBPSK modulated signal;

   The receiver is configured to perform EBPSK demodulation and decoding processing on the EBPSK modulated signal to obtain an information sequence.
10. The system of claim 9 wherein said transmitter comprises:

    a sampling module configured to discretize EBPSK modulated waveforms f0 and f1 corresponding to symbols 0 and 1, respectively, to obtain f0 waveform samples and f1 waveform samples and save;

    An encoding module configured to encode the information sequence to obtain a coding sequence;

    And a modulation module configured to select a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.
11. A system according to claim 9 or 10, wherein said receiver comprises:

    a demodulation module configured to input an EBPSK modulation signal to the digital impulse filter, and perform an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, obtaining an impact envelope integral value;

    a decoding module, configured to use the chip bit synchronization clock to correlate and integrate the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral value; and perform a second threshold detection on the correlation integral value Obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code; using the symbol-bit synchronization clock, performing a sampling decision process on the correlation integral value to obtain an information sequence.
12. An EBPSK-based transmitter that includes:

    a sampling module configured to discretize EBPSK modulated waveforms f0 and f1 corresponding to symbols 0 and 1, respectively, to obtain f0 waveform samples and f1 waveform samples and save;

    An encoding module configured to encode the information sequence to obtain a coding sequence;

    And a modulation module configured to select a corresponding f0 waveform sample and an f1 waveform sample for each symbol in the coding sequence to obtain an EBPSK modulated signal.
13. The transmitter of claim 12 wherein said sampling module obtains a coded sequence by multiplying said sequence of information with said pseudo-random sequence.
14. An EBPSK-based receiver that includes:

    a demodulation module configured to input an EBPSK modulation signal to the digital impulse filter, and perform an absolute value of the signal output by the digital impulse filter, and then perform low-pass filtering processing to obtain an impact envelope of the output signal; Performing a first threshold detection by the impact envelope to obtain a first return-to-zero code, and determining a chip bit synchronization clock according to the obtained first return-to-zero code; using the chip bit synchronization clock, performing the impact envelope Integral processing, obtaining an impact envelope integral value;

    a decoding module, configured to use the chip bit synchronization clock to correlate and integrate the impact envelope integral value with a local pseudo random sequence to obtain a correlation integral value; and perform a second threshold detection on the correlation integral value Obtaining a second return-to-zero code, and adjusting a symbol bit synchronization clock according to the obtained second return-to-zero code; using the symbol-bit synchronization clock, performing a sampling decision process on the correlation integral value to obtain an information sequence.
15. The receiver according to claim 14, wherein said demodulation module is configured to determine Whether the first return-to-zero code generated by the break is "1", and if the generated first return-to-zero code is "1", according to the relative position of the highest edge of the impact envelope and the falling edge of the first return-to-zero code "1" The relationship is obtained by the delay amount of the impact envelope, and the delay of the impact envelope is adjusted according to the obtained delay amount, so that the rising edge of the chip bit synchronization clock is aligned with the highest point of the impact envelope.
16. The receiver according to claim 14, wherein the decoding module is configured to determine whether the generated second return-to-zero code is "1", and if the generated second return-to-zero code is "1", reset the location The symbol bit synchronization clock is described.

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