Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
  • H10D48/30—Devices controlled by electric currents or voltages
  • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H10D48/34—Bipolar devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/075—Connecting or disconnecting of bond wires
  • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
  • H10W72/07552—Controlling the environment, e.g. atmosphere composition or temperature changes in structures or sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/521—Structures or relative sizes of bond wires
  • H10W72/527—Multiple bond wires having different sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/541—Dispositions of bond wires
  • H10W72/547—Dispositions of multiple bond wires
  • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/541—Dispositions of bond wires
  • H10W72/547—Dispositions of multiple bond wires
  • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/926—Multiple bond pads having different sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
  • H10W72/932—Plan-view shape, i.e. in top view
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the present disclosure relates to power modules for controlling power delivery to a load.
• SiC silicon carbide
• a conventional power device may require a bipolar structure, such as that of an insulated gate bipolar transistor (IGBT), when blocking high voltages (e.g., voltages greater than 5 kV). While utilizing a bipolar structure generally decreases the resistance of the drift layer due to conductivity modulation thereof, bipolar structures also suffer from relatively slow switching times. As will be appreciated by those of ordinary skill in the art, the reverse recovery time (attributed to the relatively slow diffusion of minority carriers) of a bipolar structure limits the maximum switching time thereof, thereby making silicon devices generally unsuitable for high voltage and high frequency applications.
• IGBT insulated gate bipolar transistor
• unipolar SiC power devices may be used to block voltages up to 10 kV or more.
• the majority carrier nature of such unipolar SiC power devices effectively eliminates the reverse recovery time of the device, thereby allowing for very high switching speeds (e.g., less than 100 ns for a double- diffused metal-oxide-semiconductor field-effect transistor (DMOSFET) with a 10 kV blocking capability and a specific on-resistance of about 100 mQ * cm 2 ).
• DMOSFET double- diffused metal-oxide-semiconductor field-effect transistor
• Power devices are often interconnected and integrated into a power module, which operates to dynamically switch large amounts of power through various components such as motors, inverters, generators, and the like.
• a power module which operates to dynamically switch large amounts of power through various components such as motors, inverters, generators, and the like.
• a power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing.
• the switch modules are interconnected and configured to facilitate switching power to a load.
• Each one of the switch modules includes at least one transistor and at least one diode.
• the switch modules are able to block 1200 volts, conduct 300 amperes, and have switching losses of less than 20 milli-Joules.
• a power module includes a housing with an interior chamber, at least one power substrate within the interior chamber, and a gate connector.
• the power substrate includes a switch module on a first surface of the power substrate for facilitating switching power to a load.
• the switch module includes at least one transistor and at least one diode.
• the gate connector is coupled to a gate contact of the at least one transistor via a signal path that includes a first conductive trace on the first surface of the power substrate. Using a conductive trace on the first surface of the power substrate to connect the gate connector to the gate of the at least one transistor reduces interference in the power module and increases the reliability of the connection between the gate connector and the gate contact of the at least one transistor.
• a power module includes a housing with an interior chamber, a pair of output contacts, and a plurality of switch modules.
• the plurality of switch modules are mounted within the interior chamber of the housing, and are interconnected to facilitate switching power from a power source coupled between the output contacts to a load.
• the pair of output contacts are arranged such that an area of at least 150 mm 2 of each one of the output contacts is located less than 1 .5 mm from the other output contact. Providing an area of each output contact of at least 150 mm 2 that is less than 1 .5 mm from the other output contact reduces the leakage inductance between the output contacts, thereby increasing the performance of the power module.
• Figure 1 is a schematic illustrating the details of a power module according to one embodiment of the present disclosure.
• Figure 2 is a graph illustrating the various signals produced by the power module shown in Figure 1 .
• Figure 3 is a schematic illustrating the details of the switching modules in the power module shown in Figure 1 .
• Figure 4 is a block diagram illustrating details of the power module shown in Figure 1 according to one embodiment of the present disclosure.
• Figure 5 is a plan-view illustrating details of the power module shown in Figure 1 according to one embodiment of the present disclosure.
• Figure 6 is a plan-view illustrating further details of the power module shown in Figure 1 according to one embodiment of the present disclosure.
• Figure 7 is a plan-view illustrating an outer housing of the power module shown in Figure 1 according to one embodiment of the present disclosure.
• Figure 8 is a plan-view illustrating details of the outer housing of the power module shown in Figure 1 according to one embodiment of the present disclosure.
• Figure 9 is a block diagram illustrating details of the power substrates in the power module shown in Figure 4 according to one embodiment of the present disclosure.
• first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
• second element could be termed a first element, without departing from the scope of the present disclosure.
• the term "and/or" includes any and all combinations of one or more of the associated listed items.
• Coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
• Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
• FIG. 1 shows an exemplary power module 10 according to one embodiment of the present disclosure.
• the power module 10 includes two switch modules SM1 and SM2, which are controlled by a control system 12 to deliver power from a power supply (DC+/DC-) to a load 14 in a controlled manner.
• the switch modules SM1 and SM2 form a half-bridge, the details of which are discussed below.
• Each one of the switch modules SM1 and SM2 includes at least a first transistor in anti-parallel with a first diode.
• a first switch module SM1 includes a first transistor Q1 in anti-parallel with a first diode D1
• a second switch module SM2 includes a second transistor Q2 in anti-parallel with a second diode D2.
• the first transistor Q1 and the second transistor Q2 are metal-oxide-semiconductor field-effect transistors (MOSFETs).
• any suitable switching device for example, insulated gate bipolar transistors (IGBTs), field-effect transistors (FETs), junction field-effect transistors (JFETs), high electron mobility transistors (HEMTs), or the like, may be used in the switching modules SM1 and SM2 without departing from the principles of the present disclosure.
• the first diode D1 and the second diode D2 may be Schottky diodes, and in particular, junction barrier Schottky diodes.
• any suitable diode device for example, P-N diodes and PiN diodes, may be used in the switching modules SM1 and SM2 without departing from the principles of the present disclosure.
• the first diode D1 and the second diode D2 are omitted, and their functionality is replaced by the internal body diode of the first transistor Q1 and the second transistor Q2, respectively.
• Using the internal body diode of the first transistor Q1 and the second transistor Q2 in place of the first diode D1 and the second diode D2 may save space and cost in the power module 10.
• a gate contact G of the first transistor Q1 and a source contact S of the first transistor Q1 are coupled to the control system 12.
• a gate contact G and a source contact S of the second transistor Q2 are also coupled to the control system 12.
• the connection from the gate contact G to the first transistor Q1 and the second transistor Q2 to the control system 12 may be accomplished via a relatively low power gate connector G1 and G2, respectively.
• the connection from the source contact S of the first transistor Q1 and the second transistor Q2 to the control system 12 may be accomplished via a low-power source return connection S1 and S2 used to measure one or more operational parameters of the first transistor Q1 or the second transistor Q1 , respectively.
• a drain contact D of the first transistor Q1 is coupled to a positive power supply terminal DC+.
• a drain contact D of the second transistor Q2 is coupled to an output terminal OUT.
• the source contact S of the first transistor Q1 is also coupled to the output terminal OUT.
• the source contact S of the second transistor Q2 is coupled to a negative power supply terminal DC-.
• the load 14 is coupled between the output terminal OUT and the negative DC power supply terminal DC-.
• the first transistor Q1 , the first diode D1 , the second transistor Q2, and the second diode D2 may each be majority carrier devices.
• Majority carrier devices generally include FETs such as MOSFETs, HEMTs, JFETs, and the like, but do not include thyristors, bipolar transistors, and insulated gate bipolar transistors (IGBTs). Accordingly, the power module 10 may be capable of operating at higher switching speeds and suffer lower switching losses when compared to a conventional power module employing bipolar devices.
• the first transistor Q1 , the first diode D1 , the second transistor Q2, and the second diode D2 are wide band-gap devices.
• a wide band-gap device is a semiconductor device with a band-gap greater than or equal to 3.0 electron-volts (eV).
• the first transistor Q1 , the first diode D1 , the second transistor Q2, and the second diode D2 may be silicon carbide (SiC) or gallium nitride (GaN) devices.
• Si has a bandgap of approximately 1 .1 eV
• SiC has a band-gap of approximately 3.3 eV.
• the power module 10 may maintain switching losses of less than 25 milli-Joules (mJ), less than 20 mJ, and even less than 15 mJ in various embodiments when operating between -40C and 150C, while also providing a low on-state voltage drop.
• the switching losses of the power module 10 generally will not fall below 1 mJ.
• the first transistor Q1 , the first diode D1 , the second transistor Q2, and the second diode D2 are both majority carrier devices and wide band-gap devices.
• the control system 12 operates the first switching module SM1 and the second switching module SM2 in a complementary fashion, such that when the first switching module SM1 is conducting, the second switching module SM2 is blocking, and vice-versa.
• a graph showing the voltage at the gate contact G of the first transistor Q1 , the voltage at the gate contact G of the second transistor Q2, the voltage at the output terminal OUT, and the current through the load 14 over the course of a switching cycle of the power module 10 is shown in Figure 2.
• T1 the first switching module SM1 is conducting, while the second switching module SM2 is blocking.
• the output terminal OUT is connected to the positive power supply terminal DC+, thereby providing a positive power supply voltage to the load 14 and causing current to flow from the positive power supply terminal DC+ through the first transistor Q1 and into the load 14.
• the load 14 is an inductive load, thereby causing the current through the load 14 to slowly ramp up while the first switching module SM1 is conducting.
• the first switching module SM1 is switched to a blocking mode. Further, the second switching module SM2 remains in a blocking mode.
• current continues to flow to the load 14 from the output terminal OUT due to the internal capacitances associated with each one of the first switching module SM1 and the second switching module SM2. Specifically, about half of the current through the load 14 is provided by the internal capacitance of each one of the switching modules SM1 and SM2. The voltage at the output terminal OUT therefore slews to ground at a given rate, and the current through the load 14 gradually decreases.
• the output terminal OUT is coupled to the negative power supply terminal DC-, which may be ground in some
• a fourth time period T4 the second switching module SW2 is switched to a blocking mode. Further, the first switching module SM1 remains in a blocking mode. In this time period, a negative current continues to flow to the load from the output terminal OUT due to the internal capacitances associated with each one of the first switching module SM1 and the second switching module SM2. Specifically, about half of the current through the load 14 is provided by the internal capacitance of each one of the switching modules SM1 and SM2. The voltage at the output terminal OUT therefore slews from ground to the positive power supply voltage provided at the positive power supply terminal DC+, and the current through the load 14 becomes increasingly positive. Finally, during a fifth time period T5, the switching cycle starts over, such that the first switching module SM1 is placed in a conducting mode while the second switching module SM2 remains in a blocking mode.
• FIG. 3 shows details of the first switching module SM1 according to one embodiment of the present disclosure.
• the second switching module SM2 may be configured similarly to the first switching module SM2, but is not shown for brevity.
• the first transistor Q1 and the first diode D1 of the first switching module SM1 may include multiple transistors Q1 ⁇ - e and multiple anti-parallel diodes D1 coupled in parallel.
• the drain contacts D of each one of a number of transistors Q1 1_ 6 may be coupled together
• the source contacts S of each one of the transistors Q1 1_ 6 may be coupled together
• the gate contacts G of each one of the transistors Q1 ⁇ - e may each be coupled together through a gate resistor R G .
• Each one of the transistors Q1 1- 6 includes an anti-parallel diode D1 -6 coupled between the source contact S and the drain contact D thereof. Although six transistors Q1 1 -6 are shown coupled in parallel with six anti-parallel diodes D1 any number of transistors and anti- parallel diodes may be used without departing from the principles of the present disclosure.
• each one of the transistors Q1 1 -6 is rated to block 1 .2 kV and conduct 50A, thereby making the first switching module SM1 capable of conducting 300A.
• each one of the transistors Q1 may be rated to block 1 .2 kV and conduct 40A, thereby making the first switching module SM1 capable of conducting 240A.
• each one of the transistors Q1 1 -6 may be rated to block 1 .2 kV and conduct 20A, thereby making the first switching module SM1 capable of conducting 120A.
• the gate resistors RG may be provided to dampen any undesirable oscillations in the first switching module SM1 that may occur when the first switching module SM1 is driven at a relatively high transition speed (e.g., greater than 20 V/ns).
• the resistance of the gate resistors RG may vary according to the current rating of each one of the transistors Q1 1 -6 , and therefore, the overall current rating of the first switching module SM1 . In one embodiment wherein the first switching module SM1 has a current rating of 120A, each one of the gate resistors RG has a resistance between about 1 ⁇ and 15 ⁇ .
• each one of the gate resistors R G has a resistance between about 1 ⁇ and 15 ⁇ . In yet another embodiment wherein the first switching module SM1 has a current rating of 300A, each one of the gate resistors has a resistance between about 15 ⁇ and 20 ⁇ .
• FIG 4 shows details of the power module 10 according to one embodiment of the present disclosure.
• the power module 10 includes a housing 16 provided with an interior chamber 18 that holds one or more power substrates 20.
• the interior chamber 18 of the housing 16 holds a first power substrate 20A, a second power substrate 20B, a third power substrate 20C, and a fourth power substrate 20D.
• the interior chamber 18 of the housing 16 can hold any number of power substrates 20 without departing from the principles of the present disclosure.
• Each one of the power substrates 20 is shown including multiple transistors Q, multiple diodes D, and multiple resistors R, that represent the primary components of the first switching module SM1 and the second switching module SM2.
• the first switching module SM1 is provided by the first power substrate 20A and the second power substrate 20B
• the second switching module SM2 is provided by the third power substrate 20C and the fourth power substrate 20D, respectively.
• interconnects between the components on each one of the power substrates 20 may be provided by metal traces (not shown) on the surface of the power substrates 20. Further, wire bonds (not shown) may be provided to interconnect the different power substrates 20, as well as to connect the power substrates 20 to one or more external connectors (not shown).
• the power substrates 20 may be mounted to a mounting structure 22 that is affixed to the housing 16.
• the mounting structure 22 is a planar heat sink that also functions to dissipate heat generated by the first switching module SM1 and the second switching module SM2.
• the multiple transistors Q and diodes D may be majority carrier devices, thereby decreasing the switching time and losses associated with each one of the transistors Q and diodes D. Accordingly, the power module 10 may operate at higher frequencies, and suffer smaller switching losses than a conventional power module. Further, the transistors Q and diodes D may be wide band-gap devices, such as SiC devices. As discussed above, using SiC for the transistors Q and diodes D significantly reduces the switching time and switching losses of the transistors Q and diodes D, thereby increasing the performance of the power module 10.
• Figure 5 shows an exemplary mounting structure 22 and details of the power substrates 20 according to one embodiment of the present disclosure.
• the first power substrate 20A, the second power substrate 20B, the third power substrate 20C, and the fourth power substrate 20D are provided on the mounting structure 22.
• the first power substrate 20A includes three of the six transistors Q1 1 -3 , three gate resistors R G , and three of the six anti- parallel diodes D1 -3 of the first switching module SM1 .
• the second power substrate 20B includes the remaining transistors Q1 4 -e, gate resistors RG, and anti-parallel diodes D1 4-6 of the first switching module SM1 .
• the third power substrate 20C includes three of the six transistors Q2i -3 , three gate resistors R G , and three of the six anti-parallel diodes D2i -3 of the second switching module SM2.
• the fourth power substrate 20D includes the remaining transistors Q2 4 . 6 , gate resistors RG, and anti-parallel diodes D2 4 . 6 of the second switching module SM2.
• the thicker, dark lines represent wire-bonds between the various components in the power module 10 and between the various components and one or more outputs 24 of the power module 10.
• the outputs 24 of the power module 10 include the first gate connector G1 , the second gate connector G2, the first source return connector S1 , and the second source return connector S2 discussed above.
• a gate bus 26 is provided on the power substrates 20, and runs between the gate contacts G of the transistors Q2i -6 in the second switching module SM2 and the outputs 24 of the power module 10.
• the gate bus 26 runs between the gate contacts G of the transistors Q2i -6 in the second switching module SM2 and the second gate connector G2, and may further provide a low power path from the source contacts S of the transistors Q2i -6 in the second switching module SM2 and the second source return connector S2.
• the gate bus 26 is a metal trace on each one of the power substrates 20, which reduces interference in the power module 10 and increases the reliability of the connection between the gate contacts G of the transistors Q2i -6 in the second switching module SM2 and the outputs 24 of the power module 10, especially when compared to the "flying" gate connections used in conventional power modules.
• the mounting structure 22 may form all or part of a heat sink that functions to dissipate heat generated by the first switching module SM1 and the second switching module SM2.
• the gate bus 26 may be replaced with one or more coaxial cables to connect the gate contacts G of the transistors Q2i -6 in the second switching module and the outputs 24 of the power module 10.
• coaxial cables to connect the outputs to the gate contacts G of the transistors Q2-I -6 may provide improved isolation when compared to other solutions, thereby improving the performance of the power module 10.
• the outputs 24 for the gate contacts G of both the switching module SM1 and the second switching module SM2 are provided on the same side of the housing 16 of the power module 10, in other embodiments they may be provided on opposite sides of the housing 16.
• Providing the outputs 24 for the gate contacts G of the first switching module SM1 and the second switching module SM2 on opposite sides of the housing 16 may provide a shorter connection route to each one of the gate contacts G of the second switching module SM2, thereby reducing interference and improving the ruggedness of the power module 10. Further, providing the outputs 24 for the gate contacts G of the first switching module SM1 and the second switching module SM2 on opposite sides of the housing 16 may reduce the required resistance of the gate resistor R G of each one of the transistors Q2i -6 in the second switching module SM2, as a shorter connection path between the gate contacts G and the outputs 24 reduces the amount of oscillation seen by the transistors Q2i -6 .
• Figure 6 shows further details of the housing 16, the output terminal OUT, the positive power supply terminal DC+, and the negative power supply terminal DC- according to one embodiment of the present disclosure.
• the housing 16 is substantially rectangular, including cutaways for mounting holes M1 -M4 used to mount the power module 10 to a platform.
• the positive power supply terminal DC+, the negative power supply terminal DC-, and the output terminal OUT are shown.
• the stray inductance across the positive power supply terminal DC+ and the negative power supply terminal DC- may cause a decrease in the performance of the power module 10, especially at high frequencies of operation of the power module 10.
• the positive power supply terminal DC+ and the negative power supply terminal DC- are provided in close proximity to one another, generally less than 1 .5 mm apart, in order to mitigate the leakage inductance across the terminals.
• the terminals may be made wide, generally around 33.5 mm across, in order to maximize the area near the opposing terminal.
• the positive power supply terminal DC+ and the negative power supply terminal DC- will have an area between about 150 mm 2 and 200 mm 2 within 1 .5 mm of the other. In one embodiment, the positive power supply terminal DC+ and the negative power supply terminal DC- have an area of about 187.31 mm 2 within 1 .5 mm of the other.
• the capacitive effect generated by placing a relatively large area of the positive power supply terminal DC+ in close proximity to a large area of the negative power supply terminal DC- effectively reduces the leakage inductance between the terminals, thereby improving the performance of the power module 10.
• Figure 7 shows further details of the housing 16 according to one embodiment of the present disclosure.
• the housing 16 encases the power substrates 20, and provides output terminals for the positive power supply terminal DC+, the negative power supply terminal DC-, the output terminal OUT, and the respective paths to connect the first switching module SM1 and the second switching module SM2 to the control system 12.
• the housing 16 and the various output terminals are industry-standard, thereby allowing the power module 10 to be used as a drop-in solution for many preexisting platforms.
• a creepage divider 28 is provided between each one of the positive power supply terminal DC+, the negative power supply terminal DC-, and the output terminal OUT, which increases the creepage distance between the respective terminals by roughly 50%. Accordingly, the power module 10 may be used in higher voltage applications without the risk of shorting or other damage.
• one or more unused terminal locations 30 may exist in the housing 16.
• the unused terminal locations 30 may be used to provide Kelvin connections to one or more components of the power module 10, or may be used to provide connections to NTC temperature sensor modules included in the power module 10 in various embodiments.
• Figure 8 shows a cutaway view of the power module 10 according to one embodiment of the present disclosure.
• an additional creepage divider 32 is provided between the positive power supply terminal DC+ and the negative power supply terminal DC-, which isolates the respective nodes from one another and therefore protects against shorting at high voltages while simultaneously allowing the power module 10 to take advantage of a reduction in the leakage inductance between the nodes discussed above.
• Figure 9 shows details of the first power substrate 20A according to one embodiment of the present disclosure.
• the second power substrate 20B, the third power substrate 20C, and the fourth power substrate 20D may be configured similarly to the first power substrate 20A, but are not shown for brevity.
• the first power substrate 20A is formed on a baseplate 34, which may be copper.
• the baseplate 34 is aluminum silicon carbide (AlSiC), which may be lighter weight and offer better thermal matching with one or more attached components than copper.
• the baseplate 34 may be shared between each one of the power substrates 20, such that the first power substrate 20A, the second power substrate 20B, the third power substrate 20C, and the fourth power substrate 20D are all formed on the baseplate 34.
• a direct-bonded-copper (DBC) substrate 36 may be provided over the baseplate 34.
• the DBC substrate 36 may include a first metal layer 38 on the surface of the baseplate 34, an insulating layer 40 over the first metal layer 38, and a second metal layer 42 over the insulating layer 40 opposite the first metal layer 38.
• the first metal layer 38 and the second metal layer 42 may be, for example, copper.
• the insulating layer 40 may be, for example, aluminum nitride (AIN). Those of ordinary skill in the art will appreciate that many different suitable materials for the insulating layer 40 exist, for example, aluminum oxide (Al 2 0 3 ) or silicon nitride (Si 3 N 4 ), all of which are contemplated herein.
• Using AIN for the insulating layer 40 may provide much higher thermal conductivity when compared to conventional alumina or silicon nitride (SiN) layers. Given the relatively low electrical resistance associated with SiC devices and the low thermal resistance of AIN, the power module 10 can thus handle higher currents than conventional power modules.
• the thickness of the insulating layer 40 may be selected based on the targeted isolation voltage. Due to the advantages provided by the use of SiC components and the AIN insulating layer 40, the power module 10 is capable of handling greater power than a conventional device of the same size, and/or may be reduced to a smaller size than its conventional counterpart. [0047] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

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• Inverter Devices (AREA)
• Power Conversion In General (AREA)
• Junction Field-Effect Transistors (AREA)

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• 2015
  • 2015-05-14 CN CN201580037680.7A patent/CN106537586B/zh active Active
  • 2015-05-14 DE DE112015002272.4T patent/DE112015002272B4/de active Active
  • 2015-05-14 WO PCT/US2015/030853 patent/WO2015175820A1/en not_active Ceased
  • 2015-05-14 CN CN202010857239.6A patent/CN111900156B/zh active Active
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• 2020
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