WO2015159526A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO2015159526A1
WO2015159526A1 PCT/JP2015/002021 JP2015002021W WO2015159526A1 WO 2015159526 A1 WO2015159526 A1 WO 2015159526A1 JP 2015002021 W JP2015002021 W JP 2015002021W WO 2015159526 A1 WO2015159526 A1 WO 2015159526A1
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WO
WIPO (PCT)
Prior art keywords
die pad
semiconductor device
tab
down bond
sealing resin
Prior art date
Application number
PCT/JP2015/002021
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English (en)
Japanese (ja)
Inventor
尾方　秀一
彰 小賀
広行 田中
Original Assignee
パナソニックＩｐマネジメント株式会社
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Publication of WO2015159526A1 publication Critical patent/WO2015159526A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention provides a semiconductor device, in particular, a QFN package (Quad Flat Non-Leaded Package), where a terminal is exposed on the back surface of the semiconductor device, and a region for connecting a wire (metal thin wire) is provided on a part of the die pad
  • QFN package Quad Flat Non-Leaded Package
  • the present invention relates to a semiconductor device using a lead frame and having one surface of a die pad sealed with resin.
  • a method of using a die pad as one terminal by joining a wire (metal thin wire) directly to the die pad is generally performed.
  • FIGS. 5A to 5C a conventional semiconductor device will be described with reference to FIGS. 5A to 5C.
  • FIG. 5A to 5C are diagrams showing a configuration of a conventional semiconductor device
  • FIG. 5A is a transmission plan view in plan view from above
  • FIG. 5B is a cross-sectional view taken along line 5B-5B in FIG. 5A
  • FIG. 5C is an outline drawing showing an outline in plan view from below.
  • the semiconductor element 1 is electrically connected to the internal connection portion 3a of the lead 3 by the first wire 2a and electrically connected to the die pad 5 by the second wire 2b. Yes. Further, it is electrically connected to an external device via the external terminal portion 3 b of the lead 3.
  • the semiconductor element 1 is mounted on the die pad 5 through a die bond portion 6 that is an adhesive. Lead 3, die pad 5 and semiconductor element 1 are covered with sealing resin 4.
  • the die pad 5 includes suspension leads 7 on the diagonal line.
  • the conventional semiconductor device has a structure in which the die pad 5 and the external terminal portion 3b of the lead 3 are exposed from the lower surface of the semiconductor device, the upper surface and the outer surface of the die pad 5, the upper surface and the side surface of the semiconductor element 1, and the lead 3
  • the internal connection portion 3 a and the side surface thereof are only in contact with the sealing resin 4. Therefore, when the semiconductor device is soldered and mounted on a printed circuit board or the like, a thermal shrinkage stress, which is an internal stress (shrinkage stress) due to thermal shrinkage, is generated in the sealing resin 4 of the semiconductor device, and the die pad 5 and the sealing resin 4 Peeling is likely to occur at the interface.
  • the sealing resin 4 can be bonded only on one side of the die pad 5, the peeling that occurs at the die bond portion 6 easily proceeds on the interface between the die pad 5 and the sealing resin 4. Therefore, for example, the bonding reliability is lowered in the form of a wire (metal thin wire) disconnection.
  • the portion where the second wire 2b is directly connected to the die pad 5 (down bond portion 11) and the die bond portion 6 are linear (the flat upper surface of the die pad 5). Connected) When peeling occurs between the semiconductor element 1 and the die pad 5 due to thermal stress at the time of mounting, the peeling easily proceeds on the interface between the die pad 5 and the sealing resin 4 and reaches the second wire 2b. For this reason, the second wire 2b is disconnected and a characteristic defect occurs.
  • (Process A) represents immediately after the completion of the conventional semiconductor device
  • (Process B) represents immediately after the mounting of the conventional semiconductor device on the substrate.
  • (Process C) represents a state in which the conventional semiconductor device is being mounted (after 40 to 80 seconds have elapsed since the start of mounting)
  • (Process D) represents a state after the conventional semiconductor device has been mounted.
  • 6 is a partial cross-sectional view of a conventional semiconductor device in (Process A) to (Process D).
  • Process B that is, immediately after the semiconductor device is mounted on the substrate, moisture contained in the adhesive (not shown) used as the die bond portion 6 expands due to heat, and the semiconductor element 1 and the die pad 5 A crack 10 occurs between the two.
  • Patent Document 1 proposes a measure for preventing the progress of the above-described linear peeling by providing a gap (slit) in the die pad 5 between the die bond portion 6 and the second wire 2b. .
  • the sealing resin 4 when the resin is sealed, the resin is injected only from the upper surface side of the semiconductor device with one surface of the slit portion closed. For this reason, there is a problem that the slit portion becomes a closed space and the air is not completely removed and the resin is not filled.
  • the present invention has an object to provide a highly reliable semiconductor device that suppresses the progress of peeling and suppresses unfilling of resin while maintaining production efficiency and cost. To do.
  • a semiconductor device of the present invention is a semiconductor device, wherein a die pad formed in a central portion of the semiconductor device, a lead formed in a peripheral portion of the semiconductor device, and the die pad Down bonding tabs formed around the semiconductor chip, a semiconductor element mounted in a predetermined region on the die pad via a die bonding part, an internal connection part on the upper surface of the lead, and a first element formed on the upper surface of the semiconductor element.
  • the die pad and the down bond tab are not connected on the same plane by the step, so that the peeling that occurs in the die bond does not easily proceed at the step with a simple configuration, and the down bond tab It can be suppressed to reach. Furthermore, since the progress of peeling is suppressed, unfilling of resin is also suppressed. Therefore, while maintaining the production efficiency and cost, the progress of peeling is suppressed and the unfilling of resin is suppressed, and a highly reliable semiconductor device is provided.
  • the bottom surface of the down bond tab is located higher than the bottom surface of the die pad, and the sealing resin is filled under the bottom surface of the down bond tab.
  • the bottom surface of the down bond tab is made higher than the bottom surface of the die pad, so that filling of the resin into the gap between the bottom surface of the down bond tab and the bottom surface of the die pad proceeds, and the sealing resin Can be further suppressed.
  • the length of the down bond tab along one side of the die pad is shorter than the length of one side of the die pad.
  • the down bond tab is provided along at least one side of the die pad.
  • a plurality of the down bond tabs are arranged along one side of the die pad.
  • the semiconductor element and the die pad are connected via the plurality of down bond tabs, and noise of an electric signal can be suppressed. Further, since the contact area between the sealing resin and the down bond tab is increased, the resistance to peeling of the sealing resin is improved.
  • the semiconductor device further includes a second wire that connects a predetermined region on the upper surface of the down bond tab and a second electrode formed on the upper surface of the semiconductor element.
  • the outer surface and the bottom surface of the lead are exposed from the sealing resin.
  • the sealing resin is formed so that an outer side surface of the lead and a side surface of the sealing resin are flush with each other.
  • the die pad-tab connecting portion is provided between a central portion of the die pad and the down bond tab, and the upper surface of the die pad-tab connecting portion is the down bond tab. It is preferably lower than both the upper surface and the upper surface of the die pad.
  • the die pad-tab connecting portion is provided on a lower surface as viewed from the semiconductor element than both the upper surface of the down bond tab and the upper surface of the die pad, thereby suppressing unfilling of the resin. be able to.
  • the down bond tab and the center portion of the die pad are connected by a plurality of die pad-tab connecting portions.
  • the downbond tab and the central portion of the die pad are connected by the plurality of die pad-tab connection portions, so that the arrangement of the downbond tab is stabilized.
  • the semiconductor device of the present invention it is possible to provide a highly reliable semiconductor device by suppressing the progress of peeling and suppressing unfilling of resin while maintaining production efficiency and cost.
  • FIG. 1A is a transparent plan view showing the internal structure of the semiconductor device according to the first embodiment of the present invention as viewed from above.
  • 1B is a cross-sectional view showing the internal structure of the semiconductor device according to the first embodiment of the present invention, taken along line 1B-1B in FIG. 1A.
  • FIG. 1C is an external view of the semiconductor device according to the first embodiment of the present invention viewed from the back side.
  • FIG. 2A is a plan view showing the configuration of the lead frame of the semiconductor device according to the first embodiment of the present invention.
  • 2B is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, taken along line 2B-2B in FIG. 2A relating to the lead frame.
  • FIG. 2C is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, taken along line 2C-2C in FIG. 2A relating to the lead frame.
  • FIG. 3A is a plan view of the lead frame of the semiconductor device according to the second embodiment of the present invention when viewed from above.
  • 3B is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention, taken along the line 3B-3B in FIG. 3A relating to the lead frame.
  • 3C is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention, taken along line 3C-3C in FIG. 3A relating to the lead frame.
  • FIG. 3D is an external view of the semiconductor device according to the second embodiment of the present invention viewed from the back surface side.
  • FIG. 4A is a plan view of the semiconductor device shown in the third embodiment of the present invention when the lead frame is viewed from above.
  • 4B is a cross-sectional view of the semiconductor device according to the third embodiment of the present invention, taken along the line 4B-4B in FIG. 4A relating to the lead frame.
  • 4C is a cross-sectional view of the semiconductor device according to the third embodiment of the present invention, taken along line 4C-4C in FIG. 4A relating to the lead frame.
  • FIG. 4D is an external view of the semiconductor device according to the third embodiment of the present invention viewed from the back surface side.
  • FIG. 5A is a plan view showing a conventional semiconductor device.
  • FIG. 5A is a plan view showing a conventional semiconductor device.
  • FIG. 5B is a cross-sectional view showing an internal structure of the semiconductor device according to the related art, taken along line 5B-5B in FIG. 5A.
  • FIG. 5C is an external view of the semiconductor device according to the related art viewed from the back side.
  • FIG. 6 is a cross-sectional view showing the progress of peeling on the die pad of the semiconductor device according to the prior art.
  • FIG. 1A to 1C are diagrams showing a configuration of the semiconductor device according to the first embodiment.
  • FIG. 1A is a transmission plan view showing the internal structure of the semiconductor device as viewed from above
  • FIG. 1B is a cross-sectional view showing the internal structure of the semiconductor device taken along line 1B-1B in FIG. 1A
  • FIG. It is the external view of the semiconductor device seen from the side.
  • 2A to 2C are configuration diagrams showing the lead frame of the semiconductor device according to the first embodiment.
  • 2A is a plan view of the lead frame as viewed from above
  • FIG. 2B is a cross-sectional view of the lead frame taken along line 2B-2B in FIG. 2A
  • FIG. 2C is a lead taken along line 2C-2C in FIG. It is sectional drawing of a flame
  • the semiconductor device of the present invention is formed as follows. In other words, it is formed by dividing each semiconductor device from a lead frame that is integrally formed by etching from a plate-like material (for example, Cu is a main component) and connected to a plurality of semiconductor devices.
  • a plate-like material for example, Cu is a main component
  • the Each drawing shows only one semiconductor device or only one semiconductor device after being divided.
  • Each semiconductor device formed on the lead frame has a rectangular die pad 5 that supports and fixes the semiconductor element 1 and leads 3 that bridge external wiring.
  • the die pad 5 is formed at the central portion of the semiconductor device, and the lead 3 is formed at the peripheral portion of the semiconductor device.
  • An adhesive (not shown) as a die bond portion 6 is applied to the die pad 5, and the semiconductor element 1 is fixed and supported on the die pad 5 at the die bond portion 6 by this adhesive. That is, the semiconductor element 1 is mounted in a predetermined region (center portion) on the die pad 5 via the die bond portion 6.
  • the lead 3 has an internal connection portion 3a and an external terminal portion 3b.
  • the semiconductor element 1 and the internal connection portion 3a are electrically connected to each other by a first wire 2a (a metal thin wire, for example, a main component is Au). ing. That is, the first wire 2 a connects the internal connection portion 3 a on the upper surface of the lead 3 and the first electrode formed on the upper surface of the semiconductor element 1.
  • a first wire 2a a metal thin wire, for example, a main component is Au.
  • a down bond tab 8 is formed around the die pad 5. That is, in the vicinity of the die pad 5, the down bond tab 8 is arranged along the side of the die pad 5.
  • the down bond tab 8 has a rectangular upper surface, and the long side of the rectangle is along one side of the die pad. The length of the long side of the down bond tab 8 is shorter than the length of one side of the die pad 5.
  • the down bond tab 8 is formed thinner than the die pad 5 by half etching or the like so as not to be exposed from the lower surface of the semiconductor device.
  • the semiconductor device also has a die pad-tab connecting portion 9 provided with steps at a plurality of positions with respect to each side of the die pad 5.
  • the die pad 5 and the down bond tab 8 are connected by the die pad-tab connecting portion 9.
  • the bottom of the step of the die pad-tab connecting portion 9 is located lower than the surface of the die pad 5 that supports and fixes the semiconductor element 1 and the upper surface of the down bond tab 8.
  • a part of the down bond tab 8 and the central portion of the die pad 5 are connected by a die pad-tab connecting portion 9 provided so as to have a step with respect to the upper surface of the down bond tab 8 and the upper surface of the die pad 5.
  • the down bond tab 8 and the central portion of the die pad 5 are connected by a plurality of die pad-tab connecting portions 9.
  • the die pad-tab connecting portion 9 is provided between the center portion of the die pad 5 and the down bond tab 8, and the upper surface of the die pad-tab connecting portion 9 is the upper surface of the down bond tab 8 and the die pad 5. Lower than any of the top surfaces.
  • the die pad-tab connecting portion 9 constitutes the bottom of the groove formed in the die pad 5.
  • the semiconductor element 1 and the down bond tab 8 are electrically connected to each other at the down bond portion 11 by the second wire 2b (metal thin wire) as necessary. That is, the second wire 2 b connects a predetermined region on the upper surface of the down bond tab 8 and the second electrode formed on the upper surface of the semiconductor element 1.
  • the second wire 2b metal thin wire
  • the surface of the die pad 5 on which the semiconductor element 1 is mounted (center portion of the upper surface) and the surface (down bond portion 11) of the down bond tab 8 connected by the second wire 2b (metal thin wire) are on the same plane. Further, they are connected by a die pad-tab connecting portion 9 provided with a step so as not to be continuously connected.
  • the back surface of the die pad 5 is exposed from the lower surface of the semiconductor device except for the down bond tab 8.
  • each lead 3 formed integrally with the internal connection portion 3a of each lead 3 is exposed on the lower surface of the sealing resin 4 (for example, the main component is epoxy).
  • the sealing resin 4 for example, the main component is epoxy.
  • the upper surface of the die pad 5, the adhesive (not shown, for example, the main component is Ag), the semiconductor element 1, the wire 2, and the internal connection portion 3 a of the lead 3 are sealed with the sealing resin 4. It has been stopped.
  • sealing resin 4 is formed into a flat quadrangular flat plate shape, and the external terminal portions 3b of the leads 3 are exposed on the lower surface from the four sides of the sealing resin 4, respectively.
  • the sealing resin 4 exposes the bottom surface of the die pad 5 and covers the leads 3, the die pad 5, and the semiconductor element 1 including the first wire 2 a.
  • the sealing resin 4 is filled under the bottom surface of the down bond tab 8.
  • the outer surface and the bottom surface of the lead 3 are exposed from the sealing resin 4.
  • the sealing resin 4 is formed so that the outer surface of the lead 3 and the side surface of the sealing resin 4 are flush with each other.
  • the down bond tab 8 is not disposed independently of the die pad 5 but on the outer periphery of the die pad 5, that is, between the die pad 5 and the internal connection portion 3 a of the lead 3. Is desirable. That is, the downbond tab 8 and the die pad-tab connecting portion 9 are preferably formed as a part of the die pad 5.
  • FIG. 1B is a diagram showing a cross-sectional structure of the semiconductor device according to the present embodiment
  • FIG. 5B is a diagram showing a cross-sectional structure of the semiconductor device according to the conventional semiconductor device.
  • the peeling that occurs at the die bond portion 6 proceeds linearly at the interface between the die pad 5 and the sealing resin 4 due to thermal stress when the semiconductor device is mounted on the substrate.
  • the down bond part 11 is easily reached. This is because a linear interface exists between the die pad 5 and the sealing resin 4.
  • the measure for providing a gap (slit) between the die pad 5 and the sealing resin 4 described as the prior art is an effective method to some extent, as described above, the essence of the problem is that the die pad 5 and the sealing resin are sealed. Since the linear interface exists between the resin 4 and the resin 4, if the down bond part 11 and the die bond part 6 are continuously connected on the same plane, the effect of suppressing peeling is insufficient.
  • the die pad-tab connecting portion 9 needs to form a discontinuous connection on the same plane as the die bonding portion 6 as in the semiconductor device in the present embodiment.
  • all the die pad-tab connection portions 9 that connect the die pad 5 and the down bond tab 8 have steps with respect to the upper surface of the die pad 5 and the upper surface of the down bond tab 8. There are no locations where the die pad 5 and the down bond tab 8 are continuously connected in the same plane (that is, there are fewer such locations than in the conventional semiconductor device). This also has the effect that the adhesion force is increased by increasing the area where the die pad 5 (or the die pad-tab connecting portion 9) is in contact with the sealing resin 4.
  • the separation that has reached the step may propagate in the lateral direction through the connecting portion between the down bond portion 11 and the die bond portion 6, so the connecting portion between the down bond portion 11 and the die bond portion 6.
  • a minimum connecting portion is required.
  • the back side of the down bond tab 8 is etched to make it thinner than the thickness of the die pad 5, thereby suppressing resin filling in the gap.
  • the combination of the step formation of the die pad-tab connecting portion 9 and the improvement of the filling property of the sealing resin can withstand a larger thermal stress and ensure high reliability.
  • the downbond tab 8 is molded in the lead frame manufacturing process.
  • the step of the die pad-tab connecting portion 9 is also formed at the same time.
  • the step forming method is performed by etching from the upper surface after the die pad 5 is formed.
  • the step at this time is desirably half the thickness of the die pad 5 (for example, about 0.06 to 0.14 mm).
  • the downbonding tab 8 is molded by etching from the back surface of the die pad 5 in the same manner.
  • the thickness at this time is preferably half of the thickness of the die pad 5 (for example, about 0.06 to 0.14 mm) as with the step.
  • the semiconductor device may be completed according to the normal assembly flow of package products.
  • the die pad 5 is formed with a die pad-tab connecting portion 9 provided with steps at a plurality of locations, and the down bond is formed thinner than the die pad.
  • the tab 8 for use, that is, by providing a step at the connecting portion between the down bond portion 11 and the die pad 5 and separating the die pad 5 from the mounting surface of the semiconductor element 1 in a horizontal plane, It is possible to suppress the progress and unfilling of the linear delamination over the tab 8, and suppress the progress even when delamination due to thermal stress applied during mounting on the board occurs while maintaining production efficiency and cost. Reliability can be ensured.
  • FIG. 3A to 3D are configuration diagrams showing a lead frame of the semiconductor device according to the second embodiment.
  • FIG. 3A is a plan view of the lead frame as viewed from above.
  • FIG. 3B is a plan view of FIG. 3C is a cross-sectional view of the lead frame taken along line 3B
  • FIG. 3C is a cross-sectional view of the lead frame taken along line 3C-3C in FIG. 3A
  • FIG. 3D is an external view of the semiconductor device using this lead frame as viewed from the back side.
  • the down bond tabs 8 are arranged only at necessary portions (for example, three sides) of the die pad 5.
  • the same effect as in the first embodiment can be obtained. Furthermore, according to the second embodiment, it is possible to ensure a degree of freedom when mounting a plurality of semiconductor elements. For example, when a motor control semiconductor element (generally rectangular) is mounted on the left side and a memory or system control semiconductor element is mounted on the right side, the system control semiconductor element is generally a signal. There are many connections to use. Therefore, by disposing the down bond tab 8 only on the side where the semiconductor element for system control is mounted, it is possible to reduce the size of the semiconductor device without providing a useless area.
  • FIG. 4A to 4D are configuration diagrams showing a lead frame of the semiconductor device according to the third embodiment.
  • FIG. 4A is a plan view of the lead frame as viewed from above.
  • FIG. 4B is a line 4B-4B in FIG. 4A.
  • 4C is a cross-sectional view of the lead frame taken along the line 4C-4C in FIG. 4A
  • FIG. 4D is an external view of the semiconductor device using this lead frame as viewed from the back side. is there.
  • a plurality of down bond tabs 8 are arranged along one side of the die pad 5.
  • the same effect as in the first embodiment can be obtained. Furthermore, according to the third embodiment, a degree of freedom when down-bonding with a plurality of semiconductor elements can be ensured. For example, when two down bond tabs 8 are installed for one side, it is possible to suppress the influence of one electrical signal as noise on the other electrical signal. Furthermore, an increase in the surface where the sealing resin 4 and the down bond tab 8 are in contact increases the anchor effect and improves the resistance to peeling.
  • the necessary area of the down bond tab 8 can be freely set according to necessity or usage. Therefore, the present invention is a technology with excellent versatility that increases the degree of freedom of bonding between the semiconductor element 1 and the terminal of the semiconductor device and can be easily developed in other fields.
  • the semiconductor device according to the present invention has been described based on the first to third embodiments. However, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which carried out the various deformation
  • the shape of the die pad 5 is a square, but the square may be a square, a rectangle, a trapezoid, or another quadrangle. Further, the shape is not limited to a square, and may be a polygon such as a triangle, pentagon, or hexagon, or may be a circle, an ellipse, or a fan. Further, the number of semiconductor elements 1 fixed to the die pad 5 is not limited to one and may be two or more.
  • down bond tab 8 is rectangular, it is not limited to a rectangle but may be a square or another quadrangle. Further, the down bond tab 8 is not limited to a quadrangle, but may be a triangle, another polygon, a circle, an ellipse, or the like.
  • the semiconductor device of the present invention suppresses the progress of peeling and suppresses unfilling of resin while maintaining production efficiency and cost, and can obtain high assembly reliability.
  • it is represented by a QFN package.
  • a semiconductor device in which a lead frame is used in which a terminal is exposed on the back surface of the semiconductor device and a region for connecting a wire (metal thin wire) is provided on a part of the die pad, and one side of the die pad is resin-sealed. It is.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

La présente invention concerne un dispositif semi-conducteur hautement fiable permettant d'empêcher la progression du pelage et d'empêcher l'apparition de résine non remplie tout en maintenant l'efficacité de production et le coût. Le dispositif semi-conducteur comprend les éléments suivants : une pastille de puce ; un conducteur ; une languette de liaison descendante formée dans la périphérie de la pastille de puce ; un élément semi-conducteur monté sur la pastille de puce par une partie de liaison de puce ; un premier fil pour connecter un conducteur et une première électrode formée sur la surface supérieure de l'élément semi-conducteur ; et une résine d'étanchéité formée de manière à exposer la surface inférieure de la pastille de puce et à recouvrir le conducteur, la pastille de puce, et l'élément semi-conducteur comprenant le premier fil. Dans le dispositif semi-conducteur, une partie de la languette de liaison descendante et une partie centrale de la pastille de puce sont connectées par une partie de connexion de languette de pastille de puce pourvue de manière à obtenir un étage par rapport à la surface supérieure de la languette de liaison descendante et à la surface supérieure de la pastille de puce.
PCT/JP2015/002021 2014-04-17 2015-04-10 Dispositif semi-conducteur WO2015159526A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-085160 2014-04-17
JP2014085160 2014-04-17

Publications (1)

Publication Number Publication Date
WO2015159526A1 true WO2015159526A1 (fr) 2015-10-22

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002164496A (ja) * 2000-11-27 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
JP2009500841A (ja) * 2005-07-08 2009-01-08 エヌエックスピー ビー ヴィ 半導体デバイス
JP2013219373A (ja) * 2000-12-28 2013-10-24 Renesas Electronics Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002164496A (ja) * 2000-11-27 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
JP2013219373A (ja) * 2000-12-28 2013-10-24 Renesas Electronics Corp 半導体装置
JP2009500841A (ja) * 2005-07-08 2009-01-08 エヌエックスピー ビー ヴィ 半導体デバイス

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