WO2015149521A1 - 电流采样电路、方法 - Google Patents

电流采样电路、方法 Download PDF

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Publication number
WO2015149521A1
WO2015149521A1 PCT/CN2014/090733 CN2014090733W WO2015149521A1 WO 2015149521 A1 WO2015149521 A1 WO 2015149521A1 CN 2014090733 W CN2014090733 W CN 2014090733W WO 2015149521 A1 WO2015149521 A1 WO 2015149521A1
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Prior art keywords
current
proportional
source
pmos
sampling
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PCT/CN2014/090733
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English (en)
French (fr)
Inventor
宋晓贞
胡劼
张永铂
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深圳市中兴微电子技术有限公司
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Priority to EP14885839.2A priority Critical patent/EP2966460B1/en
Priority to US14/773,758 priority patent/US9766274B2/en
Publication of WO2015149521A1 publication Critical patent/WO2015149521A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0038—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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  • the present invention relates to current sampling techniques in the field of circuit design, and more particularly to a current sampling circuit and method.
  • a feedback A op ⁇ g m4 R o
  • the current sampling circuit shown in FIG. 1 first mirrors the current in the power tube M1 into the sampling tubes M2 and M3, and then passes through the closed loop negative feedback circuit formed by the operational amplifier, the transistor M4, the resistor R1, and the resistor R2, and then Sampling current output.
  • Embodiments of the present invention are desirable to provide a current sampling circuit and method having an integrated circuit
  • the structure can output the sampling current stably and accurately; and the power consumption is low and the cost is low.
  • Embodiments of the present invention provide a current sampling circuit, including: a proportional current output circuit and a fully differential common mode negative feedback circuit;
  • the proportional current output circuit is configured to calculate a current output by the power device according to a preset ratio to obtain a first proportional current and a second proportional current, and output the first proportional current and the second proportional current to the Fully differential common mode negative feedback circuit;
  • the fully differential common mode negative feedback circuit is configured to divide the first proportional current and the second proportional current by using a fully differential common mode negative feedback network and a bias current of a microampere level to obtain a first sampling current and The second sampling current and constantly outputting the first proportional current and the second proportional current.
  • the power device is implemented by using a first laterally diffused N-channel metal oxide semiconductor LDNMOS;
  • the proportional current output circuit includes: a second LD NMOS, a third LD NMOS, a fourth LD NMOS, and a fifth LD NMOS;
  • the fully differential common mode negative feedback circuit includes: a first P-channel metal oxide semiconductor PMOS, a second PMOS, a third PMOS, a fourth PMOS, a first resistor, a second resistor, a second reference current source, and a third The reference current source, the fourth reference current source, and the fifth reference current source.
  • a drain of the second LDNMOS is connected to a drain of the fourth LDNMOS and a power supply, and a gate of the second LDNMOS is respectively connected to the firstLDNMOS a gate, a gate of the third LDNMOS, and a gate driving driving voltage (hdrv_in from a gate driving circuit), a source of the second LDNMOS and a drain of the third LDNMOS, respectively a drain of the fifth LD NMOS is connected; a source of the third LD NMOS is respectively connected to a source of the first LD NMOS and a first end of the first reference current source; and a gate of the fourth LD NMOS
  • the fifth LDNMOS a gate connection, a source of the fourth LDNMOS is respectively connected to a source of the first PMOS and a source of the third PMOS in the fully differential common mode negative feedback circuit; a source of the fifth LDNMOS is respectively Connecting with a source
  • the gate of the first PMOS is connected to the gate of the second PMOS, and the drain of the first PMOS is respectively connected to the first end of the first resistor a fourth PMOS gate and a third reference current source are connected to each other; a drain of the second PMOS and a first end of the second resistor, a third PMOS gate, and a fourth reference current a first terminal of the source is connected; a drain of the third PMOS is connected to a first end of the second reference current source; a drain of the fourth PMOS is connected to a fifth reference current source; The two ends are respectively connected to the second end of the second resistor, the gate of the first PMOS, and the gate of the second PMOS; the first reference current source, the second reference current source, and the third reference The second ends of the current source, the fourth reference current source, and the fifth reference current source are all connected to a ground point;
  • the drain of the first LDNMOS is connected to the power supply.
  • the embodiment of the invention further provides a current sampling method, the method comprising:
  • the current outputted by the power device is calculated according to a preset ratio to obtain a first proportional current and a second proportional current;
  • the first proportional current and the second proportional current are separately shunted by using a fully differential common mode negative feedback network and a bias current of the microampere level to obtain a first sampling current and a second sampling current, and the first sampling is constantly outputted Current and second sampled current.
  • the current outputted by the power device is calculated according to a preset ratio, and the first proportional current and the second proportional current are obtained, including:
  • the first proportional current and the second proportional current are determined according to the current value of the proportional branch.
  • the first proportional current and the second proportional current are respectively shunted by using a fully differential common mode negative feedback network and a bias current of the microampere level to obtain a first sampling current and a second sampling current, including :
  • the first sampling current I sense+ and the second sampling current I sense- are obtained according to the following formula:
  • I sense+ I J1 -I b
  • I J1 is the first proportional current
  • I J2 is the second proportional current
  • I b is a micro-ampere bias current provided by the fully differential common mode negative feedback network.
  • a fully differential common mode negative feedback circuit composed of four PMOSs and two resistors is used to replace the closed loop negative feedback circuit composed of a transistor and an operational amplifier in the related art, thereby ensuring a fully differential common mode.
  • the gain of the feedback network is more than 60 dB, and is usually maintained at 70 to 88 dB. The larger the gain, the more stable the sampling current can be, so that the sampling current can be stably sampled.
  • the fully differential common mode negative feedback circuit in the embodiment of the present invention The structure of the closed-loop negative feedback circuit in the related art is relatively simple; and the sampling current outputted by the fully differential common-mode negative feedback circuit in the embodiment of the present invention is only related to the size of the transistor, and is not affected by the process deviation, thereby The sampling current can be accurately output.
  • the fully differential common mode negative feedback circuit in the embodiment of the present invention has a higher degree of integration than the related technology, and the occupied chip layout has a small area and a low cost;
  • the fully differential common-mode negative feedback circuit used in the embodiment of the present invention requires a small bias current, which is only micro-ampere, and usually only needs 10-20 ⁇ A, so power consumption is greatly reduced.
  • FIG. 1 is a schematic structural diagram of a current sampling circuit in a related art according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a current sampling circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a current sampling circuit in an actual application according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing an equivalent structure of a fully differential common mode feedback network according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a folding current sampling circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an implementation flow of a current sampling method according to an embodiment of the present invention.
  • the current outputted by the power device is calculated according to a preset ratio to obtain a first proportional current and a second proportional current; a fully differential common mode negative feedback circuit and a microampere bias current are applied to the first
  • the proportional current and the second proportional current are separately shunted to obtain a first sampling current and a second sampling current and are outputted constantly.
  • the embodiment of the present invention provides a current sampling circuit for performing current sampling on a power device.
  • the current sampling circuit includes: a proportional current output circuit 201 and a fully differential common mode negative feedback circuit 202;
  • the proportional current output circuit 201 is configured to preset a current output by the power device according to a preset ratio Calculating, obtaining a proportional current and outputting to the fully differential common mode negative feedback circuit 202;
  • the fully differential common mode negative feedback circuit 202 is configured to divide the first proportional current and the second proportional current by using a fully differential common mode negative feedback network and a bias current of the microampere level to obtain a first sampling current. And a second sampling current and a constant output.
  • the power device may be an N-channel metal oxide semiconductor (NMOS), a P-channel metal oxide semiconductor (PMOS), a laterally diffused N-channel metal oxide.
  • NMOS N-channel metal oxide semiconductor
  • PMOS P-channel metal oxide semiconductor
  • LDPMOS laterally diffused P-channel metal oxide semiconductor
  • PNP-type transistor an NPN-type transistor, or the like having a power output function; preferably, the embodiment of the present invention uses an LDNMOS, as shown in FIG.
  • the first LDNMOS M 1 shown is a power device.
  • the proportional current output circuit 201 includes: a second LDNMOS M 2 , a third LD NMOS M 3 , a fourth LD NMOS M 4 , and a fifth LD NMOS M 5 ;
  • the fully differential common mode negative feedback circuit 202 includes: a first PMOS M 6 , a second PMOS M 7 , a third PMOS M 8 , a fourth PMOS M 9 , a first resistor R 1 , a second resistor R 2 , and a second The reference current source I 2 , the third reference current source I 3 , the fourth reference current source I 4 , and the fifth reference current source I 5 .
  • the transistors M 2 , M 3 , M 4 , and M 5 in the proportional current output circuit 201 are all implemented by the same type of LDMOS transistors as the power transistor M 1 , and the gate voltages are all gate driving voltages (hdrv_in, The gate drive circuit outputs) drive. Therefore, each transistor operates in a linear region, which is equivalent to a resistor.
  • the maximum withstand voltage of the transistors M 1 , M 2 , M 3 , M 4 , and M 5 is 18V.
  • the transistors M 6 , M 7 , M 8 , and M 9 in the fully differential common mode negative feedback circuit 203 are all implemented by PMOS transistors having a maximum withstand voltage of 20V.
  • the transistors in the fully differential common mode negative feedback circuit 203 can also be based on actual The requirements are implemented by transistors such as NMOS, NPN, and PNP.
  • the drain of the second LDNMOS M 2 is connected to the drain of the fourth LDNMOS M 4 and the power supply V in , and the gate of the second LD NMOS M 2 said first gate LDNMOS M 1, the output of the gate and the gate drive circuit hdrv_in output circuit of the third LDNMOS (i.e., the driving voltage of the gate signal outputted from the driving circuit), the second LDNMOS M 2 a source connected to a drain of the third LDNMOS M 3 and a drain of the fifth LDNMOS M 5 ; a source of the third LDNMOS M 3 and a source of the first LDNMOS M 1 One end of a reference current source I 1 is connected; a gate of the fourth LDNMOS M 4 is connected to a gate of the fifth LDNMOS M 5 , a source of the fourth LD NMOS M 4 and the fully differential common mode The source of the first PMOS M 6 and the source of the third PMOS M
  • the gate of the first PMOS M 6 is connected to the gate of the second PMOS M 7 , the drain of the first PMOS M 6 and the first One end of a resistor R 1 , a gate of the fourth PMOS M 9 , and one end of a third reference current source I 3 are connected; a drain of the second PMOS M 7 and one end of the second resistor R 2 , and a third a gate of the PMOS M 8 and one end of the fourth reference current source I 4 are connected; a drain of the third PMOS M 8 is connected to one end of the second reference current source I 2 ; a drain of the fourth PMOS M 9 Connected to a fifth reference current source I 5 ; the other end of the first resistor R 1 and the other end of the second resistor R 2 , the gate of the first PMOS M 6 , and the second PMOS M 7 a gate connection; the other ends of the first reference current source I 1 , the second reference current source I 2 , the third reference current
  • the drain of the first LDNMOS M 1 is connected to the power supply V in .
  • the working principle of the current sampling circuit is as follows:
  • the power device first LD NMOS M 1 outputs a current I power to the proportional current output circuit 201, and the proportional current output circuit 201 calculates the output current I power according to a preset ratio to obtain a first proportional current and The second proportional current is output to the fully differential common mode negative feedback circuit 202.
  • the gate voltages of the transistors M 1 , M 2 , M 3 , M 4 , and M 5 are all driven by hdrv_in, and therefore, they all operate in the linear region, equivalent to the resistance, since the voltage V in of the input power supply is the maximum 18V, therefore, the maximum withstand voltage of the transistors M 1 , M 2 , M 3 , M 4 , and M 5 is 18V.
  • the proportional current output circuit 201 first calculates the output current I power according to a preset ratio:
  • I s1 is the current value flowing through the transistor M 2 ,
  • the first proportional current I J1 is output to the sources of the transistors M 6 and M 8 in the fully differential common mode negative feedback circuit 202
  • the second proportional current I J2 is output to the fully differential common mode negative feedback circuit 202.
  • the fully differential common mode negative feedback circuit 202 employs transistors M 6 , M 7 , M 8 , M 9 , resistors R 1 , R 2 , a second reference current source I 2 , a third reference current source I 3 , a fourth reference a fully differential common mode negative feedback network composed of a current source I 4 and a fifth reference current source I 5 , and using a third reference current source and a fourth reference current source to provide a micro-ampere level for the fully differential common mode negative feedback network
  • the bias current I b is respectively shunted to the first proportional current I J1 and the second proportional current I J2 to obtain a first sampling current I sense+ and a second sampling current I sense ⁇ ;
  • I J1 I sense+ +I 3
  • I J2 I sense- +I 4
  • I sense+ is the current flowing through the transistor M 8
  • I sense ⁇ is the current flowing through the transistor M 9
  • I 3 is the flow through
  • I 4 is the current flowing through the fourth reference current source
  • I b is the reference bias current, providing a static operating point for the transistors M 6 , M 7 , Only 10 to 20 ⁇ A are required, and therefore, the power consumption of the circuit sampling circuit of the embodiment of the present invention is greatly reduced with respect to the power consumption of the current sampling circuit in the related art.
  • the fully differential common mode negative feedback network is equivalent to the negative feedback network formed by the operational amplifier, as shown in FIG. 4; wherein the transistors M 6 , M 7 and the resistors R 1 and R 2 are formed.
  • the circuit is equivalent to an operational amplifier, and the two points C and D are regarded as the input terminals of the operational amplifier, and the double sampling current can be approximated as being connected to the input terminal and the output terminal of the operational amplifier.
  • the input terminals C, D voltage is equal to two, the output of the first sampling current I sense + through the transistor M 8 of the operational amplifier is fed back to the input of point C, the output of I sense- two sampled current feedback to the operational amplifier via the transistor M 9 D input points, so has the effect of operational amplifier feedback network, capable of providing a stable gain of said current sampling circuit, and an area occupied by the chip layout Smaller, more integrated, and less expensive.
  • V sg6 V sg7
  • V sg6 is the gate-source voltage of the transistor M 6 and V sg7 is the gate-source voltage of the transistor M 7 ; obtained by the above formulas (1), (2), (3) and (4):
  • the first sampling current I sense+ in the embodiment of the present invention is only related to the channel width and the channel length of the transistor, that is, the size of the transistor, and is not affected by the process variation, so that a sampling current with high precision can be obtained.
  • the proportional current output circuit 201 and the fully differential common mode negative feedback circuit 202 can be applied to a charger chip or a power management chip.
  • the current sampling circuit in the embodiment of the present invention may also adopt a folded structure.
  • the principle of the folded current sampling circuit is similar to the principle of the current sampling current described above, and the application has certain flexibility, as shown in FIG. 5, the current
  • the sampling current includes: a proportional current output circuit 501 and a fully differential common mode negative feedback circuit 502; wherein
  • the proportional current output circuit 501 includes: a second LDNMOS M 2 , a third LD NMOS M 3 , a fourth LD NMOS M 4 , a fifth LD NMOS M 5 , a sixth LD NMOS M 6 , a seventh LD NMOS M 7 , and an eighth LD NMOS M 8 ;
  • the fully differential common mode negative feedback circuit 502 includes: a first PMOS M 9 , a second PMOS M 10 , a third PMOS M 11 , a fourth PMOS M 12 , a fifth PMOS M 13 , a sixth PMOS M 14 , and a first Resistor R 1 , second resistor R 2 , second reference current source I 2 , third reference current source I 3 , fourth reference current source I 4 , ninth NMOS M 19 , tenth NMOS M 20 , eleventh NMOS M 21 , twelfth NMOS M 22 , thirteenth NMOS M 23 , fourteenth NMOS M 24 ;
  • the transistors M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 in the proportional current output circuit 501 are implemented by the same type of LDMOS transistors as the power transistor M 1 , and the gate voltages are both Driven for hdrv_in, therefore, both work in the linear region, equivalent to the resistor, and are implemented with tubes with a withstand voltage of 18V.
  • the voltages of the transistors M 9 , M 10 , M 11 , M 12 , M 13 , M 14 in the fully differential common mode negative feedback circuit 502 are maintained at 20V; the transistors M 19 , M 20 , M 21 , M 22 , M 23 , M 24 voltage can be appropriately adjusted to ensure the reference bias current I b required in the fully differential common mode negative feedback circuit 502, the reference bias current I b is M 10 , M 11 Provides a static working point that requires only 10 to 20 ⁇ A.
  • the transistors in the fully differential common mode negative feedback circuit 502 can also be implemented by transistors such as NMOS, NPN, and PNP according to actual needs.
  • each device in the folded current sampling circuit in the embodiment of the present invention is shown in FIG.
  • the connection relationship is specified:
  • the drain of the transistor M 2 is connected to the power supply V in , the gate of the transistor M 2 and the gate of the transistor M 1 , the gate of the transistor M 3 , and the gate of the transistor M 4
  • the gate of the transistor M 5 and the hdrv_in driving voltage are connected, the source of the transistor M 2 is connected to the drain of the transistor M 3 and the drain of the transistor M 6 in the current mirror circuit 502; the source and the transistor of the transistor M 3
  • the drain of M 4 is connected to the drain of transistor M 7 ; the source of transistor M 4 is connected to the drain of transistor M 5 and the drain of transistor M 8 in said current mirror circuit 502; the source of transistor M 5 is
  • the source of the transistor M 1 is connected to one end of the first reference current source I 1 ; the gate of the transistor M 6 is connected to the gate of the transistor M 7 and the gate of the transistor M 8 , the source of the transistor M 6 and the whole
  • the source of the transistor M 9 and the source of the transistor M 13 are connected in
  • the gate-drain of the transistor M the source of the transistor M. 9 and 21 of the transistor M 22 is connected to the drain of the transistor M and the gate of the transistor M 10.
  • the transistor the gate of M 11, M 12 is the gate of the transistor is connected; a drain connected to the drain of transistor M 1 and the resistor R 10 and transistor 21 is M; a drain of the drain transistor M 2 and the resistor R 11 and transistor M 23 of a drain connection; a drain of the transistor M 12 is connected to a source of the transistor M 23 and a drain of the transistor M 24 ; a drain of the transistor M 13 is connected to one end of the second reference current source I 2 ; a drain of the transistor M 14 One end of the fourth reference current source I 4 is connected, the gate of the transistor M 13 is connected to the drain of the transistor M 21 ; the gate of the transistor M 19 is connected to the gate of the transistor M 21 , and the drain of the transistor M 19 is connected to the transistor M The gate of 21 , the gate of transistor M 11, M 12 is the gate of the
  • the source of transistor M 22 is connected to a ground point; a source electrode of the transistor M 23 Connected to the drain of the transistor M 12 and the drain of the transistor M 24 ; the source of the transistor M 24 is connected to the ground point; the first reference current source I 1 , the second reference current source I 2 , and the fourth reference current source I 4 are connected to the other end of the ground point; the other end of the third reference current source I 3 is connected to the power supply V DD;
  • the drain of the transistor M 1 is connected to the power supply V in .
  • the folding of said current sampling circuit current of the power transistor M 1 through 501 of the two scaled proportional current output circuit, the output current of the current sampling circuit becomes relatively smaller, so that The power consumption is further reduced; the transistors M 10 , M 11 , M 13 , M 14 , the first resistor R 1 , and the second resistor R 2 form a fully differential common mode negative feedback network; the transistors M 9 , M 20 , M 21 , M 22 The M 23 and the M 24 form a folded structure, and the folded current sampling circuit in the embodiment of the present invention can be adapted to the application requirements of the low voltage domain.
  • the current sampling circuit shown in FIG. 2, FIG. 3 or FIG. 5 can be applied to various devices or devices that need to perform circuit sampling.
  • the embodiment of the present invention further provides a current sampling method. Since the principle of solving the problem is similar to the circuit and the device, the implementation process and the implementation principle of the method can be referred to the implementation of the foregoing circuit and device. The description of the process and implementation principles will not be repeated here.
  • the current sampling method provided by the embodiment of the present invention includes:
  • Step S601 calculating a current output by the power device according to a preset ratio, to obtain a first proportional current and a second proportional current;
  • I power is the current output by the power device
  • I s1 is the current value of the proportional branch
  • 2X is the preset ratio
  • Step S602 The first proportional current and the second proportional current are respectively shunted by using a fully differential common mode negative feedback network and a bias current of the microampere level to obtain a first sampling current and a second sampling current and are outputted constantly.
  • the first sampling current I sense+ and the second sampling current I sense- are respectively calculated according to the following formula:
  • I sense+ I J1 -I b
  • I J1 is the first proportional current
  • I J2 is the second proportional current
  • I b is a micro-ampere bias current provided by the fully differential common mode negative feedback network.

Abstract

一种电流采样电路及其方法，该电流采样电路包括：比例电流输出电路（201）、全差分共模负反馈电路（202）；其中，所述比例电流输出电路（201），用于对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流并输出到所述全差分共模负反馈电路（202）；所述全差分共模负反馈电路（202），用于采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流并恒定输出。

Description

电流采样电路、方法 技术领域
本发明涉及电路设计领域中的电流采样技术，尤其涉及一种电流采样电路及方法。
背景技术
相关技术中，构成高精度电流采样电路的实现方式如图1所示，该电流采样电路包括：功率管M1、采样管M2和M3、以及由运算放大器、晶体管M4、电阻R1、电阻R2构成的闭环负反馈电路；其中，R1＝R2，I1和I2为偏置电流，提供所述闭环负反馈电路的静态工作点，所述闭环负反馈电路的增益为：
Afeedback＝Aop·gm4Ro
图1所示的电流采样电路，先将功率管M1中的电流镜像到采样管M2和M3中，再通过所述运算放大器、晶体管M4、电阻R1、电阻R2构成的闭环负反馈电路，然后将采样电流输出。上述电流采样电路通过所述运算放大器的钳位作用保证第一输入电压Vn＝第二输入电压Vp，能够使输出的采样电流Iout和采样管M2和M3上流过的电流相同，从而能够稳定且精确地采样功率管M1中的电流，若功率管M1中的电流改变方向，则输出的采样电流的方向也会改变，从而可以实现双向电流的精确采样。
相关技术的电流采样方案中存在以下问题：1)不利于在集成度高的大规模电路中应用；2)电流采样电路功耗大不利于节能。
发明内容
本发明实施例期望提供一种电流采样电路及方法，既具有集成化电路 结构，又能够稳定、精确地输出采样电流；且功耗低、成本低。
本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种电流采样电路，包括：比例电流输出电路、全差分共模负反馈电路；其中，
所述比例电流输出电路，用于对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流，并输出所述第一比例电流及所述第二比例电流到所述全差分共模负反馈电路；
所述全差分共模负反馈电路，用于采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流，并恒定输出所述第一比例电流和所述第二比例电流。
上述方案中，所述功率器件采用第一横向扩散N沟道金属氧化物半导体LDNMOS实现；
所述比例电流输出电路包括：第二LDNMOS、第三LDNMOS、第四LDNMOS、第五LDNMOS；
所述全差分共模负反馈电路包括：第一P沟道金属氧化物半导体PMOS、第二PMOS、第三PMOS、第四PMOS、第一电阻、第二电阻、第二参考电流源、第三参考电流源、第四参考电流源、第五参考电流源。
上述方案中，在所述比例电流输出电路中，所述第二LDNMOS的漏极与所述第四LDNMOS的漏极及供电电源连接，所述第二LDNMOS的栅极分别与所述第一LDNMOS的栅极、所述第三LDNMOS的栅极及栅极驱动驱动电压(hdrv_in，来自与栅极驱动电路)连接，所述第二LDNMOS的源极分别与所述第三LDNMOS的漏极、及所述第五LDNMOS的漏极连接；所述第三LDNMOS的源极分别与所述第一LDNMOS的源极、及第一参考电流源的第一端连接；所述第四LDNMOS的栅极与所述第五LDNMOS的 栅极连接，所述第四LDNMOS的源极分别与所述全差分共模负反馈电路中的第一PMOS的源极、及第三PMOS的源极连接；所述第五LDNMOS的源极分别与所述全差分共模负反馈电路中的第二PMOS的源极、及第四PMOS的源极连接；
在所述全差分共模负反馈电路中，所述第一PMOS的栅极与所述第二PMOS的栅极连接，所述第一PMOS的漏极分别与所述第一电阻的第一端、第四PMOS的栅极及第三参考电流源的第一端连接；所述第二PMOS的漏极分别与所述第二电阻的第一端、第三PMOS的栅极及第四参考电流源的第一端连接；所述第三PMOS的漏极与第二参考电流源的第一端连接；所述第四PMOS的漏极与第五参考电流源连接；所述第一电阻的第二端分别与所述第二电阻的第二端、所述第一PMOS的栅极及所述第二PMOS的栅极连接；所述第一参考电流源、第二参考电流源、第三参考电流源、第四参考电流源、第五参考电流源的第二端均连接接地点；
所述第一LDNMOS的漏极连接至所述供电电源。
根据上述电流采样电路，本发明实施例还提供了一种电流采样方法，该方法包括：
对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流；
采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流得到第一采样电流及第二采样电流，并恒定输出所述第一采样电流及第二采样电流。
上述方案中，所述对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流，包括：
计算功率器件输出的电流与预设比例的比值，将得到的比值作为比例支路的电流值；
根据比例支路的电流值确定第一比例电流及第二比例电流。
上述方案中，所述采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流，包括：
按照如下公式得到第一采样电流Isense+及第二采样电流Isense-：
Isense+＝IJ1-Ib
Isense-＝IJ2-Ib
其中，IJ1为所述第一比例电流，IJ2为所述第二比例电流，Ib为全差分共模负反馈网络提供的微安级的偏置电流。
本发明实施例所提供的电流采样电路及方法，与相关技术相比，取得了如下进步：
1)本发明实施例采用由四个PMOS以及两个电阻构成的全差分共模负反馈电路，来代替相关技术中由晶体管及运算放大器构成的闭环负反馈电路，如此，能够保证全差分共模反馈网络的增益达到60dB以上，通常维持在70至88dB，增益越大越能保证采样电流稳定输出，从而能实现稳定地采样电流输出；另外，本发明实施例中的全差分共模负反馈电路的结构相对于相关技术中的闭环负反馈电路的结构较为简单；并且，本发明实施例中的全差分共模负反馈电路输出的采样电流仅与晶体管的尺寸有关，不受工艺偏差的影响，从而能够精确地输出采样电流。
2)本发明实施例中的全差分共模负反馈电路相比相关技术集成化程度高，占用的芯片版图的面积较小、成本较低；
3)本发明实施例采用的全差分共模负反馈电路需要的偏置电流较小，只有微安级，通常只需要10-20μA，因此功耗大大降低。
附图说明
图1为本发明实施例相关技术中的电流采样电路的组成结构示意图；
图2为本发明实施例电流采样电路的组成结构示意图；
图3为本发明实施例实际应用中电流采样电路的组成结构示意图；
图4为本发明实施例全差分共模反馈网络的等效结构示意图；
图5为本发明实施例折叠式电流采样电路的组成结构示意图；
图6为本发明实施例电流采样方法的实现流程示意图。
具体实施方式
发明人在实现本发明的过程中，发现相关技术的电流采样方案中，至少存在以下缺陷：
1)上述电流采样电路中，为提供闭环负反馈电路的主要增益，需要在所述运算放大器的钳位上增加一个误差放大器或调整管，这样，就会使由运算放大器、以及误差放大器或调整管组成的闭环负反馈电路占用芯片版图的面积太大，需要较大芯片版图面积的开销，因此，上述电流采样电路不利于在集成度高的大规模电路中应用；
2)上述电流采样电路中，闭环负反馈电路需要的偏置电流I1和I2较大，达到安培级或毫安级，因此，上述电流采样电路需要的功耗大，不利于目前节能的发展趋势。
本发明实施例中，对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流；采用全差分共模负反馈电路及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流并恒定输出。
下面结合附图对本发明具体实施方式作进一步说明。
本发明实施例提出了一种电流采样电路，用于对功率器件进行电流采样，如图2所示，该电流采样电路包括：比例电流输出电路201、全差分共模负反馈电路202；其中，
所述比例电流输出电路201，用于对功率器件输出的电流按照预设比例 计算，得到比例电流并输出到所述全差分共模负反馈电路202；
所述全差分共模负反馈电路202，用于采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流并恒定输出。
这里，所述功率器件可以是N沟道金属氧化物半导体(Negative channel Metal Oxide Semiconductor，NMOS)、P沟道金属氧化物半导体(Positive channel Metal Oxide Semiconductor，PMOS)、横向扩散N沟道金属氧化物半导体(LDNMOS)、横向扩散P沟道金属氧化物半导体(LDPMOS)、PNP型三极管、NPN型三极管等具有功率输出功能的晶体管实现；优选的，本发明实施例中采用LDNMOS实现，如图3中所示第一LDNMOS M1即为功率器件。
下面在实际应用中结合图3所示的电流采样电路分别对比例电流输出电路201、全差分共模负反馈电路202的具体组成结构进行详细说明：
所述比例电流输出电路201包括：第二LDNMOS M2、第三LDNMOS M3、第四LDNMOS M4、第五LDNMOS M5；
所述全差分共模负反馈电路202包括：第一PMOS M6、第二PMOS M7、第三PMOS M8、第四PMOS M9、第一电阻R1、第二电阻R2、第二参考电流源I2、第三参考电流源I3、第四参考电流源I4、第五参考电流源I5。
这里，所述比例电流输出电路201中的晶体管M2、M3、M4、M5均采用与功率管M1相同类型的LDMOS晶体管实现，栅极电压均为栅极驱动电压(hdrv_in，由栅极驱动电路输出)驱动，因此，各个晶体管均工作在线性区，等效于电阻，晶体管M1、M2、M3、M4、M5的最大耐压均为18V。
这里，所述全差分共模负反馈电路203中的晶体管M6、M7、M8、M9均采用最大耐压为20V的PMOS晶体管实现。
这里，所述全差分共模负反馈电路203中的晶体管，也可以根据实际 需求采用NMOS、NPN、PNP等晶体管实现。
进一步的，结合图2所示，对本发明实施例电流采样电路中各器件的连接关系进行具体说明:
在所述比例电流输出电路201中，所述第二LDNMOS M2的漏极与所述第四LDNMOS M4的漏极及供电电源Vin连接，所述第二LDNMOS M2的栅极与所述第一LDNMOS M1的栅极、所述第三LDNMOS的栅极及栅极驱动电路输出电路的输出端hdrv_in(即由栅极驱动电路输出的电压信号驱动)，所述第二LDNMOS M2的源极与所述第三LDNMOS M3的漏极及所述第五LDNMOS M5的漏极连接；所述第三LDNMOS M3的源极与所述第一LDNMOS M1的源极及第一参考电流源I1的一端连接；所述第四LDNMOS M4的栅极与所述第五LDNMOS M5的栅极连接，所述第四LDNMOS M4的源极与所述全差分共模负反馈电路202中的第一PMOS M6的源极及第三PMOS M8的源极连接；所述第五LDNMOS M5的源极与所述全差分共模负反馈电路202中的第二PMOS M7的源极及第四PMOS M9的源极连接；
在所述全差分共模负反馈电路202中，所述第一PMOS M6的栅极与所述第二PMOS M7的栅极连接，所述第一PMOS M6的漏极与所述第一电阻R1的一端、第四PMOS M9的栅极及第三参考电流源I3的一端连接；所述第二PMOS M7的漏极与所述第二电阻R2的一端、第三PMOS M8的栅极及第四参考电流源I4的一端连接；所述第三PMOS M8的漏极与第二参考电流源I2的一端连接；所述第四PMOS M9的漏极与第五参考电流源I5连接；所述第一电阻R1的另一端与所述第二电阻R2的另一端、所述第一PMOS M6的栅极及所述第二PMOS M7的栅极连接；所述第一参考电流源I1、第二参考电流源I2、第三参考电流源I3、第四参考电流源I4、第五参考电流源I5的另一端均连接接地点；
所述第一LDNMOS M1的漏极连接至所述供电电源Vin。
本发明实施例中，基于上述电路组成结构及器件间的连接关系，所述电流采样电路的工作原理是这样的：
首先，所述功率器件第一LDNMOS M1输出电流Ipower到所述比例电流输出电路201中，所述比例电流输出电路201对输出电流Ipower按照预设比例进行计算，得到第一比例电流及第二比例电流并输出到所述全差分共模负反馈电路202。
这里，晶体管M1、M2、M3、M4、M5的栅极电压均为hdrv_in驱动，因此，均工作在线性区，等效于电阻，由于输入的供电电源的电压Vin最大为18V，因此，晶体管M1、M2、M3、M4、M5的最大耐压均为18V。
这里，晶体管的电导
Figure PCTCN2014090733-appb-000001
其中，μ·Cox为晶体管的常数因子，Vgs为晶体管的栅源电压，Vth为晶体管的阈值电压，Vds为晶体管的漏源电压，W为沟道宽度，L为沟道长度；由于晶体管的电导
Figure PCTCN2014090733-appb-000002
因此，可以通过设置晶体管的沟道宽度及沟道长度，来调节晶体管的电导G的大小；本发明实施例中，预设晶体管M1、M2、M3、M4、M5的电导G1＝X×G2＝X×G3；G2＝G3＝Y×G4＝Y×G5；其中，X、Y为预设的比例常数。
具体的，所述比例电流输出电路201先对输出电流Ipower按照预设比例进行计算得到：
Figure PCTCN2014090733-appb-000003
其中，Is1为流过晶体管M2的电流值，
Figure PCTCN2014090733-appb-000004
分别为晶体管M1、M2、M3的电阻值；
再将得到的电流Is1输出到晶体管M3、M5的漏极，从而得到流过晶体 管M4的第一比例电流IJ1，及流过晶体管M5的第二比例电流IJ2，将所述第一比例电流IJ1输出到所述全差分共模负反馈电路202中的晶体管M6及M8的源极，将第二比例电流IJ2输出到所述全差分共模负反馈电路202中的晶体管M7及M9的源极；由于所述晶体管M4和M5具有隔离高压的作用，这样能够使所述全差分共模负反馈电路202避免高压击穿的危险。
最终，全差分共模负反馈电路202采用晶体管M6、M7、M8、M9，电阻R1、R2，第二参考电流源I2、第三参考电流源I3、第四参考电流源I4、第五参考电流源I5构成的全差分共模负反馈网络，并采用第三参考电流源及第四参考电流源为所述全差分共模负反馈网络提供的微安级的偏置电流Ib，对所述第一比例电流IJ1及第二比例电流IJ2分别进行分流，得到第一采样电流Isense+及第二采样电流Isense-；
其中，IJ1＝Isense++I3，IJ2＝Isense-+I4，Isense+为流过晶体管M8的电流，Isense-为流过晶体管M9的电流，I3为流过第三参考电流源的电流，I4为流过第四参考电流源的电流，且I3＝I4＝Ib，Ib为基准偏置电流，为晶体管M6、M7提供静态工作点，仅需要10至20μA，因此，本发明实施例的电路采样电路的功耗相对于相关技术中的电流采样电路的功耗大大降低。
本发明的上述实施例中，全差分共模负反馈网络等效于运算放大器构成的负反馈网络，如图4所示；其中，晶体管M6、M7、以及电阻R1、R2构成的电路等效于运算放大器，C、D两点看作所述运算放大器的输入端，双采样电流可近似看作连接在所述运算放大器的输入端及输出端。由于所述运算放大器的钳位作用，所述输入端C、D两点的电压相等，输出端的第一采样电流Isense+通过晶体管M8反馈到所述运算放大器的输入端C点，输出端的第二采样电流Isense-通过晶体管M9反馈到所述运算放大器的输入端D点，从而具有运放反馈网络的作用，能够为所述电流采样电路提供稳定的增益，并且占用的芯片版图的面积较小、集成化程度高、成本较低。
这里，当晶体管M1中流过的电流向下时，晶体管M8所在支路流过正向的第一采样电流Isense+，晶体管M9中流过负向的第二采样电流Isense-为0；反之，当晶体管M1中流过的电流是向上即反向时，晶体管M8所在支路流过正向的第一采样电流Isense+为0，晶体管M9中流过负向的第二采样电流Isense-，且Isense+＝Isense-，两条支路分别工作，互不干扰，从而实现双向电流的采样。
下面以正向的采样为例，详细说明本发明实施例中如何得到正向的第一采样电流Isense+，从A点到G点列出的基尔霍夫电压定律KVL方程为：
Figure PCTCN2014090733-appb-000005
Vsg6＝Vsg7
(3)
IJ1＝Ib+Isense+
(4)
其中，Vsg6为晶体管M6的栅源电压，Vsg7为晶体管M7的栅源电压；由以上(1)、(2)、(3)及(4)式子得到：
Figure PCTCN2014090733-appb-000006
由此可见，本发明实施例中的第一采样电流Isense+仅仅与晶体管的沟道宽度及沟道长度，即晶体管的尺寸有关，不受工艺偏差的影响，从而能够得到精度高的采样电流。
本发明实施例中，负向的第二采样电流Isense-的计算方法与正向的第一采样电流Isense+的计算方法类似；并且，负向时的第二采样电流与正向时的第一采样电流相等，即：第二采样电流Isense-＝Ipower/(2XY)，重复之处不再赘述。
在实际应用中，所述比例电流输出电路201、全差分共模负反馈电路 202可应用于充电器芯片或电源管理芯片中。
本发明实施例中的电流采样电路也可以采用折叠式结构，所述折叠式电流采样电路的原理与上述电流采样电流的原理类似，其应用具有一定的灵活性，如图5所示，该电流采样电流包括：比例电流输出电路501、全差分共模负反馈电路502；其中，
所述比例电流输出电路501包括：第二LDNMOS M2、第三LDNMOS M3第四LDNMOS M4、第五LDNMOS M5、第六LDNMOS M6、第七LDNMOS M7、第八LDNMOS M8；
所述全差分共模负反馈电路502包括：第一PMOS M9、第二PMOS M10、第三PMOS M11、第四PMOS M12、第五PMOS M13、第六PMOS M14、第一电阻R1、第二电阻R2、第二参考电流源I2、第三参考电流源I3、第四参考电流源I4、第九NMOS M19、第十NMOS M20、第十一NMOS M21、第十二NMOS M22、第十三NMOS M23、第十四NMOS M24；
这里，所述比例电流输出电路501中的晶体管M2、M3、M4、M5、M6、M7、M8均采用与功率管M1相同类型的LDMOS晶体管实现，栅极电压均为hdrv_in驱动，因此，均工作在线性区，等效于电阻，均采用耐压为18V的管子实现。
这里，所述全差分共模负反馈电路502中的晶体管M9、M10、M11、M12、M13、M14的电压均保持在20V；晶体管M19、M20、M21、M22、M23、M24的电压可以适当调整，以保证所述全差分共模负反馈电路502中所需的基准偏置电流Ib，所述基准偏置电流Ib为M10、M11提供静态工作点，仅需要10至20μA。
这里，所述全差分共模负反馈电路502中的晶体管，也可以根据实际需求采用NMOS、NPN、PNP等晶体管实现。
下面结合图5所示对本发明实施例中的折叠式电流采样电路中各器件 的连接关系进行具体说明:
在所述比例电流输出电路501中，晶体管M2的漏极与供电电源Vin连接，晶体管M2的栅极与晶体管M1的栅极、晶体管M3的栅极、晶体管M4的栅极、晶体管M5的栅极及hdrv_in驱动电压连接，晶体管M2的源极与晶体管M3的漏极及所述电流镜像电路502中晶体管M6的漏极连接；晶体管M3的源极与晶体管M4的漏极及晶体管M7的漏极连接；晶体管M4的源极与晶体管M5的漏极及所述电流镜像电路502中晶体管M8的漏极连接；晶体管M5的源极与晶体管M1的源极及第一参考电流源I1的一端连接；晶体管M6的栅极与晶体管M7的栅极及晶体管M8的栅极连接，晶体管M6的源极与所述全差分共模负反馈电路502中晶体管M9的源极及晶体管M13的源极连接；晶体管M7的源极与所述全差分共模负反馈电路502中晶体管M10的源极及晶体管M11的源极连接；晶体管M8的源极与所述全差分共模负反馈电路502中晶体管M12的源极及晶体管M14的源极连接；
在所述全差分共模负反馈电路502中，晶体管M9的漏极与晶体管M21的源极及晶体管M22的漏极连接，晶体管M9的栅极与晶体管M10的栅极、晶体管M11的栅极、晶体管M12的栅极均连接；晶体管M10的漏极与电阻R1及晶体管M21的漏极连接；晶体管M11的漏极与电阻R2及晶体管M23的漏极连接；晶体管M12的漏极与晶体管M23的源极及晶体管M24的漏极连接；晶体管M13的漏极与第二参考电流源I2的一端连接；晶体管M14的漏极与第四参考电流源I4的一端连接，晶体管M13的栅极与晶体管M21的漏极连接；晶体管M19的栅极与晶体管M21的栅极连接，晶体管M19的漏极与晶体管M21的栅极、晶体管M23的栅极及第三参考电流源I3的一端连接，晶体管M19的漏极与晶体管M20的漏极、晶体管M22的栅极、晶体管M24的栅极连接；晶体管M20的源极连接接地点，晶体管M20的栅极与晶体管M22的栅极及晶体管M24的栅极连接；晶体管M21的源极与晶体管M9的漏极及晶体 管M22的漏极连接；晶体管M22的源极连接接地点；晶体管M23的源极与晶体管M12的漏极及晶体管M24的漏极连接；晶体管M24的源极连接接地点；所述第一参考电流源I1、第二参考电流源I2、第四参考电流源I4的另一端均连接接地点；所述第三参考电流源I3的另一端连接供电电源VDD；
晶体管M1的漏极连接至所述供电电源Vin。
本发明的上述实施例中，所述的折叠式电流采样电路中功率管M1的电流经过所述比例电流输出电路501两次缩放，输出的电流变得相对上述电流采样电路更小，从而使功耗进一步降低；晶体管M10、M11、M13、M14、第一电阻R1、第二电阻R2构成全差分共模负反馈网络；晶体管M9、M20、M21、M22、M23、M24构成折叠式的结构，本发明实施例中的折叠式电流采样电路可以适应低电压域的应用需求。
本发明实施例中，图2、图3或图5所示的电流采样电路，可应用于各种需要进行电路采样的装置或设备中。
基于相同的技术构思，本发明实施例还提供了一种电流采样方法，由于该方法解决问题的原理与电路、装置相似，因此，方法的实施过程及实施原理均可以参见前述电路、装置的实施过程及实施原理描述，重复之处不再赘述。
如图6所示，本发明实施例提供的电流采样方法，该方法包括：
步骤S601：对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流；
具体的，先根据Is1＝Ipower/2X计算功率器件输出的电流与预设比例的比值，并将得到的比值作为比例支路的电流值；再根据比例支路的电流值确定第一比例电流及第二比例电流；
其中，Ipower为功率器件输出的电流；Is1为比例支路的电流值，2X为预设比例。
步骤S602：采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流并恒定输出。
具体的，按照如下公式分别计算得到第一采样电流Isense+及第二采样电流Isense-：
Isense+＝IJ1-Ib
Isense-＝IJ2-Ib
其中，IJ1为所述第一比例电流，IJ2为所述第二比例电流，Ib为全差分共模负反馈网络提供的微安级的偏置电流。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (6)

  1. 一种电流采样电路，所述电流采样电路包括：比例电流输出电路、全差分共模负反馈电路；其中，
    所述比例电流输出电路，用于对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流，并输出所述第一比例电流及所述第二比例电流到所述全差分共模负反馈电路；
    所述全差分共模负反馈电路，用于采用全差分共模负反馈网络及微安级的偏置电流，对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流，并恒定输出所述第一比例电流和所述第二比例电流。
  2. 根据权利要求1所述的电流采样电路，其中，所述功率器件采用第一横向扩散N沟道金属氧化物半导体LDNMOS实现；
    所述比例电流输出电路包括：第二LDNMOS、第三LDNMOS、第四LDNMOS、第五LDNMOS；
    所述全差分共模负反馈电路包括：第一P沟道金属氧化物半导体PMOS、第二PMOS、第三PMOS、第四PMOS、第一电阻、第二电阻、第二参考电流源、第三参考电流源、第四参考电流源、第五参考电流源。
  3. 根据权利要求2所述的电流采样电路，其中，
    在所述比例电流输出电路中，所述第二LDNMOS的漏极与所述第四LDNMOS的漏极及供电电源连接，所述第二LDNMOS的栅极与所述第一LDNMOS的栅极、所述第三LDNMOS的栅极及栅极驱动电压连接，所述第二LDNMOS的源极分别与所述第三LDNMOS的漏极、及所述第五LDNMOS的漏极连接；所述第三LDNMOS的源极分别与所述第一LDNMOS的源极、及第一参考电流源的第一端连接；所述第四LDNMOS的栅极与所述第五LDNMOS的栅极连接，所述第四LDNMOS的源极分别 与所述全差分共模负反馈电路中的第一PMOS的源极、及第三PMOS的源极连接；所述第五LDNMOS的源极分别与所述全差分共模负反馈电路中的第二PMOS的源极、及第四PMOS的源极连接；
    在所述全差分共模负反馈电路中，所述第一PMOS的栅极与所述第二PMOS的栅极连接，所述第一PMOS的漏极分别与所述第一电阻的第一端、第四PMOS的栅极及第三参考电流源的第一端连接；所述第二PMOS的漏极分别与所述第二电阻的第一端、第三PMOS的栅极及第四参考电流源的第一端连接；所述第三PMOS的漏极与第二参考电流源的第一端连接；所述第四PMOS的漏极与第五参考电流源连接；所述第一电阻的第二端分别与所述第二电阻的第二端、所述第一PMOS的栅极及所述第二PMOS的栅极连接；所述第一参考电流源、第二参考电流源、第三参考电流源、第四参考电流源、第五参考电流源的第二端均连接接地点；
    所述第一LDNMOS的漏极连接至所述供电电源。
  4. 一种电流采样方法，所述方法包括：
    对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流；
    采用全差分共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流，并恒定输出所述第一比例电流和所述第二比例电流。
  5. 根据权利要求4所述的电流采样方法，其中，所述对功率器件输出的电流按照预设比例计算，得到第一比例电流及第二比例电流，包括：
    计算功率器件输出的电流与预设比例的比值，并将得到的比值作为比例支路的电流值；
    根据比例支路的电流值确定第一比例电流及第二比例电流。
  6. 根据权利要求4或5所述的电流采样方法，其中，所述采用全差分 共模负反馈网络及微安级的偏置电流对所述第一比例电流及第二比例电流分别进行分流，得到第一采样电流及第二采样电流，包括：
    按照如下公式得到第一采样电流Isense+及第二采样电流Isense-：
    Isense+＝IJ1-Ib
    Isense-＝IJ2-Ib
    其中，IJ1为所述第一比例电流，IJ2为所述第二比例电流，Ib为全差分共模负反馈网络提供的微安级的偏置电流。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117388561A (zh) * 2023-12-07 2024-01-12 苏州锴威特半导体股份有限公司 一种宽电压范围的电流检测电路和开关电源

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017063300A (ja) * 2015-09-24 2017-03-30 エスアイアイ・セミコンダクタ株式会社 入力回路
CN106908647A (zh) * 2015-12-23 2017-06-30 深圳市盛德金科技有限公司 电流检测电路
CN106415282B (zh) * 2016-08-16 2019-06-21 深圳市汇顶科技股份有限公司 一种电流采样保持电路及信号采集系统
CN107589296B (zh) * 2017-10-23 2021-02-26 宁德时代新能源科技股份有限公司 高压回路的信号采集装置、检测器、电池装置和运载工具
CN112946351B (zh) * 2019-12-11 2023-04-11 圣邦微电子（北京）股份有限公司 一种负向续流电流监测电路
CN111308161B (zh) * 2020-03-10 2022-04-19 福州瑞芯微电子股份有限公司 一种电压采样电路及方法
US20230275502A1 (en) * 2022-02-25 2023-08-31 Stmicroelectronics Asia Pacific Pte Ltd Vertical metal sensing method for dc-dc converter
CN115184663B (zh) * 2022-08-17 2023-06-09 上海紫鹰微电子有限公司 双向高精度nmos功率管电流采样电路及方法
CN115656609B (zh) * 2022-12-28 2023-04-28 苏州博创集成电路设计有限公司 一种电感电流采样电路
CN117310253A (zh) * 2023-09-20 2023-12-29 上海帝迪集成电路设计有限公司 一种宽范围高精度电流检测电路及其检测方法
CN117517753B (zh) * 2024-01-03 2024-03-29 江苏帝奥微电子股份有限公司 采用电阻采样且兼容p、n型功率管的电流采样电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4464591A (en) * 1982-06-23 1984-08-07 National Semiconductor Corporation Current difference sense amplifier
US5374857A (en) * 1992-05-29 1994-12-20 Sgs-Thomson Microelectronics, Inc. Circuit for providing drive current to a motor using a sensefet current sensing device and a fast amplifier
CN101821852A (zh) * 2007-08-08 2010-09-01 先进模拟科技公司 用于分立功率半导体器件的共源共栅电流传感器
CN202374224U (zh) * 2011-12-26 2012-08-08 苏州云芯微电子科技有限公司 基于共模反馈的可变增益自适应偏置功率放大器
CN202794314U (zh) * 2012-07-19 2013-03-13 快捷半导体(苏州)有限公司 一种功率开关管的过流检测电路
CN103558445A (zh) * 2013-11-13 2014-02-05 丹纳赫（上海）工业仪器技术研发有限公司 电流检测电路以及测量装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710726A (en) * 1986-02-27 1987-12-01 Columbia University In The City Of New York Semiconductive MOS resistance network
US4918338A (en) * 1988-10-04 1990-04-17 North American Philips Corporation Drain-biassed transresistance device for continuous time filters
CN1025093C (zh) * 1993-01-19 1994-06-15 天津市无线电元件五厂 一种互补共模稳流复合射极电压跟随器
US5508570A (en) * 1993-01-27 1996-04-16 Micro Linear Corporation Differential amplifier based integrator having a left-half plane pole
US5585746A (en) 1995-09-28 1996-12-17 Honeywell Inc. Current sensing circuit
US5815012A (en) * 1996-08-02 1998-09-29 Atmel Corporation Voltage to current converter for high frequency applications
EP0861492A1 (en) * 1996-09-13 1998-09-02 Koninklijke Philips Electronics N.V. Thin-film resistor and resistance material for a thin-film resistor
US6566949B1 (en) * 2000-08-31 2003-05-20 International Business Machines Corporation Highly linear high-speed transconductance amplifier for Gm-C filters
US6437645B1 (en) * 2001-02-15 2002-08-20 Texas Instruments Incorporated Slew rate boost circuitry and method
US7145384B2 (en) * 2004-07-13 2006-12-05 M/A-Com, Inc. Pulse length matched filter
TW200629738A (en) * 2004-10-12 2006-08-16 Sony Corp Sample hold circuit, and pipeline ad converter using the circuit
JP2006115003A (ja) * 2004-10-12 2006-04-27 Sony Corp サンプルホールド回路およびそれを用いたパイプラインａｄ変換器
US7164317B1 (en) * 2004-12-03 2007-01-16 National Semiconductor Corporation Apparatus and method for a low-voltage class AB amplifier with split cascode
US7221209B2 (en) * 2005-05-12 2007-05-22 Intersil Americas, Inc Precision floating gate reference temperature coefficient compensation circuit and method
KR101221799B1 (ko) * 2005-11-21 2013-01-14 페어차일드코리아반도체 주식회사 전류감지 회로 및 이를 구비한 부스트 컨버터
JP4354473B2 (ja) * 2006-09-07 2009-10-28 株式会社半導体理工学研究センター 容量帰還型チョッパ増幅回路
US7671676B2 (en) * 2006-09-12 2010-03-02 Stmicroelectronics Pvt. Ltd. Continuous time common-mode feedback module and method with wide swing and good linearity
US7642851B2 (en) * 2007-06-25 2010-01-05 Metalink Ltd. Variable gain amplifier insensitive to process voltage and temperature variations
US8786359B2 (en) * 2007-12-12 2014-07-22 Sandisk Technologies Inc. Current mirror device and method
CN101629973B (zh) * 2009-06-09 2011-04-20 中国人民解放军国防科学技术大学 适用于低电压供电的无运放高精度电流采样电路
JP2011220767A (ja) * 2010-04-07 2011-11-04 Panasonic Corp 電流検出回路
US8816722B2 (en) * 2010-09-13 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Current detection circuit
CN103575964B (zh) * 2012-07-19 2016-03-23 快捷半导体(苏州)有限公司 一种功率开关管的过流检测电路和方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4464591A (en) * 1982-06-23 1984-08-07 National Semiconductor Corporation Current difference sense amplifier
US5374857A (en) * 1992-05-29 1994-12-20 Sgs-Thomson Microelectronics, Inc. Circuit for providing drive current to a motor using a sensefet current sensing device and a fast amplifier
CN101821852A (zh) * 2007-08-08 2010-09-01 先进模拟科技公司 用于分立功率半导体器件的共源共栅电流传感器
CN202374224U (zh) * 2011-12-26 2012-08-08 苏州云芯微电子科技有限公司 基于共模反馈的可变增益自适应偏置功率放大器
CN202794314U (zh) * 2012-07-19 2013-03-13 快捷半导体(苏州)有限公司 一种功率开关管的过流检测电路
CN103558445A (zh) * 2013-11-13 2014-02-05 丹纳赫（上海）工业仪器技术研发有限公司 电流检测电路以及测量装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117388561A (zh) * 2023-12-07 2024-01-12 苏州锴威特半导体股份有限公司 一种宽电压范围的电流检测电路和开关电源
CN117388561B (zh) * 2023-12-07 2024-03-01 苏州锴威特半导体股份有限公司 一种宽电压范围的电流检测电路和开关电源

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EP2966460A1 (en) 2016-01-13
CN104977450A (zh) 2015-10-14
US20160109487A1 (en) 2016-04-21

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