WO2015143852A1 - 一种具有占空比限制功能的d类功放芯片及其装置 - Google Patents

一种具有占空比限制功能的d类功放芯片及其装置 Download PDF

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Publication number
WO2015143852A1
WO2015143852A1 PCT/CN2014/087028 CN2014087028W WO2015143852A1 WO 2015143852 A1 WO2015143852 A1 WO 2015143852A1 CN 2014087028 W CN2014087028 W CN 2014087028W WO 2015143852 A1 WO2015143852 A1 WO 2015143852A1
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Prior art keywords
mos transistor
gate
drain
twenty
class
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PCT/CN2014/087028
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English (en)
French (fr)
Inventor
左事君
杨智昌
吴冰洁
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深圳创维－Rgb电子有限公司
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Application filed by 深圳创维－Rgb电子有限公司 filed Critical 深圳创维－Rgb电子有限公司
Priority to US14/618,813 priority Critical patent/US10070218B2/en
Priority to RU2015120265/08A priority patent/RU2598336C1/ru
Priority to AU2014295834A priority patent/AU2014295834B2/en
Publication of WO2015143852A1 publication Critical patent/WO2015143852A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/007—Protection circuits for transducers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/185—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/171—A filter circuit coupled to the output of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/426—Indexing scheme relating to amplifiers the amplifier comprising circuitry for protection against overload
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/78—A comparator being used in a controlling circuit of an amplifier

Definitions

  • the present invention relates to the field of power supply technologies, and in particular, to a class D power amplifier chip having a duty ratio limiting function and an apparatus therefor.
  • Class D power amplifiers are switch-type power amplifiers, which have the advantages of high efficiency and low heat generation, and are widely used in consumer electronics such as smart TVs and smart phones.
  • a common class D power amplifier (the internal structure of the class D power amplifier chip in the dotted line frame) includes: an amplifier AMPa, a comparator CMPa, a comparator CMPb, a driver a, and a driver b; the connection relationship is as shown in FIG. .
  • the working principle of the class D power amplifier is based on the PWM mode.
  • the differential audio signal is amplified by the amplifier AMPa and input into the comparator CMPa and the comparator CMPb in two ways, and compared with the input triangular wave signal to obtain the corresponding two PWM signals. Then, the amplitudes of the two PWM signals are amplified by the driver a and the driver b, respectively, and finally the filter is restored to an audio signal, and the speaker vibration is driven to emit a sound.
  • the amplitude of the input differential audio signal When the amplitude of the input differential audio signal is too large, the amplitude of the restored audio signal exceeds the rated value of the speaker, or the input capacitor Ca or the input capacitor Cb is short-circuited, resulting in the restored audio signal being a DC component, which may burn. Bad speaker. In order to avoid such anomalies, it is necessary to limit the output amplitude of the class D amplifier. Since the pulse width (ie, duty cycle) of the PWM signal is proportional to the amplitude of the audio signal, the output amplitude of the audio signal can be limited by limiting the duty cycle of the PWM signal.
  • an object of the present invention is to provide a class D power amplifier chip having a duty limit function and a device thereof, so as to solve the problem that the existing class D power amplifier cannot limit the output amplitude of the audio signal, and the PWM signal The problem of burning out the speaker when the duty cycle is too large.
  • a class D power amplifier chip with duty cycle limiting function comprising:
  • a triangular wave module for generating a triangular wave signal
  • a PWM modulation module configured to convert the input differential audio signal and the triangular wave signal generated by the triangular wave module into a PWM signal of a low voltage pulse, and drive the PWM signal to generate a high voltage pulse;
  • a duty ratio detecting module configured to detect a duty ratio of a PWM signal generated by the PWM modulation module in real time
  • the logic control module is configured to control the PWM modulation module to stop working when the duty ratio of the PWM signal is greater than a preset maximum duty ratio.
  • the D-type power amplifier chip having a duty-limiting function
  • the PWM modulation module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first amplifier, a first comparator, and a second a comparator, a first driving circuit and a second driving circuit;
  • the forward input end of the first amplifier is connected to the first input end of the differential audio signal through the first resistor, and is also connected to the output end of the first driving circuit through the third resistor
  • the inverting input end of the first amplifier is connected to the second input end of the differential audio signal through the second resistor, and is also connected to the output end of the second driving circuit through the fourth resistor, and the positive output end of the first amplifier is connected to the inversion of the first comparator
  • the input end, the negative output end of the first amplifier is connected to the inverting input end of the second comparator, and the non-inverting input end of the first comparator and the second comparator are connected to the output end of the triangular wave
  • the D-type power amplifier chip with a duty-limiting function wherein the duty-cycle detection module includes:
  • a mirror current unit for converting the input bias current into a charging current and a discharging current to a charging and discharging control unit according to a preset ratio
  • a charge and discharge control unit configured to output a corresponding charge and discharge command according to the PWM signal generated by the PWM modulation module, and convert the charge current and the discharge current output by the mirror current unit into a capacitor voltage corresponding to the pressure value to the logic control module .
  • the D-type power amplifier chip having a duty-limiting function
  • the mirror current unit comprises: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a a six MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor;
  • the gate of the first MOS transistor is connected to the drain of the first MOS transistor, the gate of the third MOS transistor, the gate of the fifth MOS transistor, and the gate of the seventh MOS transistor, and the source of the first MOS transistor is connected.
  • a drain of the third MOS transistor is connected to a drain of the tenth MOS transistor, a gate of the tenth MOS transistor, a gate of the twelfth MOS transistor, and a gate of the fourteenth MOS transistor, the tenth MOS transistor
  • the source is connected to the drain of the ninth MOS transistor, the gate of the ninth MOS transistor, the gate of the eleventh MOS transistor, and the gate of the thirteenth MOS transistor, and the source of the twelfth MOS transistor is connected to the eleventh
  • the drain of the MOS transistor, the source of the fourteenth MOS transistor is connected to the drain of the thirteenth MOS transistor, and the sources of the ninth MOS transistor, the eleventh MOS transistor and the thirteenth MOS transistor are connected to the reference power supply terminal a drain of the twelfth MOS transistor is connected to a first input end of the charge and discharge control unit, and a drain of the fourteenth MOS transistor is connected to a second input end of the charge and discharge control unit, the
  • the D-type power amplifier chip having a duty ratio limiting function, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the first
  • the seventh MOS transistor and the eighth MOS transistor are both NMOS transistors;
  • the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor are all PMOS tube.
  • the D-type power amplifier chip having a duty-limiting function
  • the charge and discharge control unit includes a first inverter, a second inverter, a first capacitor, a second capacitor, a fifteenth MOS transistor, and a tenth a six MOS transistor, a seventeenth MOS transistor and an eighteenth MOS transistor; an input end of the first inverter is connected to the PWM modulation module, and an output end of the first inverter is connected to a gate of the fifteenth MOS transistor
  • the gate of the hexa-MOS transistor, the source of the fifteenth MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the sixteenth MOS transistor is connected to the drain of the fifth MOS transistor, and one end of the first capacitor Connecting the drain of the fifteenth MOS transistor and the drain of the sixteenth MOS transistor, and the other end of the first capacitor is grounded;
  • the input end of the second inverter is connected to the PWM modulation module, and the output end of the second inverter is connected to the gate of the seventeenth MOS transistor and the gate of the eighteenth MOS transistor, and the source of the seventeenth MOS transistor Connecting the drain of the fourteenth MOS transistor, the source of the eighteenth MOS transistor is connected to the drain of the seventh MOS transistor, and one end of the second capacitor is connected to the drain of the seventeenth MOS transistor and the eighteenth MOS transistor The drain and the other end of the second capacitor are grounded.
  • the D-type power amplifier chip having a duty-limiting function
  • the logic control module comprises: a first anti-interference circuit, a second anti-interference circuit, a third inverter, a fourth inverter, or a gate a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, and a twenty-second MOS transistor;
  • the gate of the nineteenth MOS transistor is connected to the gate of the twentieth MOS transistor and the charge and discharge control a unit
  • a drain of the nineteenth MOS transistor is connected to a drain of the twentieth MOS transistor and an input end of the third inverter
  • a source of the twentieth MOS transistor is connected to an input end of the first anti-interference circuit
  • the output end of the three inverter is connected to the control end of the first anti-interference circuit and the first input end of the OR gate;
  • the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor and the charge and discharge control unit, and the drain of the twenty-first MOS transistor is connected to the drain of the second MOSFET and the fourth reverse An input end of the phase device, a source of the 22nd MOS transistor is connected to an input end of the second anti-interference circuit, and an output end of the fourth inverter is connected to a control end of the second anti-interference circuit and a second end of the OR gate Input
  • the sources of the nineteenth MOS transistor and the twenty-first MOS transistor are all connected to the reference power supply end, and the output end of the OR gate is connected to the PWM modulation module.
  • the D-type power amplifier chip having a duty-limiting function, wherein the first anti-interference circuit comprises a twenty-third MOS transistor and a twenty-fourth MOS transistor, and a drain of the twenty-third MOS transistor Connecting the gate of the twenty-third MOS transistor, the source of the twentieth MOS transistor, and the drain of the twenty-fourth MOS transistor, and the gate of the twenty-fourth MOS transistor is connected to the output of the third inverter The sources of the twenty-third MOS transistor and the twenty-fourth MOS transistor are grounded.
  • the D-type power amplifier chip having a duty-limiting function, wherein the second anti-interference circuit comprises a twenty-fifth MOS transistor and a twenty-six MOS transistor, and a drain of the twenty-fifth MOS transistor Connecting the gate of the twenty-fifth MOS transistor, the source of the twenty-second MOS transistor, and the drain of the second sixteen MOS transistor, and the gate of the second sixteen MOS transistor is connected to the output of the fourth inverter The source of the twenty-fifth MOS transistor and the twenty-sixth MOS transistor are grounded.
  • a class D power amplifier device having a duty limit limiting function comprising a filter, a speaker and the class D power amplifier chip having a duty limit limiting function, wherein the class D power amplifier chip is connected to a speaker through a filter, class D
  • the high-voltage pulse outputted by the power amplifier chip is reduced by the filter filter to an audio signal output to the speaker, and the speaker vibration is driven to emit sound.
  • the present invention provides a class D power amplifier chip with a duty limit function and a device thereof, and converts an input differential audio signal and a triangle wave signal generated by a triangular wave module into a low voltage pulse PWM signal through a PWM modulation module.
  • the duty ratio detection module detects the duty ratio of the PWM signal in real time, and when the logic control module determines that the duty ratio of the PWM signal is greater than a preset maximum duty ratio
  • the PWM modulation module is stopped, the high-voltage pulse output of the class D power amplifier chip is turned off, which is equivalent to turning off the audio output of the class D power amplifier device; it limits the amplitude of the output audio signal, and prevents the amplitude from being excessively burned out.
  • the speaker reaches the audio signal limit and protects the speaker.
  • FIG. 2 is a schematic diagram of a class D power amplifier device with a duty limit function according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a duty ratio detecting module in a class D power amplifier chip with a duty limit function according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a logic control module in a class D power amplifier chip with a duty limit function according to an embodiment of the present invention
  • FIG. 5 is a waveform diagram of a class D power amplifier chip with a duty limit function according to an embodiment of the present invention.
  • the present invention provides a class D power amplifier chip having a duty limit function and an apparatus thereof.
  • the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
  • the class D power amplifier chip with the duty limit function provided by the present invention limits the maximum duty ratio of the PWM signal, and the duty of the PWM signal
  • the ratio is greater than the preset maximum duty ratio
  • the high-voltage pulse output of the class D power amplifier chip is turned off, which is equivalent to turning off the audio output of the class D power amplifier device, preventing the amplitude of the audio signal output from being excessively burned out;
  • the duty of the PWM signal When the ratio is less than the preset maximum duty ratio, the high-voltage pulse output of the class D power amplifier chip is turned on or maintained to ensure the normal operation of the class D power amplifier.
  • a class D power amplifier device with a duty limit function includes a filter, a speaker, and a class D power amplifier chip 10 having a duty limit function, and the class D power amplifier chip 10 is connected through a filter. speaker.
  • the class D power amplifier chip 10 includes a PWM modulation module 100, a duty ratio detection module 200, a logic control module 300, and a triangular wave module 400.
  • the PWM modulation module 100, the duty ratio detection module 200, and the logic control module 300 are sequentially connected.
  • the triangular wave module 400 is connected to the PWM modulation module 100, and the logic control module 300 is connected to the PWM modulation module 100.
  • the PWM modulation module 100 converts the input differential audio signal and the triangular wave signal generated by the triangular wave module 400 into a PWM signal of a low voltage pulse, and drives the PWM signal to generate a high voltage pulse, and then restores the audio signal output through filter filtering. Give the speaker a sound that drives the speaker to vibrate.
  • the duty cycle detection module 200 detects the duty cycle of the PWM signal in real time.
  • the logic control module 300 determines that the duty ratio of the PWM signal is greater than the preset maximum duty ratio, controls the PWM modulation module 100 to stop working, and turns off the high voltage pulse output of the class D power amplifier chip, which is equivalent to turning off the audio of the class D power amplifier device.
  • the output avoids the excessive amplitude of the audio signal output and burns out the speaker; when the duty ratio of the PWM signal is less than the preset maximum duty ratio, the logic control module 300 does not start, and the PWM modulation module 100 works normally to ensure the audio signal. Normal output.
  • the triangular wave module 400 is a prior art, which is not described in detail herein.
  • the differential audio signal is input into the PWM modulation module 100 in two ways.
  • the PWM modulation module 100 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first amplifier AMP, a first comparator CMP1, a second comparator CMP2, a first driver circuit, and The second drive circuit.
  • the forward input end of the first amplifier AMP is connected to the first input terminal A of the differential audio signal (for inputting the differential audio signal) through the first resistor R1, and is also connected to the output end of the first driving circuit through the third resistor R3.
  • the inverting input terminal of an amplifier AMP is connected to the second input terminal B of the differential audio signal through the second resistor R2, and is also connected to the output terminal of the second driving circuit through the fourth resistor R4.
  • the positive output terminal of the first amplifier AMP is connected to the first comparison.
  • the inverting input terminal of the CMP1, the negative output terminal of the first amplifier AMP is connected to the inverting input terminal of the second comparator CMP2, and the first phase comparator CMP1 and the second phase comparator CMP2 are connected to the triangular wave module
  • the output end of the first comparator CMP1 is connected to the input end of the first driving circuit and the duty ratio detecting module 200, and the output end of the second comparator CMP2 is connected to the input of the second driving circuit.
  • a second output terminal D are the output of the class D amplifier chip 10
  • a control terminal of the first driving circuit and the control terminal of the second driver circuits are connected to the output terminal of the logic control module 300.
  • the first amplifier AMP of the PWM modulation module 100 amplifies the differential audio signal to output an inverse sp signal and a sn signal.
  • the sp signal and the sn signal are respectively compared with the input fixed frequency triangular wave signal through the first comparator CMP1 and the second comparator CMP2, and then output two PWM signals (low voltage pulses) complementary to each other, that is, the PWMP signal and the PWMN signal ( For example, if the duty cycle of the PWMP signal is 60%, the duty cycle of the PWMN signal is 40%).
  • the first driving circuit and the second driving circuit respectively drive the PWMP signal and the PWMN signal to generate two corresponding high voltage pulses, and the filter filters and restores the high voltage pulse into two corresponding audio signals to the speaker.
  • the duty ratio detecting module 200 of this embodiment detects the duty ratios of the PWMP signal and the PWMN signal.
  • the duty ratio detecting module 200 charges and discharges the capacitor by using a predetermined current, and reacts the duty ratio of the PWM signal with the ratio of the charging current to the discharging current. Then, the preset maximum duty ratio is expressed as current: Idischarge / (Icharge + Idischarge), wherein Icharge is the charging current of the capacitor, and Idischarge is the discharging current of the capacitor.
  • the duty ratio detecting module 200 converts the high and low levels of the PWM signal into a charging current and a discharging current to the capacitor, thereby detecting the duty ratio thereof.
  • the duty cycle detecting module 200 includes a mirror current unit and a charge and discharge control unit 201.
  • the charge and discharge control unit 201 is connected to the mirror current unit, the logic control module, and the output of the first comparator CMP1 of the PWM modulation module and the output of the second comparator CMP2.
  • the mirror current unit adopts a mirror current source technology, which converts the input bias current Ibias into a charging current and a discharging current to the charging and discharging control unit 201 according to a preset ratio, and the charging and discharging control unit 201 generates a PWM according to the PWM modulation module.
  • the signal outputs a corresponding charging and discharging command, and converts the charging current and the discharging current output by the mirror current unit into a capacitor voltage corresponding to the voltage value to the logic control module 300.
  • the logic control module 300 determines a magnitude between a duty ratio of the PWM signal and a preset maximum duty ratio according to the charging voltage and the discharging voltage.
  • the mirror current unit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7.
  • the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are both The NMOS transistor; the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, and the fourteenth MOS transistor M14 is a PMOS tube.
  • the gate of the first MOS transistor M1 is connected to the drain of the first MOS transistor M1, the gate of the third MOS transistor M3, the gate of the fifth MOS transistor M5, and the gate of the seventh MOS transistor M7, the first MOS
  • the source of the tube M1 is connected to the drain of the second MOS transistor M2, the gate of the second MOS transistor M2, the gate of the fourth MOS transistor M4, the gate of the sixth MOS transistor M6, and the gate of the eighth MOS transistor M8.
  • the source of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4, the source of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6, and the source of the seventh MOS transistor M7 is connected to the eighth.
  • the drains of the MOS transistor M8, the sources of the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, and the eighth MOS transistor M8 are both grounded; the drain of the third MOS transistor M3 is connected to the tenth MOS a drain of the tube M10, a gate of the tenth MOS transistor M10, a gate of the twelfth MOS transistor M12, and a gate of the fourteenth MOS transistor M14, and a source of the tenth MOS transistor M10 is connected to the ninth MOS transistor
  • the drain of M9, the gate of the ninth MOS transistor M9, the gate of the eleventh MOS transistor M11, and the gate of the thirteenth MOS transistor M13, and the source of the twelfth MOS transistor M12 is connected to the eleventh MOS transistor M11
  • the drain of the fourteenth MOS transistor M14 is connected to the drain of the thirteenth MOS transistor M13, and the ninth MOS transistor M9
  • the bias current Ibias is generated by a bias circuit which is an existing structure and will not be described in detail herein.
  • This embodiment uses the bias current Ibias as a current source for the charging current and the discharging current.
  • the bias current Ibias is mirrored to the third MOS transistor M3 and the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 by the first MOS transistor M1 and the second MOS transistor M2, according to a first preset ratio.
  • the currents on the third MOS transistor M3 and the fourth MOS transistor M4 are further mirrored to the eleventh MOS transistor M11 and the twelfth MOS transistor M12 by the ninth MOS transistor M9 and the tenth MOS transistor M10 according to a second predetermined ratio.
  • a second predetermined ratio Thirteen MOS tube M13 and fourteenth MOS tube M14.
  • the first preset ratio and the second preset ratio are defined by the width (W) and the length (L) of the corresponding MOS tube, and can be derived from a known formula, which is a prior art, and is not detailed here. Said.
  • the bias current Ibias (having a certain high voltage) turns on the first MOS transistor M1 to the eighth MOS transistor M8, and the first MOS transistor M1 to the eighth MOS transistor M8 are combined into a discharge path, waiting for the discharge of the charge and discharge control unit 201. instruction.
  • the third MOS transistor M3 and the fourth MOS transistor M4 are electrically connected to ground to lower the gate of the tenth MOS transistor M10, thereby turning on the ninth MOS transistor M9 and the eleventh MOS transistor M11 to the fourteenth MOS transistor M14.
  • the reference power supply terminal VREF is turned on, and the ninth MOS transistor M9 to the fourteenth MOS transistor M14 are combined into a charging path to wait for the charging command of the charge and discharge control unit 201.
  • the charge and discharge control unit 201 includes a first inverter NOT1, a second inverter NOT2, a first capacitor C1, a second capacitor C2, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, and a tenth.
  • the seven MOS tube M17 and the eighteenth MOS tube M18; the fifteenth MOS tube M15 and the seventeenth MOS tube M17 are both PMOS tubes, and the sixteenth MOS tube M16 and the eighteenth MOS tube M18 are both NMOS tubes.
  • the unit of the capacitance values of the first capacitor C1 and the second capacitor C2 is pF.
  • the input end of the first inverter NOT1 (ie, the third input terminal 3 of the charge and discharge control unit 201) is connected to the output end of the first comparator CMP1 of the PWM modulation module 100, and the output end of the first inverter NOT1 is connected.
  • the gate of the fifteenth MOS transistor M15 and the gate of the sixteenth MOS transistor M16, the source of the fifteenth MOS transistor M15 (ie, the first input terminal 1 of the charge and discharge control unit 201) is connected to the twelfth MOS transistor M12
  • the drain, the source of the sixteenth MOS transistor M16 (ie, the first output terminal 5 of the charge and discharge control unit 201) is connected to the drain of the fifth MOS transistor M5, one end of the first capacitor C1 (ie, charge and discharge control)
  • the third output terminal 7) of the unit 201 is connected to the drain of the fifteenth MOS transistor M15 and the drain of the sixteenth MOS transistor M16, and the other end of the first capacitor C1 is grounded.
  • An input end of the second inverter NOT2 (ie, a fourth input terminal 4 of the charge and discharge control unit 201) is connected to an output end of the second comparator CMP2 of the PWM modulation module 100, and an output end of the second inverter NOT2 is connected.
  • the gate of the seventeenth MOS transistor M17 and the gate of the eighteenth MOS transistor M18, and the source of the seventeenth MOS transistor M17 (ie, the second input terminal 2 of the charge and discharge control unit 201) are connected to the fourteenth MOS transistor M14.
  • the drain of the eighteenth MOS transistor M18 (ie, the second output terminal 6 of the charge and discharge control unit 201) is connected to the drain of the seventh MOS transistor M7, and one end of the second capacitor C2 (ie, charge and discharge control)
  • the fourth output terminal 8) of the unit 201 is connected to the drain of the seventeenth MOS transistor M17 and the drain of the eighteenth MOS transistor M18, and the other end of the second capacitor C2 is grounded.
  • the circuit composed of the first inverter NOT1, the first capacitor C1, the fifteenth MOS transistor M15, and the sixteenth MOS transistor M16 expresses the duty ratio of the PWMP signal in a charging and discharging manner.
  • the specific working principle is: when the PWMP signal is high level, the first inverter NOT1 outputs a low level to turn on the fifteenth MOS transistor M15, the sixteenth MOS transistor M16 is turned off, the eleventh MOS transistor M11 and the tenth
  • the second MOS transistor M12 supplies a charging current Icharge to the bias current Ibias image, and sequentially charges the first capacitor C1 through the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the fifteenth MOS transistor M15, in order to enter the charging state,
  • the capacitor voltage CP on a capacitor C1 gradually rises.
  • the first inverter NOT1 When the PWMP signal is low, the first inverter NOT1 outputs a high level to turn on the sixteenth MOS transistor M16, and the fifteenth MOS transistor M15 is turned off.
  • the discharge current Idischarge outputted by the first capacitor C1 (provided by the fifth MOS transistor M5 and the sixth MOS transistor M6) sequentially flows through the sixteenth MOS transistor M16, the fifth MOS transistor M5, and the six MOS transistor M6 to the ground, and enters a discharge state.
  • the capacitance voltage CP on the first capacitor C1 gradually decreases.
  • the circuit composed of the second inverter NOT2, the second capacitor C2, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 expresses the duty ratio of the PWMN signal in a charging and discharging manner.
  • the working principle is the same as the PWMP signal.
  • the capacitor voltage CP can be raised to the highest voltage (about equal to the voltage V VREF on the reference power source VREF ) depends on the ratio of the charging current to the discharging current and the duty ratio of the PWMP signal. If the charge and discharge currents are equal in magnitude and the duty ratio is greater than 50%, the first capacitor C1 will continuously accumulate voltage until the highest voltage; if the duty ratio is lower than 50%, the first capacitor C1 will continue to discharge until the lowest voltage .
  • the charging and discharging currents are not equal, it is assumed that the charging current is Icharge, the discharging current is Idischarge, and the detected duty cycle threshold (ie, the preset maximum duty ratio) is Idischarge/(Icharge+Idischarge).
  • the detected duty cycle threshold ie, the preset maximum duty ratio
  • the general discharge current is greater than the charging current to detect a duty ratio of 50% or more; otherwise, if the discharge current Less than the charging current, only a duty ratio of 50% or less can be detected, so that the class D power amplifier chip 10 has no output at all.
  • the maximum duty cycle detected can be adjusted by adjusting the ratio of charge and discharge currents.
  • the logic control module 300 includes: a first anti-interference circuit 301, a second anti-interference circuit 302, a third inverter NOT3, a fourth inverter NOT4, or a gate OR, a nineteenth MOS tube M19, twentieth MOS tube M20, twenty-first MOS tube M21 and twenty-second MOS M22 tube.
  • the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21 are both PMOS transistors
  • the twentieth MOS transistor M20 and the twenty-second MOS M22 transistor are both NMOS transistors.
  • the gate of the nineteenth MOS transistor M19 is connected to the gate of the twentieth MOS transistor M20 and one end of the first capacitor C1 in the charge and discharge control unit 201, and the drain of the nineteenth MOS transistor M19 is connected to the twentieth MOS transistor.
  • the drain of the M20 and the input end of the third inverter NOT3, the source of the twentieth MOS transistor M20 is connected to the input terminal 1 of the first anti-interference circuit 301, and the output of the third inverter NOT3 is connected to the first end.
  • the gate of the twenty-first MOS transistor M21 is connected to the gate of the twenty-second MOS transistor M22 and one end of the second capacitor C2 in the charge and discharge control unit 201, and the drain of the twenty-first MOS transistor M21 is connected to the second The drain of the twelve MOS transistor M22 and the input terminal of the fourth inverter NOT4, the source of the twenty-second MOS transistor M22 is connected to the input terminal 3 of the second anti-interference circuit 302, and the fourth inverter NOT4 The output is connected to the control terminal 4 of the second disturbance rejection circuit 302 and the second input terminal of the OR gate OR.
  • the source of the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21 are connected to the reference power supply terminal VREF, and the output end of the OR gate OR is connected to the control terminal and the second driver of the first driving circuit in the PWM modulation module.
  • the inversion voltages of the twentieth MOS transistor M20 and the twelfth MOS transistor M22 are set to V VREF /2.
  • the capacitor voltage CP on the first capacitor C1 or the capacitor voltage CN on the second capacitor C2 is at a high level and greater than V VREF /2
  • the twentieth MOS transistor M20 or the twenty-second MOS transistor M22 can be guided. Passing, finally outputting the enable signal EN of the high level, thereby turning off the first driving circuit, the second driving circuit, the first comparator CMP1, the second comparator CMP2, the first amplifier AMP, and stopping the output of the large amplitude audio signal To avoid burning the speaker.
  • the first anti-interference circuit 301 includes a thirteenth MOS transistor M23 and a twenty-fourth MOS transistor M24; and a drain of the twenty-third MOS transistor M23 (ie, an input end of the first anti-interference circuit 301) 1) connecting the gate of the twenty-third MOS transistor M23, the source of the twentieth MOS transistor M20, and the drain of the twenty-fourth MOS transistor M24, the gate of the twenty-fourth MOS transistor M24 (ie, The control terminal 2) of the anti-interference circuit 301 is connected to the output terminal of the third inverter NOT3, and the sources of the twenty-third MOS transistor M23 and the twenty-fourth MOS transistor M24 are both grounded.
  • the second anti-interference circuit 302 includes a twenty-fifth MOS transistor M25 and a second sixteen MOS transistor M26; a drain of the twenty-fifth MOS transistor M25 (ie, an input of the second anti-interference circuit 302)
  • the terminal 3) is connected to the gate of the twenty-fifth MOS transistor M25, the source of the twenty-second MOS transistor M22, and the drain of the second sixteen MOS transistor M26, and the gate of the second sixteen MOS transistor M26 ( That is, the control terminal 4) of the second anti-interference circuit 302 is connected to the output terminal of the fourth inverter NOT4, and the sources of the twenty-fifth MOS transistor M25 and the twenty-sixth MOS transistor M26 are both grounded.
  • the nineteenth MOS transistor M19 when the capacitor voltage CP on the first capacitor C1 is at a low level, the nineteenth MOS transistor M19 is turned on to output a high level, and after the third inverter NOT3 is inverted, a low level is output to the OR gate. OR; at this time, the output result of the OR gate OR is determined by the output of the fourth inverter NOT4. When either OR input of the OR gate is high, its output is high; when only two inputs are low, it outputs a low level.
  • the twentieth MOS transistor M20 When the capacitance voltage CP on the first capacitor C1 is at a high level and greater than V VREF /2, the twentieth MOS transistor M20 is turned on. Since the gate of the twenty-third MOS transistor M23 is connected to its drain, the twenty-third MOS transistor M23 is equivalent to one diode (voltage drop is 0.7V), and the anode of the diode is connected to the source of the twentieth MOS transistor M20. The negative pole of the diode is grounded. Therefore, when the twentieth MOS transistor M20 is turned on, the diode (ie, the twenty-third MOS transistor M23) is also turned on, and the input terminal of the third inverter NOT3 is pulled low, and the third inverter NOT3 outputs high.
  • the diode ie, the twenty-third MOS transistor M23
  • the third inverter NOT3 outputs a high level to control the twenty-fourth MOS transistor M24 to be turned on to short-circuit the twenty-third MOS transistor M23, and as long as the capacitor voltage CP continues to be high, the third inverter can be ensured. NOT3 continues to output a high level, effectively solving the problem of waveform jitter of the capacitor voltage CP or the occurrence of disturbance burrs leading to unstable output.
  • the working principle of the second anti-interference circuit 302 is the same as that of the first anti-interference circuit 301, and details are not described herein.
  • a delay circuit may be further added after the OR gate OR, that is, the output end of the OR gate OR is connected to the input end of the delay circuit, and the output end of the delay circuit is connected to the first drive in the PWM modulation module 100.
  • the delay circuit is of a prior art and can be implemented in many ways. In this embodiment, as long as the high-level enable signal EN can be delayed, the specific circuit structure is not limited herein.
  • the duty ratio of the PWMP signal is 70%.
  • the PWMP signal with a duty ratio of 70% is input, the maximum voltage that can be reached by the voltage of the capacitor voltage CP is VVREF.
  • the duty ratio of the PWMN signal is 30%.
  • the voltage of the capacitor voltage CN is eventually zero.
  • the capacitor voltage CP and the capacitor voltage CN are output from the low level to the high level through the processing output of the logic control module, and the I5_out signal outputs a high level enable signal EN after the delay, and the output enable signal EN becomes High level, the high-voltage pulse output of the class D power amplifier chip is turned off, and the speaker is protected.
  • the input capacitance ie, the two capacitors connected when the differential audio signal is input in FIG. 2
  • the D-type power amplifier device having the duty limit function can turn off the output of the class D power amplifier chip when the amplitude of the differential audio signal is excessive, the speaker is protected. Therefore, when the input capacitor is short-circuited to ground, the output of the class D power amplifier chip is also turned off, and the class D power amplifier device can also detect an abnormal condition of the short circuit of the input capacitor.
  • the D-class power amplifier chip and the device thereof with the duty limit function provided by the present invention are based on the principle that the output amplitude of the audio signal is proportional to the duty ratio of the PWM signal, and the duty of the PWM signal is detected in real time.
  • the duty ratio of the PWM signal is greater than the preset maximum duty ratio
  • the PWM modulation module stops working, and the high-voltage pulse output of the class D power amplifier chip is turned off, thereby turning off the audio output of the class D power amplifier device, and the limitation is too large.
  • the output of the duty cycle is equivalent to limiting the output of the audio signal with an excessive amplitude, thereby preventing the excessively large audio signal from burning out the speaker. Turning on or maintaining the audio output of the Class D power amplifier device when the duty ratio of the PWM signal is less than the preset maximum duty ratio ensures the normal operation of the Class D power amplifier device.
  • the Class D power amplifier device can also detect the occurrence of some abnormal conditions, such as short circuit of the input capacitor to the ground.

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Abstract

一种具有占空比限制功能的D类功放芯片及其装置，D类功放芯片(10)包括三角波模块(400)、PWM调制模块(100)、占空比检测模块(200)和逻辑控制模块(300)，PWM调制模块(100)、占空比检测模块(200)和逻辑控制模块(300)依次连接，所述逻辑控制模块(300)连接PWM调制模块(100)；由PWM调制模块(100)将输入的差分音频信号和三角波模块(400)产生的三角波信号转换成低压脉冲的PWM信号，对PWM信号进行驱动处理生成高压脉冲；通过占空比检测模块(200)实时检测PWM信号的占空比，当逻辑控制模块判断PWM信号的占空比大于预设最大占空比时，控制PWM调制模块停止工作，相当于关闭该Ｄ类功放装置的音频输出；其限制了输出的音频信号的幅度，避免其幅值过大烧坏扬声器。

Description

一种具有占空比限制功能的D类功放芯片及其装置
技术领域
本发明涉及电源技术领域，特别涉及一种具有占空比限制功能的D类功放芯片及其装置。
背景技术
D类功放（即D类音频功率放大器）是一种开关型的功放，其优点是效率高，发热少，被广泛应用于智能电视、智能手机等消费电子领域。请参阅图1，常见的D类功放（虚线框内为D类功放芯片的内部结构）包括：放大器AMPa，比较器CMPa、比较器CMPb、驱动器a和驱动器b；其连接关系如图1所示。该D类功放的工作原理基于PWM模式，差分音频信号经过放大器AMPa放大后分两路分别输入比较器CMPa与比较器CMPb中，与输入的三角波信号进行比较后得到对应的两路PWM信号的，然后分别经过驱动器a、驱动器b将两路PWM信号的幅度放大，最后滤波还原为音频信号、驱动扬声器振动发出声音。
当输入的差分音频信号幅度过大，会使还原后的音频信号的幅度超过扬声器的额定值，或者使输入电容Ca或输入电容Cb短路，导致使还原后的音频信号为一直流分量，可能烧坏扬声器。为了避免此类异常情况发生，需要对D类功放的输出幅度进行限制。由于PWM信号的脉冲宽度（即占空比）与音频信号的幅度成正比例，因此，可通过PWM信号的占空比进行限制来限制音频信号的输出幅度。
发明内容
鉴于上述现有技术的不足之处，本发明的目的在于提供一种具有占空比限制功能的D类功放芯片及其装置，以解决现有D类功放不能限制音频信号的输出幅度，PWM信号的占空比过大时烧坏扬声器的问题。
为了达到上述目的，本发明采取了以下技术方案：
一种具有占空比限制功能的D类功放芯片，其包括：
三角波模块，用于产生三角波信号；
PWM调制模块，用于将输入的差分音频信号和所述三角波模块产生的三角波信号转换成低压脉冲的PWM信号，对所述PWM信号进行驱动处理生成高压脉冲；
占空比检测模块，用于实时检测所述PWM调制模块产生的PWM信号的占空比；
逻辑控制模块，用于判断PWM信号的占空比大于预设最大占空比时，控制PWM调制模块停止工作。
所述的具有占空比限制功能的D类功放芯片，其中，所述PWM调制模块包括第一电阻、第二电阻、第三电阻、第四电阻、第一放大器、第一比较器、第二比较器、第一驱动电路和第二驱动电路；所述第一放大器的正向输入端通过第一电阻连接差分音频信号第一输入端、还通过第三电阻连接第一驱动电路的输出端，第一放大器的反向输入端通过第二电阻连接差分音频信号第二输入端、还通过第四电阻连接第二驱动电路的输出端，第一放大器的正输出端连接第一比较器的反相输入端，第一放大器的负输出端连接第二比较器的反相输入端，所述第一比较器与第二比较器的正相输入端均连接三角波模块的输出端，第一比较器的输出端连接第一驱动电路的输入端和占空比检测模块，第二比较器的输出端连接第二驱动电路的输入端和占空比检测模块，第一驱动电路的输出端和第二驱动电路的输出端均为D类功放芯片的输出端，第一驱动电路的控制端和第二驱动电路的控制端均连接逻辑控制模块。
所述的具有占空比限制功能的D类功放芯片，其中，所述占空比检测模块包括：
镜像电流单元，用于将输入的偏置电流按预设比例镜像转换为充电电流和放电电流给充放电控制单元；
充放电控制单元，用于根据所述PWM调制模块产生的PWM信号输出对应的充、放电指令，将所述镜像电流单元输出的充电电流和放电电流转换成对应压值的电容电压给逻辑控制模块。
所述的具有占空比限制功能的D类功放芯片，其中，所述镜像电流单元包括：第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管、第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第十二MOS管、第十三MOS管和第十四MOS管；
所述第一MOS管的栅极连接第一MOS管的漏极、第三MOS管的栅极、第五MOS管的栅极和第七MOS管的栅极，第一MOS管的源极连接第二MOS管的漏极、第二MOS管的栅极、第四MOS管的栅极、第六MOS管的栅极和第八MOS管的栅极，所述第三MOS管的源极连接第四MOS管的漏极，第五MOS管的源极连接第六MOS管的漏极，第七MOS管的源极连接第八MOS管的漏极，所述第二MOS管、第四MOS管、第六MOS管和第八MOS管的源极均接地；
所述第三MOS管的漏极连接第十MOS管的漏极、第十MOS管的栅极、第十二MOS管的栅极和第十四MOS管的栅极，所述第十MOS管的源极连接第九MOS管的漏极、第九MOS管的栅极、第十一MOS管的栅极和第十三MOS管的栅极，第十二MOS管的源极连接第十一MOS管的漏极，第十四MOS管的源极连接第十三MOS管的漏极，所述第九MOS管、第十一MOS管和第十三MOS管的源极均连接基准电源端；所述第十二MOS管的漏极连接充放电控制单元的第一输入端，所述第十四MOS管的漏极连接充放电控制单元的第二输入端，所述第五MOS管的漏极连接充放电控制单元的第一输出端，所述第七MOS管的漏极连接充放电控制单元的第二输出端。
所述的具有占空比限制功能的D类功放芯片，其中，所述第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管和第八MOS管均为NMOS管；所述第九MOS管、第十MOS管、第十一MOS管、第十二MOS管、第十三MOS管和第十四MOS管均为PMOS管。
所述的具有占空比限制功能的D类功放芯片，其中，充放电控制单元包括第一反相器、第二反相器、第一电容、第二电容、第十五MOS管、第十六MOS管、第十七MOS管和第十八MOS管；所述第一反相器的输入端连接PWM调制模块，第一反相器的输出端连接第十五MOS管的栅极和第十六MOS管的栅极，第十五MOS管的源极连接第十二MOS管的漏极，第十六MOS管的源极连接第五MOS管的漏极，所述第一电容的一端连接第十五MOS管的漏极和第十六MOS管的漏极，第一电容的另一端接地；
所述第二反相器的输入端连接PWM调制模块，第二反相器的输出端连接第十七MOS管的栅极和第十八MOS管的栅极，第十七MOS管的源极连接第十四MOS管的漏极，第十八MOS管的源极连接第七MOS管的漏极，所述第二电容的一端连接第十七MOS管的漏极和第十八MOS管的漏极，第二电容的另一端接地。
所述的具有占空比限制功能的D类功放芯片，其中，所述逻辑控制模块包括：第一抗扰电路、第二抗扰电路、第三反相器、第四反相器、或门、第十九MOS管、第二十MOS管、第二十一MOS管和第二十二MOS管；所述第十九MOS管的栅极连接第二十MOS管的栅极和充放电控制单元，第十九MOS管的漏极连接第二十MOS管的漏极和第三反相器的输入端，第二十MOS管的源极连接第一抗扰电路的输入端，所述第三反相器的输出端连接第一抗扰电路的控制端和或门OR的第一输入端；
所述第二十一MOS管的栅极连接第二十二MOS管的栅极和充放电控制单元，第二十一MOS管的漏极连接第二十二MOS管的漏极和第四反相器的输入端，第二十二MOS管的源极连接第二抗扰电路的输入端，所述第四反相器的输出端连接第二抗扰电路的控制端和或门的第二输入端；
所述第十九MOS管、第二十一MOS管的源极均连接基准电源端，所述或门的输出端连接PWM调制模块。
所述的具有占空比限制功能的D类功放芯片，其中，所述第一抗扰电路包括第二十三MOS管和第二十四MOS管，所述第二十三MOS管的漏极连接第二十三MOS管的栅极、第二十MOS管的源极和第二十四MOS管的漏极，所述第二十四MOS管的栅极连接第三反相器的输出端，所述第二十三MOS管、第二十四MOS管的源极均接地。
所述的具有占空比限制功能的D类功放芯片，其中，所述第二抗扰电路包括第二十五MOS管和第二十六MOS管，所述第二十五MOS管的漏极连接第二十五MOS管的栅极、第二十二MOS管的源极和第二十六MOS管的漏极，所述第二十六MOS管的栅极连接第四反相器的输出端，所述第二十五MOS管、第二十六MOS管的源极均接地。
一种具有占空比限制功能的D类功放装置，其包括滤波器、扬声器和所述的具有占空比限制功能的D类功放芯片，所述D类功放芯片通过滤波器连接扬声器，D类功放芯片输出的高压脉冲通过滤波器滤波还原为音频信号输出给扬声器，驱动扬声器振动发出声音。
相较于现有技术，本发明提供的具有占空比限制功能的D类功放芯片及其装置，通过PWM调制模块将输入的差分音频信号和三角波模块产生三角波信号转换成低压脉冲的PWM信号，对所述PWM信号进行驱动处理生成高压脉冲；本实施例通过占空比检测模块实时检测所述PWM信号的占空比，当逻辑控制模块判断PWM信号的占空比大于预设最大占空比时，控制PWM调制模块停止工作，关闭该D类功放芯片的高压脉冲输出，相当于关闭了D类功放装置的音频输出；其限制了输出的音频信号的幅度，避免其幅值过大烧坏扬声器，达到了音频信号限制和保护扬声器的作用。
附图说明
图1为现有D类功放芯片的应用电路图；
图2为本发明实施例提供的具有占空比限制功能的D类功放装置的示意图；
图3为本发明实施例提供的具有占空比限制功能的D类功放芯片中占空比检测模块的电路图；
图4为本发明实施例提供的具有占空比限制功能的D类功放芯片中逻辑控制模块示意图；
图5为本发明实施例提供的具有占空比限制功能的D类功放芯片的波形图。
具体实施方式
本发明提供一种具有占空比限制功能的D类功放芯片及其装置，为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
为了解决D类功放PWM信号的占空比过大烧坏扬声器的问题，本发明提供的具有占空比限制功能的D类功放芯片通过限制PWM信号的最大占空比，在PWM信号的占空比大于预设最大占空比时关闭D类功放芯片的高压脉冲输出，相当于关闭了D类功放装置的音频输出，避免音频信号输出的幅值过大烧坏扬声器；在PWM信号的占空比小于预设最大占空比时打开或保持D类功放芯片的高压脉冲输出，确保了D类功放的正常工作。
请参阅图2，本发明提供的具有占空比限制功能的D类功放装置包括滤波器、扬声器和具有占空比限制功能的D类功放芯片10，所述D类功放芯片10通过滤波器连接扬声器。D类功放芯片10包括PWM调制模块100、占空比检测模块200、逻辑控制模块300和三角波模块400。所述PWM调制模块100、占空比检测模块200和逻辑控制模块300依次连接，所述三角波模块400连接PWM调制模块100，所述逻辑控制模块300连接PWM调制模块100。PWM调制模块100将输入的差分音频信号和所述三角波模块400产生的三角波信号转换成低压脉冲的PWM信号，对所述PWM信号进行驱动处理生成高压脉冲、再通过滤波器滤波还原为音频信号输出给扬声器，驱动扬声器振动发出声音。在PWM调制模块100工作时，占空比检测模块200实时检测所述PWM信号的占空比。逻辑控制模块300判断PWM信号的占空比大于预设最大占空比时、控制PWM调制模块100停止工作，关闭该D类功放芯片的高压脉冲输出，相当于关闭所述D类功放装置的音频输出，避免了音频信号输出的幅值过大烧坏扬声器；在PWM信号的占空比小于预设最大占空比时、逻辑控制模块300不启动，PWM调制模块100正常工作，确保音频信号的正常输出。其中，所述三角波模块400为现有技术，此处对此不作详述。
应当理解的是，所述差分音频信号分两路输入PWM调制模块100中。则所述PWM调制模块100包括第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第一放大器AMP、第一比较器CMP1、第二比较器CMP2、第一驱动电路和第二驱动电路。所述第一放大器AMP的正向输入端通过第一电阻R1连接差分音频信号第一输入端A（用于输入差分音频信号）、还通过第三电阻R3连接第一驱动电路的输出端，第一放大器AMP的反向输入端通过第二电阻R2连接差分音频信号第二输入端B、还通过第四电阻R4连接第二驱动电路的输出端，第一放大器AMP的正输出端连接第一比较器CMP1的反相输入端，第一放大器AMP的负输出端连接第二比较器CMP2的反相输入端，所述第一比较器CMP1与第二比较器CMP2的正相输入端均连接三角波模块的输出端（用于接收三角波信号），第一比较器CMP1的输出端连接第一驱动电路的输入端和占空比检测模块200，第二比较器CMP2的输出端连接第二驱动电路的输入端和占空比检测模块200，第一驱动电路的输出端（即所述D类功放芯片10的第一输出端C）和第二驱动电路的输出端（即所述D类功放芯片10的第二输出端D）均为D类功放芯片10的输出端，均连接滤波器，第一驱动电路的控制端和第二驱动电路的控制端均连接逻辑控制模块300的输出端。
PWM调制模块100的第一放大器AMP将差分音频信号放大后输出波形相反的sp信号和sn信号。sp信号和sn信号分别与输入的固定频率的三角波信号通过第一比较器CMP1、第二比较器CMP2比较后输出两路占空比互补的PWM信号（低压脉冲）、即PWMP信号和PWMN信号（如，PWMP信号的占空比为60%，则PWMN信号的占空比为40%）。第一驱动电路、第二驱动电路分别对PWMP信号、PWMN信号进行驱动处理生成两路对应的高压脉冲，滤波器对高压脉冲进行滤波还原成两路对应的音频信号给扬声器。本实施例的占空比检测模块200即是对PWMP信号和PWMN信号的占空比进行检测。
具体实施时，占空比检测模块200采用预定的电流给电容充电和放电，以充电电流与放电电流的比例来反应PWM信号的占空比。则所述预设最大占空比以电流方式表现为：Idischarge/(Icharge+Idischarge)，其中Icharge为电容的充电电流，Idischarge为电容的放电电流。占空比检测模块200将PWM信号的高低电平转换成对电容的充电电流和放电电流，从而检测出其占空比。
请一并参阅图3，为了实现占空比与电流之间的转换，所述占空比检测模块200包括镜像电流单元和充放电控制单元201。所述充放电控制单元201连接镜像电流单元、逻辑控制模块、以及PWM调制模块的第一比较器CMP1的输出端和第二比较器CMP2的输出端。镜像电流单元采用镜像电流源技术，其将输入的偏置电流Ibias按预设比例镜像转换为充电电流和放电电流给充放电控制单元201，充放电控制单元201根据所述PWM调制模块产生的PWM信号输出对应的充、放电指令，将所述镜像电流单元输出的充电电流和放电电流转换成对应压值的电容电压给逻辑控制模块300。逻辑控制模块300根据所述充电电压和放电电压判断PWM信号的占空比与预设最大占空比之间的大小。
其中，所述镜像电流单元包括第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4、第五MOS管M5、第六MOS管M6、第七MOS管M7、第八MOS管M8、第九MOS管M9、第十MOS管M10、第十一MOS管M11、第十二MOS管M12、第十三MOS管M13和第十四MOS管M14。所述第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4、第五MOS管M5、第六MOS管M6、第七MOS管M7和第八MOS管M8均为NMOS管；所述第九MOS管M9、第十MOS管M10、第十一MOS管M11、第十二MOS管M12、第十三MOS管M13和第十四MOS管 M14均为PMOS管。
所述第一MOS管M1的栅极连接第一MOS管M1的漏极、第三MOS管M3的栅极、第五MOS管M5的栅极和第七MOS管M7的栅极，第一MOS管M1的源极连接第二MOS管M2的漏极、第二MOS管M2的栅极、第四MOS管M4的栅极、第六MOS管M6的栅极和第八MOS管M8的栅极，所述第三MOS管M3的源极连接第四MOS管M4的漏极，第五MOS管M5的源极连接第六MOS管M6的漏极，第七MOS管M7的源极连接第八MOS管M8的漏极，第二MOS管M2、第四MOS管M4、第六MOS管M6和第八MOS管M8的源极均接地；所述第三MOS管M3的漏极连接第十MOS管M10的漏极、第十MOS管M10的栅极、第十二MOS管M12的栅极和第十四MOS管M14的栅极，所述第十MOS管M10的源极连接第九MOS管M9的漏极、第九MOS管M9的栅极、第十一MOS管M11的栅极和第十三MOS管M13的栅极，第十二MOS管M12的源极连接第十一MOS管M11的漏极，第十四MOS管M14的源极连接第十三MOS管M13的漏极，所述第九MOS管M9、第十一MOS管M11和第十三MOS管M13的源极均连接基准电源端VREF；所述第十二MOS管M12的漏极连接充放电控制单元201的第一输入端1，所述第十四MOS管M14的漏极连接充放电控制单元201的第二输入端2，所述第五MOS管M5的漏极连接充放电控制单元201的第一输出端5，所述第七MOS管M7的漏极连接充放电控制单元201的第二输出端6。
偏置电流Ibias由偏置电路产生，偏置电路为现有结构，此处对此不作详述。本实施例采用该偏置电流Ibias作为充电电流和放电电流的电流来源。通过第一MOS管M1和第二MOS管M2将所述偏置电流Ibias按第一预设比例镜像给第三MOS管M3和第四MOS管M4，第五MOS管M5和六MOS管M6，第七MOS管M7和第八MOS管M8。第三MOS管M3和第四MOS管M4上的电流再通过第九MOS管M9和第十MOS管M10按第二预设比例镜像给第十一MOS管M11和第十二MOS管M12，第十三MOS管M13和第十四MOS管M14。所述第一预设比例和第二预设比例由对应MOS管的宽（W）、长（L）限定，可从已知的公式推算出，此为现有技术，此处对此不作详述。
同时，偏置电流Ibias（具有一定高压）使第一MOS管M1~第八MOS管M8导通，第一MOS管M1~第八MOS管M8组合成放电通路，等待充放电控制单元201的放电指令。第三MOS管M3和第四MOS管M4导通接地将第十MOS管M10的栅极拉低，从而使第九MOS管M9、第十一MOS管M11~第十四MOS管M14均导通，接通基准电源端VREF，第九MOS管M9~第十四MOS管M14组合成充电通路，等待充放电控制单元201的充电指令。
其中，所述充放电控制单元201包括第一反相器NOT1、第二反相器NOT2、第一电容C1、第二电容C2、第十五MOS管M15、第十六MOS管M16、第十七MOS管M17和第十八MOS管M18；所述第十五MOS管M15和第十七MOS管M17均为PMOS管，第十六MOS管M16和第十八MOS管M18均为NMOS管，第一电容C1和第二电容C2的容值的单位级为pF。
所述第一反相器NOT1的输入端（即充放电控制单元201的第三输入端3）连接PWM调制模块100的第一比较器CMP1的输出端，第一反相器NOT1的输出端连接第十五MOS管M15的栅极和第十六MOS管M16的栅极，第十五MOS管M15的源极（即充放电控制单元201的第一输入端1）连接第十二MOS管M12的漏极，第十六MOS管M16的源极（即充放电控制单元201的第一输出端5）连接第五MOS管M5的漏极，所述第一电容C1的一端（即充放电控制单元201的第三输出端7）连接第十五MOS管M15的漏极和第十六MOS管M16的漏极，第一电容C1的另一端接地。
所述第二反相器NOT2的输入端（即充放电控制单元201的第四输入端4）连接PWM调制模块100的第二比较器CMP2的输出端，第二反相器NOT2的输出端连接第十七MOS管M17的栅极和第十八MOS管M18的栅极，第十七MOS管M17的源极（即充放电控制单元201的第二输入端2）连接第十四MOS管M14的漏极，第十八MOS管M18的源极（即充放电控制单元201的第二输出端6）连接第七MOS管M7的漏极，所述第二电容C2的一端（即充放电控制单元201的第四输出端8）连接第十七MOS管M17的漏极和第十八MOS管M18的漏极，第二电容C2的另一端接地。
本实施例中，由第一反相器NOT1、第一电容C1、第十五MOS管M15和第十六MOS管M16组成的电路将PWMP信号的占空比以充、放电流方式表现。具体工作原理为：当PWMP信号为高电平时，第一反相器NOT1输出低电平使第十五MOS管M15导通，第十六MOS管M16截止，第十一MOS管M11和第十二MOS管M12对偏置电流Ibias镜像后提供充电电流Icharge依次通过第十一MOS管M11、第十二MOS管M12、第十五MOS管M15对第一电容C1充电，为进入充电状态，第一电容C1上的电容电压CP逐渐上升。当PWMP信号为低电平时，第一反相器NOT1输出高电平使第十六MOS管M16导通，第十五MOS管M15截止。第一电容C1输出的放电电流Idischarge（由第五MOS管M5和第六MOS管M6提供）依次通过第十六MOS管M16、第五MOS管M5、六MOS管M6流出到地，进入放电状态，第一电容C1上的电容电压CP逐渐下降。
对应地，本实施例中由第二反相器NOT2、第二电容C2、第十七MOS管M17和第十八MOS管M18组成的电路将PWMN信号的占空比以充、放电流方式表现；其工作原理与PWMP信号相同，具体实施时可参照上述PWMP信号的工作原理，此处对此不作赘述。
应当理解的是，电容电压CP充电时能否上升到最高电压（约等于基准电源VREF上的电压VVREF），取决于充电电流与放电电流的比例、以及PWMP信号的占空比的大小。如果充、放电电流大小相等，占空比只要大于50%，第一电容C1就会不断累积电压，直到最高电压；如果占空比低于50%，第一电容C1就会不断放电直到最低电压。
如果充、放电电流不相等，假设充电电流为Icharge，放电电流为Idischarge，检测的占空比临界点（即预设最大占空比）为Idischarge/(Icharge+Idischarge)。第一电容C1上的电容电压CP和第二电容C2上的电容电压CN输出给逻辑控制模块时，一般放电电流要大于充电电流，才能检测到50%以上的占空比；否则，如果放电电流小于充电电流，只能检测到50%以下的占空比，这样该D类功放芯片10一直不会有输出。这是因为PWMP信号和PWMN信号的占空比是互补的，两者之间总会有一个占空比大于50%，结果总是会触发逻辑控制模块300输出使能信号EN。通过调整充、放电电流的比例就可以调整检测的最大占空比。
第一电容C1上的电容电压CP和第二电容C2上的电容电压CN输入逻辑控制模块300中作进一步判断。请一并参阅图4、所述逻辑控制模块300包括：第一抗扰电路301、第二抗扰电路302、第三反相器NOT3、第四反相器NOT4、或门OR、第十九MOS管M19、第二十MOS管M20、第二十一MOS管M21和第二十二MOS M22管。所述第十九MOS管M19和第二十一MOS管M21均为PMOS管，第二十MOS管M20和第二十二MOS M22管均为NMOS管。
所述第十九MOS管M19的栅极连接第二十MOS管M20的栅极和充放电控制单元201中第一电容C1的一端，第十九MOS管M19的漏极连接第二十MOS管M20的漏极和第三反相器NOT3的输入端，第二十MOS管M20的源极连接第一抗扰电路301的输入端1，所述第三反相器NOT3的输出端连接第一抗扰电路301的控制端2和或门OR的第一输入端。
所述第二十一MOS管M21的栅极连接第二十二MOS管M22的栅极和充放电控制单元201中第二电容C2的一端，第二十一MOS管M21的漏极连接第二十二MOS管M22的漏极和第四反相器NOT4的输入端，第二十二MOS管M22的源极连接第二抗扰电路302的输入端3，所述第四反相器NOT4的输出端连接第二抗扰电路302的控制端4和或门OR的第二输入端。
所述第十九MOS管M19、第二十一MOS管M21的源极均连接基准电源端VREF，所述或门OR的输出端连接PWM调制模块中第一驱动电路的控制端、第二驱动电路的控制端、第一比较器CMP1的控制端、第二比较器CMP2的控制端和第一放大器AMP的控制端。
本实施例中，第二十MOS管M20和第二十二MOS管M22的翻转电压设置为VVREF/2。当第一电容C1上的电容电压CP或这第二电容C2上的电容电压CN为高电平且大于VVREF/2时，第二十MOS管M20或第二十二MOS管M22即可导通，最终输出高电平的使能信号EN，从而关闭第一驱动电路、第二驱动电路、第一比较器CMP1、第二比较器CMP2、第一放大器AMP，停止较大幅度的音频信号输出，避免烧毁扬声器。
其中，所述第一抗扰电路301包括第二十三MOS管M23和第二十四MOS管M24；所述第二十三MOS管M23的漏极（即第一抗扰电路301的输入端1）连接第二十三MOS管M23的栅极、第二十MOS管M20的源极和第二十四MOS管M24的漏极，所述第二十四MOS管M24的栅极（即第一抗扰电路301的控制端2）连接第三反相器NOT3的输出端，所述第二十三MOS管M23、第二十四MOS管M24的源极均接地。
对应地，所述第二抗扰电路302包括第二十五MOS管M25和第二十六MOS管M26；所述第二十五MOS管M25的漏极（即第二抗扰电路302的输入端3）连接第二十五MOS管M25的栅极、第二十二MOS管M22的源极和第二十六MOS管M26的漏极，所述第二十六MOS管M26的栅极（即第二抗扰电路302的控制端4）连接第四反相器NOT4的输出端，所述第二十五MOS管M25、第二十六MOS管M26的源极均接地。
本实施例中，当第一电容C1上的电容电压CP为低电平时，第十九MOS管M19导通输出高电平，经过第三反相器NOT3反向后输出低电平给或门OR；此时或门OR的输出结果由第四反相器NOT4的输出决定。或门OR任一输入为高电平时，其输出高电平；只有两个输入均为低电平时，才输出低电平。
当第一电容C1上的电容电压CP为高电平且大于VVREF/2时，第二十MOS管M20导通。由于第二十三MOS管M23的栅极与其漏极连接，第二十三MOS管M23等效于一个二极管（压降为0.7V），二极管的正极连接第二十MOS管M20的源极，二极管的负极接地。因此，当第二十MOS管M20导通时，二极管（即第二十三MOS管M23）也导通，将第三反相器NOT3的输入端拉低，则第三反相器NOT3输出高电平至或门OR，或门OR输出高电平。同时，第三反相器NOT3输出高电平控制第二十四MOS管M24导通使第二十三MOS管M23短路，只要电容电压CP持续为高电平，就能确保第三反相器NOT3持续输出高电平，有效地解决了电容电压CP的波形抖动、或出现干扰毛刺导致输出不稳定的问题。
所述第二抗扰电路302的工作原理与第一抗扰电路301相同，此处不作赘述。
为了减少误判断，进一步地可在或门OR后面增加延时电路，即所述或门OR的输出端连接延时电路的输入端，延时电路的输出端连接PWM调制模块100中第一驱动电路的控制端、第二驱动电路的控制端、第一比较器CMP1的控制端、第二比较器CMP2的控制端和第一放大器AMP的控制端；使高电平的使能信号EN延时100毫秒后再输出。所述延时电路对为现有技术，可实现的方式较多，本实施例只要能使高电平的使能信号EN延时输出即可，此处对其具体电路结构不作限定。
请同时参阅图5，对上述D类功放芯片进行波形仿真后可以看出，假设PWMP信号的占空比为70%。PWMP信号的高电平持续时间较长，对第一电容C1的充电时间（即PWMP信号为高电平的时间）长于其放电时间（即PWMP信号为低电平的时间）；本实施例中Idischarge/Icharge=2，则检测的预设最大占空比为66.7%。当占空比为70%的PWMP信号输入时，电容电压CP的电压最终可以达到的最大电压为VVREF。由于PWMN信号的占空比与PWMP信号信号的占空比相加之和为100%，则PWMN信号的占空比为30%。电容电压CN的电压最终为零。电容电压CP和电容电压CN经过逻辑控制模块的处理输出I5_out信号从低电平转换为高电平，I5_out信号经过延时后输出高电平的使能信号EN为，输出使能信号EN变成高电平，关闭D类功放芯片的高压脉冲输出，保护了扬声器。
另外，当差分音频信号的幅度过大时，会使输入电容（即图2中差分音频信号输入时连接的两个电容）对地短路。由于通过所述具有占空比限制功能的D类功放装置能在差分音频信号的幅度过大时关闭D类功放芯片的输出，保护扬声器。因此，输入电容对地短路时也会关闭D类功放芯片的输出，所述D类功放装置还能检测输入电容短路的异常状况。
综上所述，本发明提供的具有占空比限制功能的D类功放芯片及其装置，基于音频信号的输出幅度与PWM信号的占空比成正比的原理，通过实时检测PWM信号的占空比，在判断PWM信号的占空比大于预设最大占空比时、PWM调制模块停止工作，关闭该D类功放芯片的高压脉冲输出，从而关闭了D类功放装置的音频输出，限制过大占空比的输出相当于限制幅度过大的音频信号的输出，从而避免了幅度过大的音频信号烧坏扬声器。在PWM信号的占空比小于预设最大占空比时打开或保持D类功放装置的音频输出，确保了D类功放装置的正常工作。
另外，所述D类功放装置还能检测一些异常情况的发生，例如：输入电容对地短路等。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (13)

  1. 一种具有占空比限制功能的D类功放芯片，其特征在于，包括：
    三角波模块，用于产生三角波信号；
    PWM调制模块，用于将输入的差分音频信号和所述三角波模块产生的三角波信号转换成低压脉冲的PWM信号，对所述PWM信号进行驱动处理生成高压脉冲；
    占空比检测模块，用于实时检测所述PWM调制模块产生的PWM信号的占空比；
    逻辑控制模块，用于当所述PWM调制模块产生的PWM信号的占空比大于预设最大占空比时，控制PWM调制模块停止工作。
  2. 根据权利要求1所述的具有占空比限制功能的D类功放芯片，其特征在于，所述PWM调制模块包括第一电阻、第二电阻、第三电阻、第四电阻、第一放大器、第一比较器、第二比较器、第一驱动电路和第二驱动电路；所述第一放大器的正向输入端通过第一电阻连接差分音频信号第一输入端、还通过第三电阻连接第一驱动电路的输出端，第一放大器的反向输入端通过第二电阻连接差分音频信号第二输入端、还通过第四电阻连接第二驱动电路的输出端，第一放大器的正输出端连接第一比较器的反相输入端，第一放大器的负输出端连接第二比较器的反相输入端，所述第一比较器与第二比较器的正相输入端均连接三角波模块的输出端，第一比较器的输出端连接第一驱动电路的输入端和占空比检测模块，第二比较器的输出端连接第二驱动电路的输入端和占空比检测模块，第一驱动电路的输出端和第二驱动电路的输出端均为D类功放芯片的输出端，第一驱动电路的控制端和第二驱动电路的控制端均连接逻辑控制模块。
  3. 根据权利要求1所述的具有占空比限制功能的D类功放芯片，其特征在于，所述逻辑控制模块包括：第一抗扰电路、第二抗扰电路、第三反相器、第四反相器、或门、第十九MOS管、第二十MOS管、第二十一MOS管和第二十二MOS管；所述第十九MOS管的栅极连接第二十MOS管的栅极和充放电控制单元，第十九MOS管的漏极连接第二十MOS管的漏极和第三反相器的输入端，第二十MOS管的源极连接第一抗扰电路的输入端，所述第三反相器的输出端连接第一抗扰电路的控制端和或门OR的第一输入端；
    所述第二十一MOS管的栅极连接第二十二MOS管的栅极和充放电控制单元，第二十一MOS管的漏极连接第二十二MOS管的漏极和第四反相器的输入端，第二十二MOS管的源极连接第二抗扰电路的输入端，所述第四反相器的输出端连接第二抗扰电路的控制端和或门的第二输入端；
    所述第十九MOS管、第二十一MOS管的源极均连接基准电源端，所述或门的输出端连接PWM调制模块。
  4. 根据权利要求3所述的具有占空比限制功能的D类功放芯片，其特征在于，所述第一抗扰电路包括第二十三MOS管和第二十四MOS管，所述第二十三MOS管的漏极连接第二十三MOS管的栅极、第二十MOS管的源极和第二十四MOS管的漏极，所述第二十四MOS管的栅极连接第三反相器的输出端，所述第二十三MOS管、第二十四MOS管的源极均接地。
  5. 根据权利要求3所述的具有占空比限制功能的D类功放芯片，其特征在于，所述第二抗扰电路包括第二十五MOS管和第二十六MOS管，所述第二十五MOS管的漏极连接第二十五MOS管的栅极、第二十二MOS管的源极和第二十六MOS管的漏极，所述第二十六MOS管的栅极连接第四反相器的输出端，所述第二十五MOS管、第二十六MOS管的源极均接地。
  6. 一种具有占空比限制功能的D类功放芯片，其特征在于，包括：
    三角波模块，用于产生三角波信号；
    PWM调制模块，用于将输入的差分音频信号和所述三角波模块产生的三角波信号转换成低压脉冲的PWM信号，对所述PWM信号进行驱动处理生成高压脉冲；
    占空比检测模块，用于实时检测所述PWM调制模块产生的PWM信号的占空比；
    逻辑控制模块，用于当所述PWM调制模块产生的PWM信号的占空比大于预设最大占空比时，控制PWM调制模块停止工作；
    所述占空比检测模块包括：
    镜像电流单元，用于将输入的偏置电流按预设比例镜像转换为充电电流和放电电流给充放电控制单元；
    充放电控制单元，用于根据所述PWM调制模块产生的PWM信号输出对应的充、放电指令，将所述镜像电流单元输出的充电电流和放电电流转换成对应压值的电容电压给逻辑控制模块。
  7. 根据权利要求6所述的具有占空比限制功能的D类功放芯片，其特征在于，所述镜像电流单元包括：第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管、第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第十二MOS管、第十三MOS管和第十四MOS管；
    所述第一MOS管的栅极连接第一MOS管的漏极、第三MOS管的栅极、第五MOS管的栅极和第七MOS管的栅极，第一MOS管的源极连接第二MOS管的漏极、第二MOS管的栅极、第四MOS管的栅极、第六MOS管的栅极和第八MOS管的栅极，所述第三MOS管的源极连接第四MOS管的漏极，第五MOS管的源极连接第六MOS管的漏极，第七MOS管的源极连接第八MOS管的漏极，所述第二MOS管、第四MOS管、第六MOS管和第八MOS管的源极均接地；
    所述第三MOS管的漏极连接第十MOS管的漏极、第十MOS管的栅极、第十二MOS管的栅极和第十四MOS管的栅极，所述第十MOS管的源极连接第九MOS管的漏极、第九MOS管的栅极、第十一MOS管的栅极和第十三MOS管的栅极，第十二MOS管的源极连接第十一MOS管的漏极，第十四MOS管的源极连接第十三MOS管的漏极，所述第九MOS管、第十一MOS管和第十三MOS管的源极均连接基准电源端；所述第十二MOS管的漏极连接充放电控制单元的第一输入端，所述第十四MOS管的漏极连接充放电控制单元的第二输入端，所述第五MOS管的漏极连接充放电控制单元的第一输出端，所述第七MOS管的漏极连接充放电控制单元的第二输出端。
  8. 根据权利要求6所述的具有占空比限制功能的D类功放芯片，其特征在于，所述第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管和第八MOS管均为NMOS管；所述第九MOS管、第十MOS管、第十一MOS管、第十二MOS管、第十三MOS管和第十四MOS管均为PMOS管。
  9. 根据权利要求6所述的具有占空比限制功能的D类功放芯片，其特征在于，充放电控制单元包括第一反相器、第二反相器、第一电容、第二电容、第十五MOS管、第十六MOS管、第十七MOS管和第十八MOS管；所述第一反相器的输入端连接PWM调制模块，第一反相器的输出端连接第十五MOS管的栅极和第十六MOS管的栅极，第十五MOS管的源极连接第十二MOS管的漏极，第十六MOS管的源极连接第五MOS管的漏极，所述第一电容的一端连接第十五MOS管的漏极和第十六MOS管的漏极，第一电容的另一端接地；
    所述第二反相器的输入端连接PWM调制模块，第二反相器的输出端连接第十七MOS管的栅极和第十八MOS管的栅极，第十七MOS管的源极连接第十四MOS管的漏极，第十八MOS管的源极连接第七MOS管的漏极，所述第二电容的一端连接第十七MOS管的漏极和第十八MOS管的漏极，第二电容的另一端接地。
  10. 根据权利要求6所述的具有占空比限制功能的D类功放芯片，其特征在于，所述逻辑控制模块包括：第一抗扰电路、第二抗扰电路、第三反相器、第四反相器、或门、第十九MOS管、第二十MOS管、第二十一MOS管和第二十二MOS管；所述第十九MOS管的栅极连接第二十MOS管的栅极和充放电控制单元，第十九MOS管的漏极连接第二十MOS管的漏极和第三反相器的输入端，第二十MOS管的源极连接第一抗扰电路的输入端，所述第三反相器的输出端连接第一抗扰电路的控制端和或门OR的第一输入端；
    所述第二十一MOS管的栅极连接第二十二MOS管的栅极和充放电控制单元，第二十一MOS管的漏极连接第二十二MOS管的漏极和第四反相器的输入端，第二十二MOS管的源极连接第二抗扰电路的输入端，所述第四反相器的输出端连接第二抗扰电路的控制端和或门的第二输入端；
    所述第十九MOS管、第二十一MOS管的源极均连接基准电源端，所述或门的输出端连接PWM调制模块。
  11. 根据权利要求10所述的具有占空比限制功能的D类功放芯片，其特征在于，所述第一抗扰电路包括第二十三MOS管和第二十四MOS管，所述第二十三MOS管的漏极连接第二十三MOS管的栅极、第二十MOS管的源极和第二十四MOS管的漏极，所述第二十四MOS管的栅极连接第三反相器的输出端，所述第二十三MOS管、第二十四MOS管的源极均接地。
  12. 根据权利要求10所述的具有占空比限制功能的D类功放芯片，其特征在于，所述第二抗扰电路包括第二十五MOS管和第二十六MOS管，所述第二十五MOS管的漏极连接第二十五MOS管的栅极、第二十二MOS管的源极和第二十六MOS管的漏极，所述第二十六MOS管的栅极连接第四反相器的输出端，所述第二十五MOS管、第二十六MOS管的源极均接地。
  13. 一种具有占空比限制功能的D类功放装置，其特征在于，包括滤波器、扬声器和如权利要求1-12任意一项所述的具有占空比限制功能的D类功放芯片，所述D类功放芯片通过滤波器连接扬声器，D类功放芯片输出的高压脉冲通过滤波器滤波还原为音频信号输出给扬声器，驱动扬声器振动发出声音。
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103905006B (zh) * 2014-03-28 2017-10-24 深圳创维－Rgb电子有限公司 一种具有占空比限制功能的d类功放芯片及其装置
CN105373178B (zh) 2014-08-15 2018-02-02 深圳市中兴微电子技术有限公司 电路启动方法、控制电路及电压基准电路
CN104836192B (zh) * 2015-04-16 2018-02-09 深圳市一生微电子有限公司 用于pwm调制型音频功放的输入短路保护电路
CN104917467B (zh) * 2015-06-24 2017-08-25 江苏博普电子科技有限责任公司 一种GaN微波功率放大器用漏极调制电路
CN105119574B (zh) * 2015-08-20 2018-03-30 深圳创维－Rgb电子有限公司 带pop噪声抑制的d类功放电路
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CN108648896B (zh) * 2018-05-11 2020-02-14 温州大学 双占空比脉宽调制信号的双向电磁铁驱动电路及使用方法
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CN112994631A (zh) * 2019-12-02 2021-06-18 华润微集成电路(无锡)有限公司 D类功放自适应半波调制控制的电路结构
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CN112213696B (zh) * 2020-09-30 2023-03-28 深圳迈睿智能科技有限公司 抗干扰微波探测模块及其抗干扰方法
CN113054928B (zh) * 2021-03-12 2023-08-29 苏州至盛半导体科技有限公司 D类功放动态升压闭环控制器及动态升压的d类功放
CN114447890A (zh) * 2022-02-10 2022-05-06 广东省大湾区集成电路与系统应用研究院 驱动保护电路及电子芯片
CN114567198A (zh) * 2022-02-22 2022-05-31 陕西省电子技术研究所有限公司 一种基于d类功放的单相纯正弦逆变电源

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05218757A (ja) * 1992-01-31 1993-08-27 Nec Corp トランジスタ電力増幅装置
US20070268069A1 (en) * 2005-05-19 2007-11-22 Lg Electronics Inc. Apparatus and method for controlling temperature of electronic apparatus
CN101150297A (zh) * 2006-09-18 2008-03-26 晶豪科技股份有限公司 半波式脉冲宽度调制式d类音频放大器
CN101567668A (zh) * 2008-04-24 2009-10-28 骅讯电子企业股份有限公司 应用于d类放大器的电压检测式过电流保护装置
CN101696996A (zh) * 2009-10-16 2010-04-21 西安英洛华微电子有限公司 脉宽信号占空比检测器
US20100246852A1 (en) * 2009-03-24 2010-09-30 Jy-Der David Tai Output-level-controlling converter device
CN103905006A (zh) * 2014-03-28 2014-07-02 深圳创维－Rgb电子有限公司 一种具有占空比限制功能的d类功放芯片及其装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389829A (en) 1991-09-27 1995-02-14 Exar Corporation Output limiter for class-D BICMOS hearing aid output amplifier
US6016075A (en) * 1997-06-04 2000-01-18 Lord Corporation Class-D amplifier input structure
EP1049247B1 (en) * 1999-04-27 2005-08-03 STMicroelectronics S.r.l. Class-D amplifier with enhanced bandwidth
RU2188498C1 (ru) * 2001-01-29 2002-08-27 Федеральное государственное унитарное предприятие "Центральный научно-исследовательский институт "Морфизприбор" Двухканальный усилитель класса d
JP3982342B2 (ja) * 2002-03-28 2007-09-26 ヤマハ株式会社 Ｄ級増幅器における三角波生成回路および該三角波生成回路を用いたｄ級増幅器
US7142050B2 (en) * 2003-10-15 2006-11-28 Texas Instruments Incorporated Recovery from clipping events in a class D amplifier
US7339425B2 (en) * 2006-08-03 2008-03-04 Elite Semiconductor Memory Technology, Inc. Class-D audio amplifier with half-swing pulse-width-modulation
JP4408912B2 (ja) * 2007-04-13 2010-02-03 日本テキサス・インスツルメンツ株式会社 Ｄ級増幅回路
CN101419255B (zh) * 2008-12-04 2012-02-29 杭州士兰微电子股份有限公司 开关电源的占空比检测电路、检测方法及应用
CN201374646Y (zh) * 2008-12-04 2009-12-30 杭州士兰微电子股份有限公司 开关电源的占空比检测电路及开关电源频率检测电路
CN201440647U (zh) * 2009-07-06 2010-04-21 德信科技股份有限公司 具有双调变模块的d类放大器
CN103066566B (zh) * 2013-01-15 2016-04-13 昂宝电子（上海）有限公司 基于占空比信息为电源转换器提供过流保护的系统和方法
US8330541B2 (en) * 2011-03-01 2012-12-11 Maxim Integrated Products, Inc. Multilevel class-D amplifier
US8421535B2 (en) * 2011-08-08 2013-04-16 Adamson Systems Engineering Inc. Method and apparatus for reducing distortion in Class D amplifier
CN103188851B (zh) * 2011-12-31 2016-08-03 海洋王照明科技股份有限公司 Led恒流驱动电路
CN102843109B (zh) * 2012-09-25 2016-01-20 上海贝岭股份有限公司 一种d类功放芯片

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05218757A (ja) * 1992-01-31 1993-08-27 Nec Corp トランジスタ電力増幅装置
US20070268069A1 (en) * 2005-05-19 2007-11-22 Lg Electronics Inc. Apparatus and method for controlling temperature of electronic apparatus
CN101150297A (zh) * 2006-09-18 2008-03-26 晶豪科技股份有限公司 半波式脉冲宽度调制式d类音频放大器
CN101567668A (zh) * 2008-04-24 2009-10-28 骅讯电子企业股份有限公司 应用于d类放大器的电压检测式过电流保护装置
US20100246852A1 (en) * 2009-03-24 2010-09-30 Jy-Der David Tai Output-level-controlling converter device
CN101696996A (zh) * 2009-10-16 2010-04-21 西安英洛华微电子有限公司 脉宽信号占空比检测器
CN103905006A (zh) * 2014-03-28 2014-07-02 深圳创维－Rgb电子有限公司 一种具有占空比限制功能的d类功放芯片及其装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI824457B (zh) * 2022-03-28 2023-12-01 晶豪科技股份有限公司 具工作週期控制的音訊放大器

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