WO2015123800A1 - 一种台阶封装基板控胶方法 - Google Patents

一种台阶封装基板控胶方法 Download PDF

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Publication number
WO2015123800A1
WO2015123800A1 PCT/CN2014/000587 CN2014000587W WO2015123800A1 WO 2015123800 A1 WO2015123800 A1 WO 2015123800A1 CN 2014000587 W CN2014000587 W CN 2014000587W WO 2015123800 A1 WO2015123800 A1 WO 2015123800A1
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Prior art keywords
glue
package substrate
groove
peelable
conductor
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PCT/CN2014/000587
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English (en)
French (fr)
Inventor
刘秋华
穆敦发
吴小龙
吴梅珠
徐杰栋
胡广群
梁少文
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无锡江南计算技术研究所
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Publication of WO2015123800A1 publication Critical patent/WO2015123800A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of integrated circuit fabrication, and more particularly to a step-sealing substrate control method.
  • the chip or soldering position on the substrate medium 1 is stepped (or groove 2), as shown in Fig. 1, the conductor is exposed (the exposed conductor 3 at the groove), and the surface is made. After processing (gold plating or tinning), wire or solder the device. This part of the exposed conductor needs to be wired or soldered at the back, so the conductor must remain intact and must be completely exposed, that is, no residual medium is allowed on the conductor, which requires glue control.
  • the prepreg 4 is fenestrated in the exposed area of the conductor. Due to the difference in pattern distribution and the difference in heat, the flow adhesive of the prepreg 4 is unstable, and the flow amount generally fluctuates between 0.5 and 2 mm. This flow span spans far beyond the range of the small hole around the groove, and the prepreg Opening the window too much will cause defects such as voids caused by local pressure loss, and even interfere with the via hole 5 beside the groove, as shown in Fig. 2. If the window is too small, the glue will flow to the exposed conductor, thereby forming the overflow on the conductor at the groove 6, as shown in Fig. 3.
  • the existing solutions are as follows: First, adding a filler gel at the conductor position to control the amount of glue; Second, using a prepreg laminated with a small amount of glue, by controlling the window opening of the prepreg Meet the design requirements.
  • Adding a filler gel at the conductor position is critical to the choice of filler. It is required that the filler 7 can be completely filled into the groove position, and there is no flow of the prepreg between the filler and the groove conductor, otherwise the glue will seep on the conductor. Pad. In fact, it is difficult to avoid the local flow of glue from the gap between the filler and the conductor to the pad, as shown in Fig. 4.
  • the amount of the prepreg with a small amount of glue is below 0.5mm.
  • the window size of the prepreg it can ensure that the flow glue on the groove conductor is within the control range (the flow glue does not exceed 20% of the area of the conductor area) , but for lamination of multilayer boards, to ensure interlayer flow Glue fills the conductor gap to ensure reliability.
  • a prepreg with a large amount of glue is used to better fill the pattern gap, which leads to uncontrollable flow. Therefore, the application range of using a small amount of prepreg to open the window to control the flow glue is very narrow, and most of the stack design is not feasible. Summary of the invention
  • the technical problem to be solved by the present invention is to provide the above-mentioned defects in the prior art, and to provide a method for manufacturing a control glue by using a peelable glue, which can ensure that there is no medium residue in the exposed conductor at the step position.
  • a step package substrate control method comprising: a first step: pickling an inner layer monolith formed with a four-slot package structure, and then screen printing a strip of peelable glue at the groove position ;
  • the second step baking the screen with the peelable adhesive structure to solidify the peelable adhesive; the third step: after the peelable adhesive is solidified, the inner layer is browned and laminated to form a plurality of layers. Board
  • Fourth step Remove the strippable glue before the finished product is milled to expose the conductor under the strippable strip.
  • the conditions for baking and curing in the second step are baking at 150 ° C for 30-60 minutes.
  • the distance of the peelable glue from the side of the groove window is in the range of 0.1 - 0.2 mm.
  • the thickness of the peelable glue is in the range of 40 ⁇ to 60 ⁇ .
  • the blind shield is removed by blind milling to expose the strippable area, thereby peeling off the peelable glue and exposing the strippable protective conductor.
  • the step package substrate control method provided by the invention screens the strippable glue at the groove position before the substrate is laminated to protect the conductor at the groove, and the strippable glue covers most of the entire conductor after curing. After removing the peelable glue before the finished product is milled, the part of the conductor is intact, no residual glue, and subsequent wire bonding or welding can be performed. Since the inner layer is monolithically printed on the inner surface of the groove in the groove region, the conductor can be in contact with the rest of the medium, thereby controlling the glue on the conductor and ensuring the groove. The area has no residual glue residue, ensuring the effective size of the groove area.
  • the method for controlling the glue of the step package substrate provided by the invention can effectively prevent the residual glue at the exposed position of the groove.
  • Fig. 1 schematically shows a stepped structure of a package substrate.
  • Fig. 2 schematically shows a case where the prepreg louver is excessively large in the stepped structure of the package substrate.
  • Fig. 3 is a view schematically showing a case where the prepreg louvering is too small in the stepped structure of the package substrate.
  • Fig. 4 schematically shows a solution for adding a filler gel at the conductor position.
  • Fig. 5 is a flow chart schematically showing a method of controlling the glue of a step package substrate in accordance with a preferred embodiment of the present invention.
  • Fig. 6 is a schematic cross-sectional view showing a method of controlling the adhesion of a step package substrate in accordance with a preferred embodiment of the present invention.
  • Fig. 7 is a schematic plan view showing a method of controlling the adhesion of a step package substrate in accordance with a preferred embodiment of the present invention.
  • the present invention solves some of the control glues for the two methods of the prior art mentioned in the background art.
  • Limitation a new type of glue control is proposed, which can ensure that there is no glue residue in the groove position conductor by silk-screening a strippable adhesive on the exposed conductor at the groove, thereby ensuring the subsequent wire bonding of the groove conductor or welding.
  • Fig. 5 is a flow chart schematically showing a method of controlling the glue of a step package substrate in accordance with a preferred embodiment of the present invention.
  • a method for controlling a rubber of a step package substrate includes: a first step S1: pickling an inner layer of a package structure having a groove 2 (ie, a stepped structure) Then, at the groove position (for example, the surface of the exposed conductor 3 at the groove, that is, the corresponding position of the groove region) is screen printed with a strip of strippable glue 8;
  • the distance of the peelable glue 8 from the side edge 9 of the groove window is in the range of 0.1-0.2 mm;
  • the thickness of the strippable glue 8 is generally controlled to be about 50 ⁇ m.
  • the thickness of the strippable glue 8 is in the range of 40 ⁇ m to 60 ⁇ m, as shown in FIGS. 6 and 7.
  • the second step S2 baking the structure with the strippable glue 8 on the silk screen to cure the peelable glue 8; preferably, the baking curing condition is generally baked at 150 ° C for 30-60 minutes;
  • the third step S3 after the peelable adhesive is cured and formed, the inner layer is browned; after that, subsequent lamination is performed according to the manufacturing process of the conventional package substrate, for example, lamination to form a multilayer board;
  • Fourth step S4 removing the strippable glue before exposing the finished product to expose the conductor under the strippable rubber; specifically, as shown in Fig. 5, after the lamination and the like are completed, before the finished milling, the blind milling The medium on the peelable adhesive is removed, the peelable adhesive area is exposed, and the peelable glue is removed to expose the peelable protective conductor. Subsequent wire bonding or soldering can then be performed on the exposed conductor.
  • the step package substrate control method the groove position is screen printed before the substrate is laminated to protect the conductor at the groove, and the strippable adhesive covers the entire conductor after curing. Most areas (for example, more than 80% of the area). After removing the peelable glue before the finished product is milled, the part of the conductor is intact, no residual glue, and subsequent wire bonding or welding can be performed. Since the inner layer is monolithically printed in the groove region, the tape can be peeled off, and the contact between the insulated conductor and the remaining medium is Thereby, the glue control effect on the conductor is achieved, and at the same time, the residual area of the groove is not left, and the effective size of the groove area is ensured.
  • the step package substrate control method according to the preferred embodiment of the present invention can effectively prevent the flow glue residue at the exposed position of the groove position.
  • the distance of the peelable glue 8 from the side edge 9 of the groove window is not more than 0.15 mm; and the thickness of the peelable glue 8 is generally controlled to be about 50 ⁇ m, and the flow can be substantially completely prevented. Residue of glue.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Laminated Bodies (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种台阶封装基板控胶方法，包括：第一步骤，对形成有凹槽的封装结构的内层单片进行酸洗，然后在凹槽位置丝印一层可剥胶；第二步骤，对丝印有可剥胶的结构进行烘烤，使可剥胶固化成型；第三步骤，可剥胶固化成型后将内层单片进行棕化，并进行层压以形成多层板；第四步骤，在成品铣切前去掉可剥胶以暴露可剥胶下的导体。提供的台阶封装基板控胶方法可有效防止凹槽位置外露的导体处的流胶残余。

Description

一种台阶封装基板控胶方法 技术领域
本发明涉及集成电路制造领域， 更具体地说， 本发明涉及一种台阶封 装基板控胶方法。
背景技术
一些封装基板设计时， 将基板介质 1 上贴的芯片或焊接位置做成台 阶状（或凹槽 2 )， 如图 1所示， 该处导体外露（凹槽处外露的导体 3 )， 做表面处理 （镀金或喷锡）后打线或焊接器件用。 这部分外露的导体由 于后面需要打线或焊接等， 因此导体处必须保持完整， 须完全棵露在外， 即该导体上不允许有介质残留， 从而需要进行控胶制作。
常规层压时， 在该导体外露区域将半固化片 4开窗。 由于图形分布 差异、 受热不同差异， 半固化片 4的流胶不稳定， 流胶量一般在 0.5-2mm 之间波动， 这一流胶跨度范围已远远超出凹槽周围小孔距凹槽的范围 , 半固化片开窗过大会造成局部失压导致空洞等缺陷， 甚至会干扰凹槽旁 的导通孔 5， 如图 2所示。 开窗过小会使得凹槽位置流胶流到外露的导体 处， 从而形成凹槽处导体上的溢胶 6, 如图 3所示。
针对上述技术缺陷， 现有的解决方法有： 第一， 在导体位置加填充 物阻胶， 控制流胶量； 第二， 选用流胶量很小的半固化片层压， 通过控 制半固化片的开窗可以达到设计要求。
在导体位置加填充物阻胶对填充物选择非常关键， 要求填充物 7能 完全填充到凹槽位置， 填充物和凹槽导体之间无半固化片的流胶， 否则 流胶会渗到导体上污染焊盘。 实际上选用常规的填充物阻胶均难以避免 局部流胶从填充物和导体的缝隙间渗入污染到焊盘， 如图 4所示。
另一方面， 流胶量小的半固化片流胶量在 0.5mm以下通过合理设计 半固化片的开窗大小可以确保凹槽导体上的流胶在控制范围内 （流胶不 超过导体区域面积的 20% )， 但是对于多层板的层压来说， 为确保层间流 胶填充导体间隙， 保证可靠性， 一般选用流胶量大的半固化片以更好地 填充满图形间隙， 这样就导致了流胶的不可控制。 因此采取选用流胶量 小半固化片开窗控制流胶的适用范围很窄， 大部分叠构设计是不可行的。 发明内容
本发明所要解决的技术问题是针对现有技术中存在上述缺陷， 提供 一种用可剥胶填充控胶的制作方式， 可以确保台阶位置外露导体无介质 残留。
根据本发明， 提供了一种台阶封装基板控胶方法， 其包括： 第一步骤： 对形成有四槽的封装结构的内层单片进行酸洗， 然后在 凹槽位置丝印一层可剥胶；
第二步骤： 对丝印有可剥胶的结构进行烘烤， 使可剥胶固化成型； 第三步骤： 可剥胶固化成型后将内层单片进行棕化， 并进行层压以 形成多层板；
第四步骤： 在成品铣切前去掉可剥胶以暴露可剥胶下的导体。
优选地， 第二步骤中烘烤固化的条件为 150°C下烘烤 30-60分钟。 优选地， 在第一步骤中， 可剥胶距凹槽窗口的侧边的距离介于 0.1 -0.2mm的范围内。
优选地， 在第一步骤中， 可剥胶的厚度介于 40 μ ηι至 60 μ ιη的范围 内。
优选地， 在第四步骤中， 在成品铣切前， 盲铣揭掉可剥胶上的介盾， 露出可剥胶区域， 进而揭掉可剥胶， 露出可剥胶保护的导体。
本发明提供的台阶封装基板控胶方法在凹槽位置在基板层压前丝印 可剥胶以保护凹槽处的导体， 该可剥胶固化成型后即覆盖住整个导体的 大部分区域。 在成品铣切前去掉可剥胶后这部分导体完好， 无残胶， 可 以进行后续的打线或焊接。 由于内层单片上在凹槽区域丝印可剥胶， 隔 绝导体和其余介质的接触， 从而起到导体上的控胶效果， 同时确保凹槽 区域无流胶残余， 保证凹槽区域的有效尺寸。
由此， 本发明提供的台阶封装基板控胶方法可有效防止凹槽位置外 露的导体处的流胶残余。
附图说明
结合附图， 并通过参考下面的详细描述， 将会更容易地对本发明有 更完整的理解并且更容易地理解其伴随的优点和特征， 其中：
图 1示意性地示出了封装基板的台阶状结构。
图 2示意性地示出了封装基板的台阶状结构中半固化片开窗过大的 情况。
图 3 示意性地示出了封装基板的台阶状结构中半固化片开窗过小的 情况。
图 4示意性地示出了在导体位置加填充物阻胶的方案。
图 5示意性地示出了根据本发明优选实施例的台阶封装基板控胶方 法的流程图。
图 6示意性地示出了根据本发明优选实施例的台阶封装基板控胶方 法的截面示意图。
图 7示意性地示出了根据本发明优选实施例的台阶封装基板控胶方 法的平面示意图。
需要说明的是， 附图用于说明本发明， 而非限制本发明。 注意， 表 示结构的附图可能并非按比例绘制。 并且， 附图中， 相同或者类似的元 件标有相同或者类似的标号。 具体实施方式
为了使本发明的内容更加清楚和易懂， 下面结合具体实施例和附图 对本发明的内容进行详细描述。
本发明针对背景技术中提到的现有技术的两种方法解决控胶的一些 局限性， 提出一种新型的控胶方式， 通过在凹槽处外露的导体上丝印一 层可剥胶方式阻胶确保凹槽位置导体无流胶残留， 保证了凹槽导体的后 续打线或焊接。
具体地说， 图 5 示意性地示出了根据本发明优选实施例的台阶封装 基板控胶方法的流程图。
如图 5所示， 根据本发明优选实施例的台阶封装基板控胶方法包括： 第一步骤 S1 : 对形成有凹槽 2 (即， 台阶状结构） 的封装结构的内 层单片进行酸洗， 然后在凹槽位置（例如， 凹槽处外露的导体 3 的表面 上， 即， 凹槽区域的对应位置）丝印一层可剥胶 8;
优选地， 可剥胶 8距凹槽窗口的侧边 9 (即， 内层图形区域 10的与 可剥胶 8相邻的侧边 9 ) 的距离介于 0.1-0.2mm的范围内； 而且优选地， 可剥胶 8的厚度一般控制在 50 μ m左右， 例如可剥胶 8的厚度介于 40 μ m至 60 μ ιη的范围内， 如图 6、 图 7所示。
第二步骤 S2: 对丝印有可剥胶 8的结构进行烘烤， 使可剥胶 8固化 成型； 优选地， 烘烤固化的条件一般为 150°C下烘烤 30-60分钟；
第三步骤 S3: 可剥胶固化成型后再将内层单片进行棕化； 在此之后， 后续按照常规封装基板的制作流程进行层压等制作， 例如进行层压以形 成多层板；
第四步骤 S4: 在成品铣切前去掉可剥胶以暴露可剥胶下的导体； 具 体地说， 如图 5 所示， 可在层压等制作完成之后， 在成品铣切前， 盲铣 揭掉可剥胶上的介质， 露出可剥胶区域， 进而揭掉可剥胶， 即可露出可 剥胶保护的导体。 此后可以在露出的导体上进行后续的打线或焊接。
随后， 即可进行成品铣切等后续步骤。
由此， 根据本发明优选实施例的台阶封装基板控胶方法， 凹槽位置 在基板层压前丝印可剥胶以保护凹槽处的导体， 该可剥胶固化成型后即 覆盖住整个导体的大部分区域（例如， 80%以上的区域）。 在成品铣切前 去掉可剥胶后这部分导体完好， 无残胶， 可以进行后续的打线或焊接。 由于内层单片上在凹槽区域丝印可剥胶， 隔绝导体和其余介质的接触， 从而起到导体上的控胶效果， 同时确保凹槽区域无流胶残余， 保证凹槽 区域的有效尺寸。
而且， 根据本发明优选实施例的台阶封装基板控胶方法可有效防止 凹槽位置外露的导体处的流胶残余
而且， 根据实验测试， 在可剥胶 8距凹槽窗口的侧边 9的距离不大 于 0.15mm; 而且可剥胶 8的厚度一般控制在大约 50 μ m的情况下，基本 上能完全防止流胶残余。
此外， 需要说明的是， 除非特别指出， 否则说明书中的术语 "第一"、 "第二"、 "第三" 等描述仅仅用于区分说明书中的各个组件、 元素、 步 骤等， 而不是用于表示各个组件、 元素、 步骤之间的逻辑关系或者顺序 关系等。
可以理解的是， 虽然本发明已以较佳实施例披露如上， 然而上述实 施例并非用以限定本发明。 对于任何熟悉本领域的技术人员而言， 在不 脱离本发明技术方案范围情况下， 都可利用上述揭示的技术内容对本发 明技术方案作出许多可能的变动和修饰， 或修改为等同变化的等效实施 例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发明的技术实质 对以上实施例所做的任何简单修改、 等同变化及修饰， 均仍属于本发明 技术方案保护的范围内。

Claims

桓 利 要 求 书
1. 一种台阶封装基板控胶方法， 其特征在于包括:
第一步骤： 对形烕有 HI槽的封装結构的肉晨单片进行酸 *, 然 在 凹槽位置丝印一层可剥胶；
笫二步骤: 对丝印有可剥胶的结构进行烘烤， 使可剥胶固化成型; 第三步骤: 可剥胶固化成型后将内层单片进行棕化, 并进行层压以 形成多层极；
第四步骤： 在成品铣切前去掉可剥胶以暴露可剥胶下的导体
2. 根据权利要求 1所述的台阶封装基板控胶方法，其特征在于， 第 二步骤中烘烤固化的条件为 150 下烘烤 30-60分钟。
3.根据权利要求 1或 2所述的台阶封装基板控胶方法，其特征在于， 在第一步琛中， 可剥胶距凹槽窗口的側边的距离介于 0.1 -0.2mm 的范围 内。
4.根据权利要求 1或 2所述的台阶封装基板控胶方法，其特征在于, 在第一歩骤中， 可剥胶的厚度介于 40 μ πι至 60 μ πι的范围内。
5.根据权利要求 1或 2所述的台阶封装基板控胶方法,其特征在于， 在第四步骤中， 在成品銑切前， 盲镇揭摔可剝服上的介廣， 露 Λ可剩胶 区域, 进而揭掉可剥胶, 露出可剥胶保护的导体。
PCT/CN2014/000587 2014-02-18 2014-06-16 一种台阶封装基板控胶方法 WO2015123800A1 (zh)

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