WO2015122257A1 - Élément de conversion photoélectrique - Google Patents

Élément de conversion photoélectrique Download PDF

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WO2015122257A1
WO2015122257A1 PCT/JP2015/051790 JP2015051790W WO2015122257A1 WO 2015122257 A1 WO2015122257 A1 WO 2015122257A1 JP 2015051790 W JP2015051790 W JP 2015051790W WO 2015122257 A1 WO2015122257 A1 WO 2015122257A1
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amorphous semiconductor
semiconductor layer
silicon substrate
photoelectric conversion
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PCT/JP2015/051790
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Japanese (ja)
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神川　剛
真臣 原田
和也 辻埜
直城 小出
直城 浅野
雄太 松本
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to a photoelectric conversion element.
  • pyramidal unevenness caused by the (111) plane is obtained by anisotropically etching the surface of the silicon substrate having the (100) plane using an alkaline solution. It is known to use a light confinement structure having a shape.
  • Such a light confinement structure can increase the short-circuit current because the reflectivity of the surface of the silicon substrate is reduced due to the pyramidal uneven shape.
  • intrinsic (i-type) amorphous silicon is interposed between the n-type single crystal silicon substrate and the p-type amorphous silicon layer to reduce defects at the interface and to improve the heterojunction interface characteristics.
  • HIT Heterojunction with Intrinsic Thin Layer
  • ⁇ Pyramidal irregularities are formed on the surface of the silicon substrate so that incident sunlight is not reflected on the surface of the silicon substrate, thereby reducing the reflectance of the surface of the silicon substrate.
  • a photoelectric conversion element capable of improving the conversion efficiency by suppressing the deterioration of the passivation characteristics due to the texture structure is provided.
  • the photoelectric conversion element is a photoelectric conversion element including a silicon substrate, and the silicon substrate has first and second surfaces.
  • the first surface is textured.
  • the second surface is opposed to the first surface, has no texture structure, and includes a first unevenness and a second unevenness.
  • the height difference of the first unevenness is 6 ⁇ m or less, and the average surface roughness of the second unevenness is smaller than 0.75 nm.
  • the open circuit voltage is increased. Become.
  • the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the height difference of the first unevenness is 2 ⁇ m or less.
  • the open circuit voltage can be dramatically increased as the average surface roughness of the second unevenness decreases.
  • the photoelectric conversion element further includes first and second amorphous semiconductor layers.
  • the first amorphous semiconductor layer is disposed in contact with the second surface and substantially has an i-type conductivity type.
  • the second amorphous semiconductor layer is disposed in contact with the first amorphous semiconductor layer and has a conductivity type opposite to that of the silicon substrate.
  • the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the average surface roughness of the second unevenness is 0.40 nm or less.
  • the open circuit voltage can be increased dramatically as the height difference of the first unevenness decreases.
  • the photoelectric conversion element further includes third and fourth amorphous semiconductor layers.
  • the third amorphous semiconductor layer is disposed in contact with the first surface and substantially has an i-type conductivity type.
  • the fourth amorphous semiconductor layer is disposed in contact with the third amorphous semiconductor layer and has the same conductivity type as that of the silicon substrate.
  • the light receiving surface of the silicon substrate is passivated by the third amorphous semiconductor layer, and recombination of the photoexcited minority carriers on the light receiving surface side is suppressed. As a result, the short circuit current increases.
  • the photoelectric conversion element further includes first to fifth amorphous semiconductor layers.
  • the first amorphous semiconductor layer is disposed in contact with the first surface.
  • the second amorphous semiconductor layer is disposed in contact with the second surface and has a substantially i-type conductivity type.
  • the third amorphous semiconductor layer is disposed in contact with the second surface and is disposed adjacent to the second amorphous semiconductor layer in the in-plane direction of the silicon substrate.
  • the fourth amorphous semiconductor layer is disposed in contact with the second amorphous semiconductor layer and has a conductivity type opposite to that of the silicon substrate.
  • the fifth amorphous semiconductor layer is disposed in contact with the third amorphous semiconductor layer and has the same conductivity type as that of the silicon substrate.
  • the photoelectric conversion element in which the pn junction by the heterojunction is arranged on the side opposite to the light receiving surface, recombination of carriers on the light receiving surface side of the silicon substrate is suppressed to increase the short-circuit current and increase the open circuit voltage.
  • the conversion efficiency can be further improved by further suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the silicon substrate is substantially sandwiched between the i-type amorphous semiconductor layers, thermal strain of the silicon substrate can be suppressed in the manufacturing process of the photoelectric conversion element, so that the lifetime of the carrier can be suppressed.
  • the first amorphous semiconductor layer includes sixth and seventh amorphous semiconductor layers.
  • the sixth amorphous semiconductor layer is disposed in contact with the light receiving surface of the silicon substrate and substantially has an i-type conductivity type.
  • the seventh amorphous semiconductor layer is disposed in contact with the sixth amorphous semiconductor layer and has the same conductivity type as that of the silicon substrate.
  • the recombination of carriers on the light receiving surface side of the silicon substrate is further suppressed.
  • the conversion efficiency can be further improved by increasing the short-circuit current.
  • the open circuit voltage is increased. Become.
  • the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • FIG. 1 It is sectional drawing which shows the structure of the photoelectric conversion element by Embodiment 1 of this invention. It is a top view of the electrode of the back surface side of the photoelectric conversion element shown in FIG. It is a figure which shows the microscope picture of the (100) plane of an n-type single crystal silicon substrate. It is a figure which shows the SEM photograph of a flat board
  • FIG. 4 is a third process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • 6 is a cross-sectional view illustrating a configuration of a photoelectric conversion element according to Embodiment 2.
  • FIG. It is a 1st process drawing which shows the manufacturing method of the photoelectric conversion element shown in FIG.
  • It is a 2nd process drawing which shows the manufacturing method of the photoelectric conversion element shown in FIG.
  • It is a figure which shows the microscope picture of the (100) plane of an n-type single crystal silicon substrate.
  • 6 is a cross-sectional view illustrating a configuration of a photoelectric conversion element according to Embodiment 4.
  • FIG. FIG. 15 is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 14.
  • FIG. 15 is a second process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 14.
  • FIG. 15 is a third process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 14.
  • FIG. 6 is a cross-sectional view illustrating a configuration of a photoelectric conversion element according to a fifth embodiment.
  • FIG. 19 is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 18.
  • FIG. 19 is a second process diagram illustrating a method of manufacturing the photoelectric conversion element illustrated in FIG. 18.
  • FIG. 19 is a third process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 18. It is the schematic which shows the structure of a photoelectric conversion module provided with the photoelectric conversion element by this embodiment.
  • amorphous silicon is expressed as “a-Si”, but this notation actually means that hydrogen (H) atoms are included.
  • (a-Ge) means that an H atom is contained.
  • the amorphous semiconductor layer includes a completely amorphous semiconductor layer and a microcrystalline semiconductor layer.
  • the microcrystalline semiconductor layer refers to a semiconductor in which the average particle diameter of semiconductor crystals precipitated in the amorphous semiconductor layer is 1 to 50 nm.
  • FIG. 1 is a cross-sectional view showing the configuration of the photoelectric conversion element according to Embodiment 1.
  • photoelectric conversion element 100 according to Embodiment 1 includes n-type single crystal silicon substrate 1, amorphous semiconductor layer 2, i-type amorphous semiconductor layers 3 and 4, and p-type non-crystal.
  • a crystalline semiconductor layer 5, an n-type amorphous semiconductor layer 6, transparent conductive films 7 and 8, electrodes 9 and 10, and an insulating layer 11 are provided.
  • the n-type single crystal silicon substrate 1 has, for example, a (100) plane orientation and a specific resistance of 0.1 to 10 ⁇ ⁇ cm.
  • the n-type single crystal silicon substrate 1 has a light receiving surface textured.
  • the thickness of the n-type single crystal silicon substrate 1 is, for example, 100 to 150 ⁇ m.
  • the amorphous semiconductor layer 2 is disposed on the n-type single crystal silicon substrate 1 in contact with the light receiving surface of the n-type single crystal silicon substrate 1.
  • i-type amorphous semiconductor layers 3 and 4 are arranged on n-type single crystal silicon substrate 1 in contact with the back surface of n-type single crystal silicon substrate 1 (the surface opposite to the surface on which the texture structure is formed). .
  • the p-type amorphous semiconductor layer 5 is disposed on the i-type amorphous semiconductor layer 3 in contact with the i-type amorphous semiconductor layer 3.
  • the n-type amorphous semiconductor layer 6 is disposed on the i-type amorphous semiconductor layer 4 in contact with the i-type amorphous semiconductor layer 4.
  • the transparent conductive film 7 is disposed on the p-type amorphous semiconductor layer 5 in contact with the p-type amorphous semiconductor layer 5.
  • the transparent conductive film 8 is disposed on the n-type amorphous semiconductor layer 6 in contact with the n-type amorphous semiconductor layer 6.
  • the electrode 9 is disposed on the transparent conductive film 7 in contact with the transparent conductive film 7.
  • the electrode 10 is disposed on the transparent conductive film 8 in contact with the transparent conductive film 8.
  • the insulation increase 11 is disposed on the amorphous semiconductor layer 2 in contact with the amorphous semiconductor layer 2.
  • the amorphous semiconductor layer 2 is composed of i-type amorphous semiconductor layer / n-type amorphous semiconductor layer or n-type amorphous semiconductor layer.
  • the amorphous semiconductor layer 2 is composed of an i-type amorphous semiconductor layer / n-type amorphous semiconductor layer
  • the i-type amorphous semiconductor layer is disposed in contact with the n-type single crystal silicon substrate 1, and the n-type non-crystalline semiconductor layer 2 is formed.
  • the crystalline semiconductor layer is disposed in contact with the i-type amorphous semiconductor layer.
  • the i-type amorphous semiconductor layer is made of i-type a-Si.
  • the i-type amorphous semiconductor layer has a thickness of 1 to 10 nm, for example, a thickness of 3 nm.
  • the n-type amorphous semiconductor layer is made of n-type a-Si.
  • the n-type amorphous semiconductor layer has a thickness of 2 to 50 nm, for example, a thickness of 12 nm.
  • the n-type amorphous semiconductor layer has a thickness of 3 to 60 nm, for example, 15 nm.
  • the amorphous semiconductor layer 2 includes at least an n-type amorphous semiconductor layer having the same conductivity type as that of the n-type single crystal silicon substrate 1. As a result, the amorphous semiconductor layer 2 can suppress the minority carriers (holes) generated in the n-type single crystal silicon substrate 1 from reaching the insulating layer 11 and improve the short circuit current.
  • Each of the i-type amorphous semiconductor layers 3 and 4 is made of i-type a-Si.
  • the i-type amorphous semiconductor layer 3 has a thickness of 1 to 10 nm, for example, 2 nm.
  • the i-type amorphous semiconductor layer 4 has a thickness of 1 to 10 nm, for example, a thickness of 3 nm.
  • the thickness of the i-type amorphous semiconductor layer 4 is different from the thickness of the i-type amorphous semiconductor layer 3.
  • the thickness of the i-type amorphous semiconductor layer 4 may be the same as the thickness of the i-type amorphous semiconductor layer 3.
  • the p-type amorphous semiconductor layer 5 is made of p-type a-Si.
  • the p-type amorphous semiconductor layer 5 has a thickness of 2 to 50 nm, for example, a thickness of 25 nm.
  • the p-type amorphous semiconductor layer 5 contains, for example, boron (B) as a p-type impurity, and the B concentration is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the n-type amorphous semiconductor layer 6 is made of n-type a-Si.
  • the n-type amorphous semiconductor layer 6 has a thickness of 2 to 50 nm, for example, a thickness of 15 nm.
  • the n-type amorphous semiconductor layer 6 includes, for example, phosphorus (P) as an n-type impurity, and the P concentration is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • Each of the transparent conductive films 7 and 8 is made of ITO, SnO 2, ZnO, or the like. Each of the transparent conductive films 7 and 8 has a thickness of 70 to 100 nm.
  • Each of the electrodes 9 and 10 is made of a conductive material such as a metal such as Ag, Cu, Sn, Pt, or Au, or an alloy containing one or more of these metals.
  • a conductive material such as a metal such as Ag, Cu, Sn, Pt, or Au, or an alloy containing one or more of these metals.
  • Each of the electrodes 9 and 10 may be a single film of the metal described above or a multilayer film of the transparent conductive film and the metal.
  • the insulating layer 11 has a function as an antireflection film and a function as a protective film.
  • the insulating layer 11 is made of silicon or aluminum nitride, oxynitride and oxide, titanium, zirconium, niobium, yttrium, tantalum, or the like, and generally has a large absorption in the visible light region. Made of no dielectric.
  • the insulating layer 11 may be a single film as described above, and is preferably a multilayer film made of a material selected from the above.
  • the insulating layer 11 has a thickness of 80 to 300 nm. Thereby, the reflectance at the surface of the n-type single crystal silicon substrate 1 can be reduced, and the short-circuit current can be increased.
  • the insulating layer 11 is preferably made of silicon nitride or silicon oxynitride.
  • FIG. 2 is a plan view of the electrodes 9 and 10 on the back surface side of the photoelectric conversion element 100 shown in FIG. Referring to FIG. 2, each of electrodes 9 and 10 has a comb shape. The comb shape of the electrode 9 is arranged so as to mesh with the comb shape of the electrode 10.
  • FIG. 3 is a view showing a micrograph of the (100) plane of the n-type single crystal silicon substrate 1.
  • the silicon substrate used for the photoelectric conversion element is usually not subjected to a mirroring process such as CMP (Chemical-Mechanical Polishing) from the viewpoint of low cost.
  • CMP Chemical-Mechanical Polishing
  • the silicon substrate is planarized by chemical etching without using a mechanical polishing step as in CMP.
  • a substrate surface is called a flat substrate surface.
  • substrate surface is a board
  • etching is performed in order to remove the damage layer and the unevenness on the surface and flatten the surface.
  • this etching is called a damage layer removal etching process.
  • an alkaline solution such as sodium hydroxide (NaOH) is generally used for stabilization of the process.
  • an alkaline solution for example, NaOH etching solution: 10%, diluted with H 2 O, about 2 minutes at 80 ° C.
  • an alkaline solution for example, NaOH etching solution: 10%, diluted with H 2 O, about 2 minutes at 80 ° C.
  • etching can be performed without generating a complete pyramid shape.
  • a quadrangular uneven shape is formed as shown in FIG.
  • This rectangular uneven shape is referred to as “macro unevenness” in the embodiment of the present invention.
  • This macro unevenness is a quadrangle whose length of one side is about 10 to 50 ⁇ m, and when measuring the depth with a laser microscope or the like, it exists in a wide range from shallow to about 500 nm to several ⁇ m. ((B) of FIG. 3).
  • the angle of the slope is about 10 to 30 degrees, and most is about 20 degrees.
  • the angle of the slope here is an angle formed by the substrate surface ((100) plane) and a quadrangular slope as shown in FIG.
  • the substrate thickness is etched as thin as about 100 to 150 ⁇ m by using acid-based etching such as hydrofluoric acid.
  • acid-based etching such as hydrofluoric acid.
  • a protective film SiO 2 , SiN, etc.
  • the thickness of the protective film is about 1 to 2 ⁇ m.
  • the protective film is formed by a method such as sputtering, electron beam evaporation, and TEOS. Since the surface of the silicon substrate on which the protective film is formed is not etched with an alkaline etchant, a texture structure is not formed.
  • the n-type single crystal silicon substrate 1 having the texture structure formed only on one side can be produced.
  • macro unevenness is formed on the entire surface of the substrate, and unevenness on the order of ⁇ m is formed on the flat substrate surface on which the texture structure is not formed.
  • FIG. 4 is a view showing an SEM (Scanning Electron Microscope) photograph of the flat substrate surface.
  • the vertex area and the bottom area are always present in the pyramid shape, and such a vertex area and the bottom area are not present on the flat surface.
  • the top and bottom become carrier recombination centers that cause a decrease in the lifetime of minority carriers, this type of loss occurs because there is almost no flat substrate surface. It is difficult to perform passivation that is better than the surface on which the texture structure is formed.
  • the inclined surface of the macro unevenness has an angle of about 10 to 30 degrees.
  • the (111) plane appears by anisotropic etching, so the angle with the (100) plane is 54.7 degrees.
  • the angle is completely matched with 54.7 degrees. It is difficult to do so, but the inclination is slightly relaxed, but it is still about 50 degrees.
  • the surface orientation of silicon is greatly different between the texture structure and the macro unevenness formed on the flat substrate surface. For this reason, when amorphous silicon is deposited by the CVD method, the mechanism of passivation is greatly different.
  • the flat substrate surface is different from the surface having a texture structure in that the flat substrate surface has very fine nano irregularities on the order of nm.
  • FIG. 5 is a diagram showing an AFM image.
  • 5A is an AFM image showing a height distribution
  • FIG. 5B is a differential image of the height distribution.
  • fine irregularities of about several tens to 100 nm are formed.
  • the size is greatly different by a digit and completely different.
  • the height is about several nm, and a height of about several nm is formed on the entire surface of the substrate.
  • this unevenness is referred to as “nano-unevenness”, and an unevenness having a size smaller than 1 ⁇ m and a height smaller than 100 nm is defined as nano-unevenness.
  • corrugation whose magnitude
  • the macro unevenness and the nano unevenness are defined as described above.
  • “macro unevenness is 2 ⁇ m or less” is described in all regions of the substrate. It is not necessarily formed to be 2 ⁇ m or less, and some abnormal portions may be formed. Even in this case, since the abnormal portion is very small in area, the effect described in the embodiment of the present invention is not affected. Therefore, even if the macro unevenness is 2 ⁇ m or less or the nano unevenness is 0.75 nm or less, it is a problem if 90% or more of the total area of the silicon substrate is within the described range. Make it not exist.
  • the n-type single crystal silicon substrate 1 has macro unevenness and nano unevenness on the surface opposite to the light receiving surface (surface on which the texture structure is formed).
  • the size of the nano unevenness is defined by the average surface roughness Ra measured by AFM.
  • the average surface roughness Ra is an index for quantifying the unevenness of the surface measured by AFM, and is defined by the following equation.
  • hydrofluoric acid solution the hydrofluoric acid solution.
  • the average surface roughness Ra was smaller when treated with a solution (A) having a higher hydrofluoric acid concentration. It was found that the higher the hydrofluoric acid concentration, the lower the average surface roughness Ra, and the lower the height of the irregularities, the closer to the flat state.
  • the thickness of the silicon substrate was adjusted so that the thickness after the treatment with the solutions (A) and (B) was the same.
  • hydrofluoric acid concentration and nitric acid concentration are not limited to the above, and can be set as appropriate.
  • a photoelectric conversion element having the structure shown in FIG. 1 was produced using these substrates.
  • the size of the photoelectric conversion element was 2 cm square, and the photoelectric conversion elements were produced at equal intervals in 4 rows ⁇ 4 columns in a silicon substrate (125 mm square).
  • FIG. 6 is a diagram showing the relationship between the average surface roughness and the open circuit voltage.
  • the vertical axis represents the open circuit voltage
  • the horizontal axis represents the average surface roughness.
  • the open circuit voltage is normalized by the open circuit voltage when the height difference of the macro unevenness is 6 ⁇ m and the average surface roughness Ra is 1.15 nm.
  • the open circuit voltage Voc increases as the average surface roughness Ra decreases with respect to each height difference of the macro unevenness.
  • the open circuit voltage Voc hardly changes even if the height difference of the macro unevenness is reduced.
  • the open circuit voltage Voc is improved if the height difference of the macro unevenness is 6 ⁇ m or less. Further, the improvement rate of the open circuit voltage Voc increases as the height difference of the macro unevenness decreases in the range of 6 ⁇ m or less.
  • the open circuit voltage Voc When the nano unevenness is large, even if the level difference of the macro unevenness is reduced and flattened, the open circuit voltage Voc is not greatly improved. However, when the nano unevenness is 0.75 nm or less, the height of the macro unevenness is high. It has been found that reducing the difference is effective in improving the open circuit voltage Voc.
  • the height difference of the macro unevenness is preferably 2 ⁇ m or less. Moreover, it is more preferable that the height difference of the macro unevenness is 1 ⁇ m or less, and the average surface roughness of the nano unevenness is 0.4 nm or less. When the thickness is 0.4 nm or less, the flatness is improved, and the adhesiveness when the electrode is formed becomes uniform, so that an effect of suppressing electrode peeling is obtained.
  • the open circuit voltage Voc is correlated with the macro unevenness and the nano unevenness as follows.
  • the macro unevenness on the (100) plane has an angle of about 20 degrees from the (100) plane, and exposes a crystal plane different from the (111) plane of the texture structure.
  • nano unevenness having a large average surface roughness Ra is formed on the slope portion, it is considered that the recombination center of the carrier becomes large.
  • the open circuit voltage Voc is considered to be lower, and it is considered that the area of the slope portion is reduced by reducing the height difference of the macro unevenness.
  • the open circuit voltage Voc increases as the average surface roughness Ra decreases.
  • the pn junction is formed between the n-type single crystal silicon substrate 1 and the p-type amorphous semiconductor layer 5 deposited on the n-type single crystal silicon substrate 1.
  • the shape of the pn junction interface affects the open circuit voltage Voc. That is, it was found that the higher the open circuit voltage Voc is obtained, the smaller the average surface roughness Ra and the pn junction formed with a flat interface.
  • the average surface roughness Ra of the nano unevenness is determined by the concentration of hydrofluoric acid (mixing ratio of hydrofluoric acid and nitric acid). It was found that the unevenness can be controlled by the concentration regardless of the etching time.
  • the shape of the macro unevenness changes by adjusting the etching time.
  • the rectangular recesses seen in the macro unevenness are gradually etched by the longer etching time, and the depth of the rectangular shape (the difference in height from the surroundings) becomes smaller. Further, the angle of the quadrangular inclined portion gradually decreases from about 20 degrees.
  • the open circuit voltage Voc that determines the characteristics of the photoelectric conversion element has a strong correlation with the surface roughness of the silicon substrate. It was found that the surface roughness depends on both the macro unevenness and the nano unevenness, and the mutual roughness influences each other.
  • the open-circuit voltage Voc is improved, so the n-type single crystal silicon substrate 1 is Opposite to the surface on which the texture structure is formed, it has a surface (back surface) in which the macro unevenness is 0.6 ⁇ m or less and the average surface roughness of the nano unevenness is 0.75 nm or less.
  • FIG. 7 to 9 are first to third process diagrams showing a method for manufacturing the photoelectric conversion element 100 shown in FIG. 1, respectively.
  • the photoelectric conversion element 100 is manufactured by a plasma CVD (Chemical Vapor Deposition) method mainly using a plasma apparatus.
  • a plasma CVD Chemical Vapor Deposition
  • the plasma apparatus includes, for example, a power source that applies RF power of 13.56 MHz to the parallel plate electrodes via a matching unit.
  • the silicon substrate sliced from the silicon ingot is etched with the above-described solution (A) to produce the n-type single crystal silicon substrate 1 having macro unevenness and nano unevenness ( Step (a) in FIG. 7).
  • silicon oxide (SiO 2) having a thickness of about 100 to 300 nm is formed on one surface of the n-type single crystal silicon substrate 1 by sputtering, and 1 wt% to 5 wt% potassium hydroxide (KOH) and 1
  • the surface of the n-type single crystal silicon substrate 1 is chemically anisotropically etched by using 10% by weight of isopropyl alcohol (IPA) at a temperature of 80 ° C. to 90 ° C. for 30 minutes.
  • IPA isopropyl alcohol
  • the other surface of the silicon substrate 1 is textured (see step (b) in FIG. 7). In this case, the inclination angle of the formed pyramid shape is between 50 degrees and 60 degrees.
  • the n-type single crystal silicon substrate 1 is immersed in hydrofluoric acid to remove the natural oxide film formed on the surface of the n-type single crystal silicon substrate 1, and the surface of the n-type single crystal silicon substrate 1 is hydrogenated. Terminate.
  • the n-type single crystal silicon substrate 1 is put into the reaction chamber of the plasma apparatus.
  • the amorphous semiconductor layer 2 is formed on the light receiving surface (surface on which the texture structure is formed) of the n-type single crystal silicon substrate 1 by the plasma CVD method (see step (c) in FIG. 7).
  • the i-type amorphous semiconductor layer is formed of, for example, 40 sccm of silane (SiH 4 ) gas and 0 sccm to 100 sccm.
  • SiH 4 silane
  • the pressure was set to 40 Pa (40 to 120 Pa)
  • the substrate temperature was set to 170 ° C.
  • the n-type amorphous semiconductor layer is formed by, for example, flowing 40 sccm of SiH 4 gas, 0 sccm to 100 scm of H 2 gas, and hydrogen-diluted 40 sccm of phosphine (PH 3 ) gas into the reaction chamber.
  • set 40Pa 40 ⁇ 120Pa
  • the substrate temperature 170 °C 130 ⁇ 180 °C
  • the RF having a power density of 8.33mW / cm 2 (5 ⁇ 15mW / cm 2) through a matching unit And applied to parallel plate electrodes.
  • the concentration of PH 3 gas diluted with hydrogen is, for example, 1%.
  • the n-type amorphous semiconductor layer is formed using the above formation conditions.
  • the i-type amorphous semiconductor layer 20 is formed on the back surface (texture structure is different) of the n-type single crystal silicon substrate 1 by plasma CVD. It is formed on the surface opposite to the formed surface (see step (d) in FIG. 7).
  • a resist is applied to the entire surface of the p-type amorphous semiconductor layer 30, and the applied resist is patterned by photolithography to form a resist pattern 40 (see step (f) in FIG. 8).
  • a part of the i-type amorphous semiconductor layer 20 and the p-type amorphous semiconductor layer 30 is etched using the resist pattern 40 as a mask, and the i-type amorphous semiconductor layer 3 and the p-type amorphous semiconductor layer 5 are removed. (See step (g) in FIG. 8).
  • an i-type amorphous semiconductor layer 50 is deposited on the n-type single crystal silicon substrate 1 and the resist pattern 40 using the same formation conditions as those of the i-type amorphous semiconductor layer described above, and thereafter, an n-type amorphous semiconductor is deposited.
  • the n-type amorphous semiconductor layer 60 is formed on the i-type amorphous semiconductor layer 50 by plasma CVD using the same formation conditions as those of the porous semiconductor layer (see step (h) in FIG. 8).
  • the resist pattern 40 is removed using an alkaline solution (KOH, NaOH).
  • KOH, NaOH an alkaline solution
  • the i-type amorphous semiconductor layer / n-type amorphous semiconductor layer formed on the resist pattern 40 is removed by lift-off, and the i-type amorphous semiconductor layer 4 and the n-type amorphous semiconductor layer 6 are removed. Is formed (see step (i) in FIG. 8).
  • an insulating layer 11 made of silicon nitride is formed on the amorphous semiconductor layer 2 by a sputtering method (see step (j) in FIG. 9).
  • a transparent conductive film (ITO) is formed on the entire surface of the p-type amorphous semiconductor layer 5 and the n-type amorphous semiconductor layer 6 by a sputtering method, and subsequently, Ag is formed by an electron beam evaporation method. Then, the transparent conductive film (ITO) and Ag are etched to form the transparent conductive films 7 and 8 and the electrodes 9 and 10 (see step (k) in FIG. 9). Thereby, the photoelectric converter 100 is completed.
  • ITO transparent conductive film
  • the i-type amorphous semiconductor layer 4 / n-type amorphous semiconductor layer 6 is formed after the i-type amorphous semiconductor layer 3 / p-type amorphous semiconductor layer 5 is formed.
  • the present invention is not limited to this, and after forming the i-type amorphous semiconductor layer 4 / n-type amorphous semiconductor layer 6, the i-type amorphous semiconductor layer 3 / p-type amorphous semiconductor layer is formed. 5 may be formed.
  • the n-type single crystal silicon substrate 1 of the photoelectric conversion element 100 has a texture structure on the surface where the height difference of the macro unevenness is 0.6 ⁇ m or less and the average surface roughness of the nano unevenness is 0.75 nm or less. Therefore, the open circuit voltage of the photoelectric conversion element 100 is increased. Therefore, the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the transparent conductive film 7 is disposed between the p-type amorphous semiconductor layer 5 and the electrode 9, and the transparent conductive film is interposed between the n-type amorphous semiconductor layer 6 and the electrode 10. Since 8 is disposed, carrier recombination can be suppressed at the interface between the p-type amorphous semiconductor layer 5 and the electrode 9 and at the interface between the n-type amorphous semiconductor layer 6 and the electrode 10.
  • the light transmitted through the n-type single crystal silicon substrate 1 can be reflected at the interface between the transparent conductive film 7 and the electrode 9 and the interface between the transparent conductive film 8 and the electrode 10 to increase the short circuit current.
  • the photoelectric conversion element 100 may not include the transparent conductive film 8. This is because the transparent conductive film 8 is disposed between the n-type amorphous semiconductor layer 6 that collects majority carriers (electrons) and the electrode 10, so that recombination of carriers does not become a problem. Therefore, in the photoelectric conversion element 100, it is sufficient that a transparent conductive film is disposed between at least the p-type amorphous semiconductor layer 5 that collects minority carriers (holes) and the electrode 9.
  • the photoelectric conversion element 100 may not include the i-type amorphous semiconductor layers 3 and 4. Even without the i-type amorphous semiconductor layers 3 and 4, a pn junction (n-type single crystal silicon substrate 1 / p-type amorphous semiconductor layer 5) can be formed on the back surface of the n-type single crystal silicon substrate 1. Because it can.
  • the i-type amorphous semiconductor layers 3 and 4 are made of i-type a-Si.
  • the i-type amorphous semiconductor layers 3 and 4 are not limited to this. , I-type a-SiC, i-type a-SiN, i-type a-SiO, i-type a-SiON, i-type a-SiGe, and i-type a-Ge.
  • the i-type amorphous semiconductor layers 3 and 4 may contain P or B of 1 ⁇ 10 16 cm ⁇ 3 or less.
  • dopant impurities such as P and B are attached to the walls of the reaction chamber, and the dopant impurities are mixed when forming the i-type amorphous semiconductor layers 3 and 4. Because it does. Even if a dopant impurity having a concentration of 1 ⁇ 10 16 cm ⁇ 3 or less is mixed, an amorphous silicon film or the like containing a dopant impurity having a concentration of 1 ⁇ 10 16 cm ⁇ 3 or less is substantially i-type conductive. Has a mold. Therefore, the i-type amorphous semiconductor layers 3 and 4 only need to have substantially the i-type conductivity type.
  • the n-type amorphous semiconductor layer 3 has been described as being made of n-type a-Si, the first embodiment is not limited to this, and the n-type amorphous semiconductor layer 3 is made of n-type a-SiC, n It may be composed of any one of type a-SiN, n-type a-SiO, n-type a-SiON, n-type a-SiGe, and n-type a-Ge.
  • the p-type amorphous semiconductor layer 5 has been described as being made of p-type a-Si.
  • the first embodiment is not limited to this, and the p-type amorphous semiconductor layer 5 is composed of p-type a-SiC, p-type. It may be composed of any one of type a-SiN, p-type a-SiO, p-type a-SiON, p-type a-SiGe, and p-type a-Ge.
  • i-type a-SiC is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, and methane (CH 4 ) gas as material gases.
  • i-type a-SiN is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas and ammonia (NH 3 ) gas as material gases.
  • the i-type a-SiO is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, and O 2 gas as material gases.
  • the i-type a-SiON is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, O 2 gas, and NH 3 gas as material gases.
  • the i-type a-SiGe is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas and germane (GeH 4 ) gas as material gases.
  • i-type a-Ge is formed by the above-described plasma CVD method using H 2 gas and GeH 4 gas as material gases.
  • the n-type a-SiC is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, CH 4 gas, and PH 3 gas as material gases.
  • the n-type a-SiN is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, NH 3 gas, and PH 3 gas as material gases.
  • the n-type a-SiO is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, O 2 gas, and PH 3 gas as material gases.
  • the n-type a-SiON is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, and O 2 gas as materials gas and NH 3 gas and PH 3 gas.
  • the n-type a-SiGe is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, GeH 4 gas and PH 3 gas as material gases.
  • the n-type a-Ge is formed by the above-described plasma CVD method using H 2 gas, GeH 4 gas and PH 3 gas as material gases.
  • the p-type a-SiC is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, CH 4 gas, and B 2 H 6 gas as material gases.
  • the p-type a-SiN is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, NH 3 gas, and B 2 H 6 gas as material gases.
  • the p-type a-SiO is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, O 2 gas, and B 2 H 6 gas as material gases.
  • the p-type a-SiON is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, O 2 gas, NH 3 gas, and B 2 H 6 gas as material gases.
  • the p-type a-SiGe is formed by the above-described plasma CVD method using SiH 4 gas, H 2 gas, GeH 4 gas, and B 2 H 6 gas as material gases.
  • the p-type a-Ge is formed by the above-described plasma CVD method using H 2 gas, GeH 4 gas, and B 2 H 6 gas as material gases.
  • the photoelectric conversion element 100 may include any one of a p-type single crystal silicon substrate, an n-type polycrystalline silicon substrate, and a p-type polycrystalline silicon substrate instead of the n-type single crystal silicon substrate 1.
  • each of the p-type single crystal silicon substrate, the n-type polycrystalline silicon substrate, and the p-type polycrystalline silicon substrate is etched by the above-described method, and the macro unevenness whose height difference is 6 ⁇ m or less and the average surface roughness are It has a surface (back surface) including nano unevenness that is 0.75 nm or less.
  • the texture structure is formed by dry etching.
  • the photoelectric conversion element 100 generally only needs to include a silicon substrate.
  • the pn junction is not the light-receiving surface side where the texture structure is formed, but the macro unevenness having a height difference of 6 ⁇ m or less and the nano unevenness having an average surface roughness of 0.75 nm or less. It is arranged on the surface side having This is because the open circuit voltage is improved when the height difference of the macro unevenness is 6 ⁇ m or less and the average surface roughness of the nano unevenness is 0.75 nm or less.
  • FIG. 10 is a cross-sectional view illustrating a configuration of the photoelectric conversion element according to the second embodiment.
  • photoelectric conversion element 200 according to the second embodiment includes n-type single crystal silicon substrate 1, i-type amorphous semiconductor layers 201 and 203, n-type amorphous semiconductor layer 202, p A type amorphous semiconductor layer 204, a transparent conductive film 205, a conductive layer 206, and electrodes 207 and 208 are provided.
  • the i-type amorphous semiconductor layer 201 is made of an intrinsic amorphous semiconductor.
  • the i-type amorphous semiconductor layer 201 is disposed on the n-type single crystal silicon substrate 1 in contact with the light-receiving surface (surface on which the texture structure is formed) of the n-type single crystal silicon substrate 1.
  • the i-type amorphous semiconductor layer 201 has a thickness of 0.5 nm to 25 nm, for example.
  • the i-type amorphous semiconductor layer 201 includes i-type a-SiC, i-type a-SiO, i-type a-SiON, i-type a-SiN, i-type a-Si, i-type a-SiGe, and i-type. It consists of one of a-Ge.
  • the n-type amorphous semiconductor layer 202 is made of an amorphous semiconductor doped with n-type impurities.
  • the n-type impurity is, for example, P.
  • the n-type amorphous semiconductor layer 202 is disposed on the i-type amorphous semiconductor layer 201 in contact with the i-type amorphous semiconductor layer 201.
  • the thickness of the n-type amorphous semiconductor layer 202 is, for example, about 2 nm to about 50 nm.
  • the P concentration in the n-type amorphous semiconductor layer 202 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the n-type amorphous semiconductor layer 202 includes n-type a-SiC, n-type a-SiO, n-type a-SiON, n-type a-SiN, n-type a-Si, n-type a-SiGe, and n-type. It consists of one of a-Ge.
  • the i-type amorphous semiconductor layer 203 is disposed on the n-type single crystal silicon substrate 1 in contact with the surface opposite to the light receiving surface of the n-type single crystal silicon substrate 1.
  • the thickness of the i-type amorphous semiconductor layer 203 is the same as the thickness of the i-type amorphous semiconductor layer 201.
  • the i-type amorphous semiconductor layer 203 includes i-type a-SiC, i-type a-SiO, i-type a-SiON, i-type a-SiN, i-type a-Si, i-type a-SiGe, and i-type. It consists of one of a-Ge.
  • the p-type amorphous semiconductor layer 204 is made of an amorphous semiconductor doped with p-type impurities.
  • the p-type impurity is, for example, B.
  • the p-type amorphous semiconductor layer 204 is disposed on the i-type amorphous semiconductor layer 203 in contact with the i-type amorphous semiconductor layer 203.
  • the thickness of the p-type amorphous semiconductor layer 204 is, for example, about 2 nm to about 50 nm.
  • the p-type amorphous semiconductor layer 204 includes p-type a-SiC, p-type a-SiO, p-type a-SiON, p-type a-SiN, p-type a-Si, p-type a-SiGe, and p-type. It consists of one of a-Ge.
  • the B concentration in the p-type amorphous semiconductor layer 204 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the transparent conductive film 205 is disposed on the n-type amorphous semiconductor layer 202 in contact with the n-type amorphous semiconductor layer 202.
  • the transparent conductive film 205 is made of, for example, ITO, SnO 2, ZnO, or the like.
  • the conductive layer 206 is disposed on the p-type amorphous semiconductor layer 204 in contact with the p-type amorphous semiconductor layer 204.
  • the conductive layer 206 is made of a conductive material such as a transparent conductive film, a metal such as Ag, Cu, Sn, Pt, Au, Ti, Ta, Ni, Co, and Al, and an alloy containing one or more of those metals. Become.
  • the thickness of the conductive layer 206 is, for example, about 70 nm to about 100 nm.
  • the electrode 207 is disposed on the transparent conductive film 205 in contact with a part of the transparent conductive film 205.
  • the electrode 207 is made of Ag, for example.
  • the electrode 208 is disposed on the conductive layer 206 in contact with the conductive layer 206.
  • the electrode 208 is made of Ag, for example.
  • 11 and 12 are first and second process diagrams showing a method for manufacturing the photoelectric conversion element 200 shown in FIG. 10, respectively.
  • steps (a) and (b) in FIG. 7 are performed to produce the n-type single crystal silicon substrate 1 (steps (a) and (in FIG. 11). b)).
  • the n-type single crystal silicon substrate 1 is immersed in hydrofluoric acid to remove the natural oxide film formed on the surface of the n-type single crystal silicon substrate 1, and the surface of the n-type single crystal silicon substrate 1 is hydrogenated. Terminate.
  • the n-type single crystal silicon substrate 1 is put into the reaction chamber of the plasma apparatus.
  • the i-type amorphous semiconductor layer 201 is formed on the light-receiving surface (texture structure is formed) using the same formation conditions as those for the i-type amorphous semiconductor layers 3 and 4 described above. (Refer to step (c) in FIG. 11).
  • the n-type amorphous semiconductor layer 202 is formed on the i-type amorphous semiconductor layer 201 using the same formation conditions as those for the n-type amorphous semiconductor layer 306 described above (step (d) in FIG. )reference).
  • the i-type amorphous semiconductor layer 203 is formed on the surface opposite to the light-receiving surface of the n-type single crystal silicon substrate 1 using the same formation conditions as the i-type amorphous semiconductor layers 3 and 4. (See step (e) in FIG. 11).
  • the p-type amorphous semiconductor layer 204 is formed on the i-type amorphous semiconductor layer 203 using the same formation conditions as those for the p-type amorphous semiconductor layer 5 described above (step (f) in FIG. )reference).
  • the transparent conductive film 205 and the conductive layer 206 may be formed by a thin film forming method such as a CVD method and an evaporation method, a plating method, or a combination thereof, in addition to the sputtering method.
  • an Ag paste obtained by kneading Ag fine powder in an epoxy resin is formed by screen printing to a height of about 10 to 30 ⁇ m and a width of 100 to 500 ⁇ m, and then fired and cured at 200 ° C. for 80 minutes to form a comb shape. Electrodes 207 and 208 are formed (see step (i) in FIG. 12). Thereby, the photoelectric conversion element 200 is completed.
  • the photoelectric conversion element 200 includes the n-type single crystal silicon substrate 1 and a pn junction (n-type single crystal silicon substrate 1 / p-type amorphous semiconductor) formed by a heterojunction on the side opposite to the light receiving surface. Layer 204) is present. Therefore, the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the conductive layer 206 is disposed between the p-type amorphous semiconductor layer 204 and the electrode 208, carriers at the interface between the p-type amorphous semiconductor layer 204 and the electrode 208 are used. Can be suppressed.
  • the conductive layer 206 is made of a transparent conductive film and the electrode 208 is made of Ag, the light transmitted through the n-type single crystal silicon substrate 1 is reflected at the interface of the conductive layer 206 (transparent conductive film) / electrode 208 (Ag). And is absorbed by the n-type single crystal silicon substrate 1. Therefore, the short circuit current of the photoelectric conversion element 200 can be increased.
  • the i-type amorphous semiconductor layer 203 / p-type amorphous semiconductor layer 204 is formed on the light receiving surface side, and the i-type amorphous semiconductor layer 201 / n-type amorphous semiconductor layer 202 is formed. May be formed on the side opposite to the light receiving surface.
  • the open-circuit voltage was improved when the height difference of the macro unevenness was 6 ⁇ m or less and the average surface roughness of the nano unevenness was 0.75 nm or less. Therefore, the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the silicon substrate was etched using NaOH etching solution: 10%, diluted with H 2 O, and at 80 ° C. for about 2 minutes.
  • NaOH etching solution 10%
  • the silicon substrate was etched using H 2 O dilution at 100 ° C. for about 3 minutes.
  • FIG. 13 is a view showing a micrograph of the (100) plane of the n-type single crystal silicon substrate. When the silicon substrate is etched under the above conditions, spoon-cut macro unevenness is formed (see FIG. 13A).
  • the height difference is slightly smaller than that of the square macro unevenness (see FIG. 13B), which is preferable.
  • the height difference means a height difference from the bottom of the spoon cut portion to the highest region of the boundary with the adjacent spoon cut portion.
  • the height difference of the macro unevenness is 6 ⁇ m or less and the average surface of the nano unevenness is the same as in the first embodiment.
  • the roughness is 0.75 nm or less, the open circuit voltage is improved.
  • the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the configuration of the photoelectric conversion element in the third embodiment may be the photoelectric conversion element 100 or 200 described above, or may be a photoelectric conversion element according to the fourth or fifth embodiment described later.
  • FIG. 14 is a cross-sectional view showing the configuration of the photoelectric conversion element according to the fourth embodiment.
  • a photoelectric conversion element 400 according to Embodiment 4 includes an n-type single crystal silicon substrate 401, an antireflection film 402, a first passivation film 403, a second passivation film 404, electrodes 405, and 406.
  • N-type single crystal silicon substrate 401 includes p-type diffusion layer 4011 and n-type diffusion layer 4012 in contact with the surface opposite to the light receiving surface.
  • the p-type diffusion layers 4011 and the n-type diffusion layers 4012 are alternately arranged in the in-plane direction of the n-type single crystal silicon substrate 401.
  • the p-type diffusion layer 4011 has a B concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 , for example.
  • the p-type diffusion layer 4011 has a thickness of 100 to 200 nm, for example.
  • the n-type diffusion layer 4012 has a P concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the n-type diffusion layer 4012 has a thickness of 100 to 200 nm, for example.
  • n-type single crystal silicon substrate 401 is the same as the description of the n-type single crystal silicon substrate 1.
  • the antireflection film 402 is disposed on the n-type single crystal silicon substrate 401 in contact with the light receiving surface (the surface on which the texture structure is formed) of the n-type single crystal silicon substrate 401.
  • the antireflection film 402 is made of, for example, silicon nitride and has a thickness of, for example, 80 to 300 nm.
  • the first passivation film 403 is disposed in contact with the p-type diffusion layer 4011 of the n-type single crystal silicon substrate 401.
  • the first passivation film 403 is made of, for example, SiO 2 and has a thickness of, for example, 100 to 200 nm.
  • the second passivation film 404 is disposed in contact with a portion other than the p-type diffusion layer 4011 of the n-type single crystal silicon substrate 401.
  • the second passivation film 404 is made of, for example, silicon nitride and has a thickness of 100 to 200 nm, for example.
  • the electrode 405 is disposed in contact with the p-type diffusion layer 4011 through the first passivation film 403.
  • the electrode 405 is made of Ag, for example.
  • the electrode 406 is disposed in contact with the n-type diffusion layer 4012 through the second passivation film 404.
  • the electrode 406 is made of Ag, for example.
  • 15 to 17 are first to third process diagrams showing a method for manufacturing the photoelectric conversion element 400 shown in FIG. 14, respectively.
  • steps (a) and (b) in FIG. 7 are executed to manufacture the n-type single crystal silicon substrate 1 (steps (a) and (in FIG. 15). b)).
  • a first diffusion mask 410 made of silicon oxide is formed on the entire light receiving surface and back surface of the n-type single crystal silicon substrate 401.
  • a first etching paste is printed in a desired pattern on the first diffusion mask 410 formed on the back surface of the n-type single crystal silicon substrate 401 by a screen printing method.
  • the n-type single crystal silicon substrate 401 on which the first etching paste is printed is subjected to heat treatment. Thus, only the portion on which the first etching paste is printed is removed by etching from the first diffusion mask 410 formed on the back surface of the n-type single crystal silicon substrate 401.
  • the n-type single crystal silicon substrate 401 is immersed in water, and ultrasonic cleaning is performed by applying ultrasonic waves.
  • the first etching paste is removed, and a window 412 is formed on the back surface of the n-type single crystal silicon substrate 401 (see step (c) in FIG. 15).
  • B which is a p-type impurity
  • BSG boron silicate glass
  • a second diffusion mask 411 made of silicon oxide is formed on the entire light receiving surface and back surface of the n-type single crystal silicon substrate 401.
  • a second etching paste is printed in a desired pattern on the second diffusion mask 411 formed on the back surface of the n-type single crystal silicon substrate 401 by a screen printing method.
  • the n-type single crystal silicon substrate 401 on which the second etching paste is printed is subjected to heat treatment. Thereby, only the portion on which the second etching paste is printed is removed by etching from the second diffusion mask 411 formed on the back surface of the n-type single crystal silicon substrate 401.
  • the n-type single crystal silicon substrate 401 is immersed in water, and ultrasonic cleaning is performed by applying ultrasonic waves.
  • the second etching paste is removed, and a window 414 is formed on the back surface of the n-type single crystal silicon substrate 401 (see step (e) in FIG. 15).
  • n-type diffusion layer 4012 is formed (see step (f) in FIG. 16).
  • n-type single crystal silicon substrate 401 thermal oxidation is performed on the n-type single crystal silicon substrate 401.
  • a silicon oxide film 413 is formed on the light receiving surface of the n-type single crystal silicon substrate 401, and a passivation film 415 made of silicon oxide is formed on the back surface of the n-type single crystal silicon substrate 401 (step (g in FIG. 16). )reference).
  • an etching paste is printed on the passivation film 415 other than the portion formed on the p-type diffusion layer 4011 by a screen printing method, and the n-type single crystal silicon substrate 401 is heat-treated.
  • a portion of the passivation film 415 other than the portion formed on the p-type diffusion layer 4011 is removed, and the first passivation film 403 is formed on the p-type diffusion layer 4011 (step (h) in FIG. )reference).
  • a second passivation film 404 made of silicon nitride is formed on the back surface of the n-type single crystal silicon substrate 401 by plasma CVD (see step (i) in FIG. 16).
  • the silicon oxide film 413 formed on the light receiving surface of the n-type single crystal silicon substrate 401 is removed using a hydrogen fluoride aqueous solution or the like, and the antireflection film 402 made of silicon nitride is removed from the n-type single crystal silicon substrate 401. It is formed on the light receiving surface (see step (j) in FIG. 17).
  • an etching paste is printed by screen printing on a part of the first passivation film 403 and a part of the second passivation film 404 located on the n-type diffusion layer 4012, and the n-type single crystal silicon substrate 401 is formed. Heat treatment. Thereby, a part of the first passivation film 403 and a part of the second passivation film 404 are removed, and contact holes 416 and 417 are formed (see step (k) in FIG. 17).
  • the photoelectric conversion element 400 is opposed to the light receiving surface on which the texture structure is formed, and the height difference of the macro unevenness is 0.6 ⁇ m or less. Since the n-type single crystal silicon substrate 401 having a front surface (back surface) having an average surface roughness of unevenness of 0.75 nm or less is provided, the open circuit voltage Voc is improved. Therefore, the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • FIG. 18 is a cross-sectional view showing the configuration of the photoelectric conversion element according to the fifth embodiment.
  • photoelectric conversion element 500 according to Embodiment 5 includes n-type single crystal silicon substrate 501, antireflection film 502, insulating layer 504, and electrodes 503 and 505.
  • N-type single crystal silicon substrate 501 includes an n-type diffusion layer 5011 and a p-type diffusion layer 5012.
  • N-type diffusion layer 5011 is disposed in n-type single crystal silicon substrate 501 in contact with the light receiving surface of n-type single crystal silicon substrate 501.
  • the n-type diffusion layer 5011 has a P concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the n-type diffusion layer 5011 has a thickness of 100 to 200 nm, for example.
  • the p-type diffusion layer 5012 is disposed in the n-type single crystal silicon substrate 501 in contact with the surface opposite to the light receiving surface of the n-type single crystal silicon substrate 501.
  • the p-type diffusion layer 5012 has a B concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 , for example.
  • the p-type diffusion layer 5012 has a thickness of 100 to 200 nm, for example.
  • n-type single crystal silicon substrate 501 is the same as the description of the n-type single crystal silicon substrate 1.
  • the antireflection film 502 is disposed on the n-type single crystal silicon substrate 501 in contact with the light receiving surface of the n-type single crystal silicon substrate 501.
  • the antireflection film 502 is made of any one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the antireflection film 502 has a thickness of 80 to 300 nm in consideration of the function of preventing the reflection of incident light.
  • the electrode 503 is disposed in contact with the n-type diffusion layer 5011 of the n-type single crystal silicon substrate 501 through the antireflection film 502.
  • the electrode 503 is made of Ag, for example.
  • the insulating layer 504 is made of the same material as the antireflection film 502 and has a thickness of 100 to 200 nm.
  • the electrode 505 is disposed in contact with the p-type diffusion layer 5012 of the n-type single crystal silicon substrate 501 through the insulating layer 504.
  • the electrode 505 is made of Ag, for example.
  • the photoelectric conversion element 500 includes a pn junction (bulk region / p-type diffusion layer 5012 of the n-type single crystal silicon substrate 501) on the side opposite to the light receiving surface where the texture structure is formed.
  • 19 to 21 are first to third process diagrams showing a method for manufacturing the photoelectric conversion element 500 shown in FIG. 18, respectively.
  • P atoms are vapor-phase diffused from the light receiving surface of the n-type single crystal silicon substrate 501 into the n-type single crystal silicon substrate 501 to form an n-type diffusion layer 5011 (see step (c) in FIG. 19).
  • B atoms are vapor-phase diffused from the back surface of the n-type single crystal silicon substrate 501 into the n-type single crystal silicon substrate 501 to form a p-type diffusion layer 5012 (see step (d) in FIG. 19).
  • an antireflection film 502 is formed on the light receiving surface of the n-type single crystal silicon substrate 501 by a sputtering method (see step (e) in FIG. 19).
  • an insulating layer 504 is formed on the back surface of the n-type single crystal silicon substrate 501 by a sputtering method (see step (f) in FIG. 20).
  • a resist is applied to the entire surface of the antireflection film 502, and the applied resist is patterned by photolithography to form a resist pattern 510 (see step (g) in FIG. 20).
  • step (h) in FIG. 20 a part of the antireflection film 502 is etched using the resist pattern 510 as a mask.
  • the Ag paste is printed by screen printing, and the printed Ag paste is baked to form the electrode 503 (see step (i) in FIG. 20).
  • a resist is applied to the entire surface of the insulating layer 504, and the applied resist is patterned by photolithography to form a resist pattern 520 (see step (j) in FIG. 21).
  • a part of the insulating layer 504 is etched using the resist pattern 520 as a mask (see step (k) in FIG. 21).
  • the photoelectric conversion element 500 has a macro unevenness difference of 0.6 ⁇ m or less with respect to the light receiving surface on which the texture structure is formed, and Since the n-type single crystal silicon substrate 501 having a front surface (back surface) having an average surface roughness of nano unevenness of 0.75 nm or less is provided, the open circuit voltage Voc is improved. Therefore, the conversion efficiency can be improved by suppressing the deterioration of the passivation characteristics due to the texture structure.
  • the n-type single crystal silicon substrate 501 of the photoelectric conversion element 500 may include a p-type diffusion layer in contact with the light-receiving surface and may include an n-type diffusion layer in contact with the back surface opposite to the light-receiving surface.
  • FIG. 22 is a schematic diagram illustrating a configuration of a photoelectric conversion module including the photoelectric conversion element according to this embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.
  • the plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series. Note that the plurality of photoelectric conversion elements 1001 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel.
  • Each of the plurality of photoelectric conversion elements 1001 includes any one of the photoelectric conversion elements 100, 200, 400, and 500.
  • the cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001.
  • the output terminal 1003 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • the photoelectric conversion elements 100, 200, 400, and 500 have high conversion efficiency.
  • the conversion efficiency of the photoelectric conversion module 1000 can be improved.
  • the photoelectric conversion module according to Embodiment 6 is not limited to the configuration illustrated in FIG. 22, and may have any configuration as long as any one of the photoelectric conversion elements 100, 200, 300, 400, and 500 is used.
  • FIG. 23 is a schematic diagram showing a configuration of a photovoltaic power generation system including the photoelectric conversion element according to this embodiment.
  • the solar power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.
  • connection box 1102 is connected to the photoelectric conversion module array 1101.
  • the power conditioner 1103 is connected to the connection box 1102.
  • Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110.
  • the power meter 1105 is connected to the distribution board 1104 and the grid connection.
  • the photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.
  • connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.
  • the power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104. Further, the power conditioner 1103 may supply a part of the DC power received from the connection box 1102 to the distribution board 1104 as it is without converting the DC power into AC power.
  • Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electric equipment 1110, the distribution board 1104 supplies the surplus AC power to the grid interconnection via the power meter 1105.
  • the power meter 1105 measures power in the direction from the grid connection to the distribution board 1104 and measures power in the direction from the distribution board 1104 to the grid connection.
  • FIG. 24 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG.
  • the photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.
  • the plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Note that the plurality of photoelectric conversion modules 1120 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.
  • the output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.
  • the output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.
  • the photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.
  • the power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.
  • the distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the grid connection via the power meter 1105.
  • the distribution board 1104 receives the AC power received from the grid connection and the AC power received from the power conditioner 1103 to the electric device 1110. Supply.
  • the solar power generation system 1100 includes any one of the photoelectric conversion elements 100, 200, 400, and 500 having high conversion efficiency.
  • the conversion efficiency of the photovoltaic power generation system 1100 can be improved.
  • the photovoltaic power generation system according to Embodiment 7 is not limited to the configuration shown in FIGS. 23 and 24, and may have any configuration as long as any one of photoelectric conversion elements 100, 200, 400, and 500 is used. .
  • FIG. 25 is a schematic diagram showing a configuration of a photovoltaic power generation system including a photoelectric conversion element according to this embodiment.
  • solar power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221.
  • the photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation system 1100 illustrated in FIG.
  • the power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.
  • the transformer 1221 is connected to the power conditioners 1211 to 121n and the grid connection.
  • Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).
  • Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.
  • Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.
  • connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.
  • the current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1231 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1232 convert sunlight into electricity to generate DC power, and the generated DC power is supplied to the current collecting box 1321 through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To supply box 1321.
  • the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.
  • the j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.
  • the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.
  • the power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.
  • the transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the grid interconnection.
  • the solar power generation system 1200 includes any one of the photoelectric conversion elements 100, 200, 300, 400, and 500 having high conversion efficiency.
  • the conversion efficiency of the photovoltaic power generation system 1200 can be improved.
  • the photovoltaic power generation system according to Embodiment 8 is not limited to the configuration shown in FIG. 25, and may have any configuration as long as any one of the photoelectric conversion elements 100, 200, 400, and 500 is used.
  • the height difference of the macro unevenness is 0.6 ⁇ m or less, and the average surface roughness of the nano unevenness is
  • the n-type single crystal silicon substrate 1 having a surface (back surface) having a thickness of 0.75 nm or less it is possible to increase the open-circuit voltage and suppress the deterioration of the passivation characteristics due to the texture structure and increase the conversion efficiency. explained.
  • the height difference of the macro unevenness is 0.6 ⁇ m or less, and the nano unevenness
  • the open circuit voltage is increased, and the deterioration of the passivation characteristics due to the texture structure is suppressed, thereby converting the conversion efficiency. I explained that I can make it higher.
  • the height difference of the macro unevenness is 0.6 ⁇ m or less, and the average surface roughness of the nano unevenness is
  • an n-type single crystal silicon substrate 401 having a surface (back surface) having a thickness of 0.75 nm or less it is possible to increase the open-circuit voltage and suppress the deterioration of the passivation characteristics due to the texture structure to increase the conversion efficiency. explained.
  • the height difference of the macro unevenness is 0.6 ⁇ m or less, and the average surface roughness of the nano unevenness is 0.75 nm or less.
  • the pn junction may be either a heterojunction or a homojunction, and the arrangement position of the pn junction may be on the light receiving surface side of the silicon substrate.
  • the light receiving surface may be on the opposite side.
  • the photoelectric conversion element according to the embodiment of the present invention is a photoelectric conversion element including a silicon substrate, and the silicon substrate is opposed to the first surface on which the texture structure is formed and the first surface.
  • the texture structure is not formed, and the first surface has a second surface including the first unevenness and the second surface, and the height difference of the first unevenness is 6 ⁇ m or less, and the average of the second unevenness
  • the surface roughness should just be smaller than 0.75 nm.
  • the open-circuit voltage is improved, and the conversion efficiency is suppressed by suppressing the deterioration of the passivation characteristics due to the texture structure. It is because it can improve.
  • the photoelectric conversion element 100 in which the pn junction by the heterojunction is provided on the side opposite to the light receiving surface, it is important to form the pn junction by the heterojunction with the silicon substrate. Therefore, the photoelectric conversion element according to the embodiment of the invention preferably includes a first unevenness having a height difference of 0.6 ⁇ m or less and a second unevenness having an average surface roughness of 0.75 nm or less.
  • a first amorphous semiconductor layer disposed in contact with the second surface and having a substantially i-type conductivity, and a first amorphous semiconductor layer And a second amorphous semiconductor layer having a conductivity type opposite to that of the silicon substrate.
  • This invention is applied to a photoelectric conversion element.

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Abstract

L'invention concerne un élément de conversion photoélectrique (100) qui est pourvu d'un substrat en silicium monocristallin du type n (1). Le substrat en silicium monocristallin du type n (1) présente une surface de réception de lumière sur laquelle une structure texturée est formée, et une surface (surface arrière) opposée à la surface de réception de lumière et comprenant des macro-aspérités ayant une différence de hauteur de 0,6 µm ou moins et des nano-aspérités ayant une rugosité de surface moyenne de 0,75 nm ou moins. L'élément de conversion photoélectrique (100) est pourvu de couches de semi-conducteur amorphe du type i (3, 4), d'une couche de semi-conducteur amorphe du type p (5), et d'une couche de semi-conducteur amorphe du type n (6) sur le côté opposé à la surface de réception de lumière. La couche de semi-conducteur amorphe du type p (5) est disposée sur la couche de semi-conducteur amorphe du type i (3), et la couche de semi-conducteur amorphe du type n (6) est disposée sur la couche de semi-conducteur amorphe du type i (4). Par conséquent, une jonction pn par hétérojonction est formée côté surface arrière du substrat en silicium monocristallin du type n (1).
PCT/JP2015/051790 2014-02-13 2015-01-23 Élément de conversion photoélectrique WO2015122257A1 (fr)

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WO2017051635A1 (fr) * 2015-09-24 2017-03-30 シャープ株式会社 Substrat semi-conducteur, élément de conversion photoélectrique, procédé de fabrication de substrat semi-conducteur et procédé de fabrication d'élément de conversion photoélectrique
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EP4131425A1 (fr) * 2021-08-04 2023-02-08 Shanghai Jinko Green Energy Enterprise Management Co., Ltd. Cellule solaire, son procédé de fabrication et module photovoltaïque
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WO2008037658A2 (fr) * 2006-09-26 2008-04-03 Commissariat A L'energie Atomique Procede de realisation de cellule photovoltaique a heterojonction en face arriere
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