WO2015110069A1 - 一种基于ONO结构的SiC终端结构制备方法 - Google Patents

一种基于ONO结构的SiC终端结构制备方法 Download PDF

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WO2015110069A1
WO2015110069A1 PCT/CN2015/071458 CN2015071458W WO2015110069A1 WO 2015110069 A1 WO2015110069 A1 WO 2015110069A1 CN 2015071458 W CN2015071458 W CN 2015071458W WO 2015110069 A1 WO2015110069 A1 WO 2015110069A1
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layer
etching
silicon dioxide
sic
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杨霏
张昭
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State Grid Smart Grid Research Institute of SGCC
State Grid Corp of China SGCC
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/037Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0115Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/035Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a SiC termination structure based on an ONO structure.
  • the offset field plate is a metal that is attached to the main junction to cover the SiO2 layer on the surface of the substrate.
  • the depletion layer can be extended along the surface toward the outside of the main junction, thereby increasing the breakdown voltage.
  • Metal field plates are very simple to fabricate and can be formed with device electrodes without the need to add separate process steps. The attraction of the offset field plate to the charge in the medium makes the device using this terminal technology less sensitive to interfacial charge (especially mobile charge).
  • an ONO structure without special treatment is usually used, and a metal field plate is laid as a terminal structure, thereby reducing a local electric field, increasing surface breakdown voltage and reliability, and making the device actually hit.
  • it also acts on passivation to prevent moisture and Na + from entering the substrate.
  • the ONO structure without special treatment is used to etch and expose the active region and fill the metal field plate.
  • the defect of the structure is that while the ONO structure is etched, there is a possibility that the silicon carbide substrate is easily damaged;
  • the metal field plate has the possibility of breaking at the corner of the uppermost silicon dioxide trench, which poses a great threat to the normal use of the electrode.
  • the object of the present invention is to provide a method for fabricating an SiC terminal structure based on an ONO structure, which optimizes the ONO structure in the current silicon carbide terminal structure.
  • the invention provides a method for preparing a SiC terminal structure based on an ONO structure, which is improved in that the method comprises the following steps:
  • Step one depositing an ONO structure on the surface of the silicon carbide substrate
  • Step two coating a photoresist on the ONO structure, and forming a pattern transfer of the mesa by a photolithography process;
  • Step 3 etching the uppermost layer of silicon dioxide in the ONO structure to expose the silicon nitride of the intermediate layer;
  • Step four etching the silicon nitride of the intermediate layer in the ONO structure, and etching to the bottommost silicon dioxide;
  • Step 5 etching the third layer of residual silicon dioxide in the ONO structure to expose the active region of the silicon carbide substrate;
  • Step six annealing the silicon carbide substrate
  • Step seven depositing metal to form a metal field plate.
  • a layer is deposited on the surface of the silicon carbide substrate.
  • Silica depositing a layer on the silicon dioxide layer Silicon nitride, and finally deposit a layer on the silicon nitride layer Silica.
  • the silicon dioxide layer and the nitrogen are deposited by enhanced plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or inductively coupled plasma chemical vapor deposition (ICP-CVD). Silicon layer.
  • PECVD enhanced plasma chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • ICP-CVD inductively coupled plasma chemical vapor deposition
  • the uppermost layer of silicon dioxide in the ONO structure is wet-etched to form an inverted trapezoidal smooth trench via hole, and the smooth trench is adjusted by the ratio of the hydrofluoric acid buffer solution. Adjust between 5° and 85°; or
  • the uppermost layer of silicon dioxide in the ONO structure is dry etched to form an inverted trapezoidal smooth trench via, which is adjusted between 5° and 85° by process gas, pressure and power adjustment. .
  • the intermediate layer silicon nitride is dry-etched to form vertical trench via holes, and etched to the bottommost silicon dioxide.
  • the bottom layer of the silicon dioxide is etched by a combination of dry etching and wet etching to form a lateral groove structure at a distance from the bottom of the layer.
  • the trench at the location has a lateral recess structure, the upper portion of the lateral recess is a vertical via, and the active region of the silicon carbide substrate is exposed.
  • hydrofluoric acid buffer solution in the wet etching has a ratio of hydrofluoric acid: ammonium fluoride of 1:1 to 1:50.
  • the dry etching comprises reactive ion etching RIE and inductively coupled plasma etching ICP
  • the reactive ion etching RIE in dry etching is performed, and the process gas used is trifluoromethane CHF3 in an amount of 10 to 50 sccm, sulfur hexafluoride SF6 in an amount of 1 to 20 sccm, and oxygen O 2 in an amount of 1 to 1. 25sccm, reactive ion etching RIE RF power is 100 ⁇ 500W, reactive ion etching RIE equipment chamber pressure is 500 ⁇ 2500mTorr.
  • inductively coupled plasma etching ICP in dry etching
  • the process gas used is trifluoromethane CHF3 used in 5 to 40 sccm
  • sulfur hexafluoride SF6 is used in 1 to 45 sccm
  • oxygen O 2 is used in 1 to 20sccm
  • inductively coupled plasma etching ICP RF power is 100 ⁇ 500W
  • ICP power is 100 ⁇ 3000W
  • inductively coupled plasma etching ICP equipment cavity pressure is 5 ⁇ 60mTorr.
  • the annealing method is rapid annealing, and the temperature is in the range of 400 to 1500 degrees Celsius in a nitrogen atmosphere or an oxygen atmosphere, and the holding time is 1 to 20 minutes.
  • the deposited metal is formed by electron beam evaporation or magnetron sputtering; firstly depositing Ti in the range of 1 to 15 nm, depositing Ni in the range of 200 to 700 nm, and finally depositing a thickness of 100 Ag or Al or Cu in the range of ⁇ 500 nm.
  • the uppermost layer of silicon dioxide in the ONO structure is wet-etched to form an inverted trapezoidal gentle trench via hole, and the groove can be adjusted between 5° and 85° according to the ratio of the hydrofluoric acid buffer solution. Make adjustments. The possibility of breakage at the corners of the metal field plate is avoided.
  • the uppermost layer of silicon dioxide in the ONO structure is dry etched to form an inverted trapezoidal smooth trench via, which can be adjusted between 5° and 85° as required by process gas, pressure and power. Make adjustments. The possibility of breakage at the corners of the metal field plate is avoided.
  • Dry etching can effectively control the etching angle.
  • the intermediate layer of silicon nitride is dry etched to form vertical trench vias.
  • the third layer of silicon dioxide is etched by a dry method and a wet method to form a through hole having a special morphology.
  • the topography is divided into two parts, the upper half is a vertical groove, and the lower half is a lateral concave.
  • the trench structure is prepared to avoid damage to the active region of the silicon carbide substrate.
  • the etched ONO structure is treated by rapid annealing to make the ONO structure denser. Compared with the ONO structure without special treatment, it has extremely stable chemical properties, insulating properties and the effect of isolating metal ions.
  • FIG. 1 is a schematic view of a prior art ONO structure after processing
  • Figure 2 is a schematic view of the ONO structure before processing
  • FIG. 3 is a schematic view of the ONO structure after processing according to an embodiment of the present invention.
  • FIG. 4 is a schematic view showing a process of depositing a metal field plate after processing an ONO structure according to an embodiment of the present invention
  • the invention provides a preparation method of a SiC terminal structure using a specially treated ONO structure; after special treatment, the structure avoids the possibility of damaging the active region during engraving and the possibility of fracture when laying the metal field plate. Advantages: avoiding the damage of the active region of the silicon carbide substrate, avoiding breakage at the corners of the metal field plate, and having extremely stable chemical properties, insulating properties and the effect of isolating metal ions.
  • the method of the invention comprises the steps of:
  • Step one depositing an ONO structure on the surface of the silicon carbide substrate: depositing a layer on the surface of the silicon carbide substrate Silica, depositing a layer on the silicon dioxide layer Silicon nitride, and finally deposit a layer on the silicon nitride layer Silica.
  • PECVD Enhanced plasma chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • ICP-CVD inductively coupled plasma chemical vapor deposition
  • the photoresist is coated on the ONO structure, and the pattern transfer of the mesa is formed by photolithography: a photoresist is formed on the ONO structure to form a patterned mask layer, and an area in the ONO structure that needs to be opened is defined.
  • Step 3 etching the uppermost layer of silicon dioxide in the ONO structure to expose the intermediate layer of silicon nitride: wet etching the uppermost layer of silicon dioxide in the ONO structure to form an inverted trapezoidal gentle trench via hole. Adjusting the ratio of the hydrofluoric acid buffer solution between 5° and 85°; or
  • the uppermost layer of silicon dioxide in the ONO structure is dry etched to form an inverted trapezoidal smooth trench via, which is adjusted between 5° and 85° by process gas, pressure and power adjustment. .
  • step four the intermediate layer of silicon nitride in the ONO structure is dry etched to form vertical trench vias, and etched to the bottommost silicon dioxide.
  • Step 5 etching the third layer of residual silicon dioxide in the ONO structure to expose the active region of the silicon carbide substrate; specifically: etching the bottommost dioxide by a combination of dry etching and wet etching Silicon forms a lateral groove structure at the bottom of the layer
  • the trench at the location has a lateral recess structure, the upper portion of the lateral recess is a vertical via, and the active region of the silicon carbide substrate is exposed.
  • Hydrofluoric acid buffer solution in wet etching Hydrofluoric acid The ratio of ammonium fluoride is 1:1 to 1:50.
  • Dry etching includes reactive ion etching RIE and inductively coupled plasma etching ICP;
  • the process gas used is trifluoromethane CHF3 used in an amount of 10 to 50 sccm, sulfur hexafluoride SF6 is used in an amount of 1 to 20 sccm, and oxygen O 2 is used in an amount of 1 to 25 sccm.
  • the RF power of the ion etching RIE is 100-500 W, and the gas pressure in the chamber of the reactive ion etching RIE apparatus is 500-2500 mTorr.
  • Inductively coupled plasma etching ICP in dry etching using process gas trifluoromethane CHF3 is 5 ⁇ 40sccm, sulfur hexafluoride SF6 is 1 ⁇ 45sccm, oxygen O2 is 1 ⁇ 20sccm, inductance
  • the coupled RF plasma ICP has an RF power of 100-500 W and an ICP power of 100-3000 W.
  • the inductively coupled plasma-etched ICP device has a gas pressure of 5 to 60 mTorr.
  • Step 6 Annealing the silicon carbide substrate: the annealing method is rapid annealing, and the temperature is in the range of 400 to 1500 degrees Celsius in a nitrogen atmosphere or an oxygen atmosphere, and the holding time is 1 to 20 minutes.
  • Step 7 depositing metal to form a metal field plate: depositing metal by electron beam evaporation or magnetron sputtering; first depositing Ti in the range of 1 to 15 nm, and then depositing Ni in the range of 200 to 700 nm, Finally, Ag or Al or Cu having a thickness in the range of 100 to 500 nm is deposited.
  • Step one first deposit a thickness on the surface of the silicon carbide substrate by LPCVD in order.
  • Silica 3 preferably having a thickness of
  • a layer of thickness Silicon nitride 2 preferably having a thickness of
  • a layer of thickness is deposited Silica 1, preferably having a thickness of At this time, the ONO structure has been formed.
  • a patterned mask layer is formed on the ONO structure by using a photoresist to define an area of the ONO structure that needs to be opened.
  • Reactive ion etching (RIE) can also be used.
  • the amount of trifluoromethane (CHF3) used is 10 to 50 sccm, preferably 30 sccm, and the amount of sulfur hexafluoride (SF6) is 1 to 20 sccm, preferably 10 sccm, oxygen ( O2)
  • the amount used is 1 ⁇ 25 sccm, the preferred parameter is 8 sccm, the radio frequency power is 100 to 500 W, the preferred parameter is 350 W, the gas pressure is 500 to 2500 mTorr, and the preferred parameter is 750 mTorr.
  • ICP Inductively coupled plasma etching
  • CHF3 trifluoromethane
  • SF6 sulfur hexafluoride
  • O2 is used in an amount of 1 to 20 sccm, preferably has a parameter of 4 sccm, a radio frequency power of 100 to 500 W, a preferred parameter of 400 W, an ICP power of 100 to 3000 W, a preferred parameter of 1200 W, a gas pressure of 5 to 60 mTorr, and a preferred parameter of 30 mTorr.
  • the silicon dioxide layer 1 showed an inverted trapezoidal gentle trench with a groove angle of 40° and exposed the intermediate layer silicon nitride layer 2. The formation of gentle trenches eliminates the possibility of breakage of subsequent deposited metal field plates.
  • the silicon nitride layer 2 is dry etched, and the dry etching may be performed by reactive ion etching (RIE).
  • RIE reactive ion etching
  • the amount of trifluoromethane (CHF3) used is 10 to 50 sccm, preferably 40 sccm, sulfur hexafluoride.
  • SF6 is used in an amount of 1 to 20 sccm, preferably 12 sccm
  • oxygen (O2) is 1 ⁇ 25 sccm, preferably 8 sccm
  • radio frequency power is 100 to 500 W
  • preferred parameter is 100 W
  • air pressure is 500 to 2500 mTorr.
  • the parameter is 1850mTorr.
  • Dry etching can also be performed by inductively coupled plasma etching (ICP).
  • ICP inductively coupled plasma etching
  • the amount of trifluoromethane (CHF3) used is 5 to 40 sccm, the preferred parameter is 35 sccm, and the amount of sulfur hexafluoride (SF6) is 1 to 45 sccm.
  • 10sccm, oxygen (O2) is used in an amount of 1 to 20 sccm, preferably 8 sccm
  • RF power is 100 to 500 W, preferably 300 W
  • ICP power is 100 to 3000 W
  • preferred parameter is 200 W
  • pressure is 5 to 60 mTorr, preferably The parameter is 20mTorr.
  • the silicon nitride layer 2 forms a vertical via hole and is etched into the third layer of the silicon dioxide layer 3, so that the remaining thickness of the silicon dioxide 3 is
  • step five the remaining silicon dioxide layer 3 of the third layer is wet etched to expose the active region. Avoid damage to the active area of the substrate due to poor mastering of dry etching.
  • the silicon dioxide layer 3 of the third layer is etched to form irregular via holes.
  • the through hole is divided into two parts, and the bottom of the layer is inside the groove In the deep range, there is a lateral groove structure, and the above part of the lateral groove is a vertical through hole.
  • Step 6 as shown in FIG. 3, the above-mentioned etched ONO structure is rapidly annealed in an oxygen atmosphere at 400 to 1500 degrees Celsius, preferably at a temperature of 900 degrees Celsius, for 1 to 20 minutes, preferably for 14 minutes.
  • the structure becomes denser in the annealing process, and provides an effective guarantee for blocking the alkali metal ion pollution such as Na+ and K+.
  • Step seven deposits the metal by electron beam evaporation over the exposed edge region.
  • Ti is deposited in a thickness ranging from 1 to 15 nm, preferably to a thickness of 8 nm, and then Ni is deposited in the range of 200 to 700 nm, preferably 630 nm, and finally Cu is deposited in a thickness ranging from 100 to 500 nm, preferably having a thickness of 450 nm.
  • the metal field plate structure 4 is formed.

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Abstract

提供一种具有ONO结构的SiC终端结构制备方法,包括:步骤一,在碳化硅表面沉积ONO结构;步骤二,在ONO结构上涂覆光刻胶进行图案化;步骤三,刻蚀ONO结构最上层的二氧化硅层(1)暴露中间氮化硅层(2);步骤四,刻蚀中间氮化硅层(2),并刻蚀至最底层的二氧化硅层(3);步骤五,对ONO结构最底层的剩余的二氧化硅进行刻蚀,暴露出碳化硅衬底有源区;步骤六,对碳化硅衬底进行退火;步骤七,沉积金属,形成金属场板(4)。

Description

一种基于ONO结构的SiC终端结构制备方法 技术领域
本发明涉及半导体技术领域,具体涉及一种基于ONO结构的SiC终端结构制备方法。
背景技术
通常偏移场板是连接主结的覆盖在衬底表面SiO2层上的金属,通过在场板上加偏压可以使耗尽层沿着表面向主结外侧扩展,以此来提高击穿电压。金属场板制造非常简单,可以与器件电极一起形成,无需增加单独的工艺步骤。偏移场板对介质中电荷的吸引作用,使得采用这种终端技术的器件对界面电荷(尤其是可动电荷)不是很敏感。
随着半导体功率器件的发展,第三代宽禁带半导体碳化硅电力电子器件逐步成为发展趋势。目前,碳化硅器件终端结构中,使用厚SiO2作为金属场板的终端结构一的部分。尽管它在机械、化学和电气等方面都是非常稳定的,具有很好的钝化作用。但是于场板边缘处场板与衬底之间电位差很大,所以此处电场强度较大,击穿容易在较低电压时提前发生,而且有可能发生在表面处,对介质层有较高的要求。因此单独使用这一技术不适合较高击穿电压的分立器件。此外由于它本身固有的一些特点,导致对Na+、K+等碱金属离子掩蔽能力差,影响器件性能。
在碳化硅功率器件的终端制造工艺中,通常采用未经特殊处理的ONO结构,铺设金属场板作为终端结构,以此达到减小局部电场、提高表面击穿电压及可靠性、使器件实际击穿电压更接近平行平面结理想值而专门设计的特殊结构。另一方面对钝化也起到作用,可以阻止水汽和Na+进入衬底。
采用未经特殊处理的ONO结构,刻蚀并暴露出有源区并填充金属场板,目前,该结构的缺陷在于,刻蚀ONO结构的同时,存在容易损伤碳化硅衬底的可能;沉积的金属场板在最上方二氧化硅沟槽拐角处存在断裂的可能,对电极的正常使用有着巨大威胁。
发明内容
针对现有技术的不足,本发明的目的是提供一种基于ONO结构的SiC终端结构制备方法,对目前碳化硅终端结构中ONO结构进行优化。
本发明的目的是采用下述技术方案实现的:
本发明提供一种基于ONO结构的SiC终端结构制备方法,其改进之处在于,所述方法包括下述步骤:
步骤一,在碳化硅衬底表面沉积ONO结构;
步骤二,在ONO结构上涂覆光刻胶,采用光刻工艺形成台面的图形转移;
步骤三,对ONO结构中最上层的二氧化硅进行刻蚀,暴露出中间层的氮化硅;
步骤四,对ONO结构中的中间层的氮化硅刻蚀,并刻蚀至最底层的二氧化硅;
步骤五,对ONO结构中第三层剩余二氧化硅进行刻蚀,暴露出碳化硅衬底有源区;
步骤六,对碳化硅衬底进行退火;
步骤七,沉积金属,形成金属场板。
进一步地,所述步骤一中,在碳化硅衬底表面沉积一层
Figure PCTCN2015071458-appb-000001
的二氧化硅,在二氧化硅层上沉积一层
Figure PCTCN2015071458-appb-000002
的氮化硅,最后在氮化硅层上沉积一层
Figure PCTCN2015071458-appb-000003
的二氧化硅。
进一步地,所述步骤一中,采用增强型等离子体化学气相沉积PECVD、低压化学气相沉积LPCVD、常压化学气相沉积APCVD,或电感耦合等离子体化学气相沉积ICP-CVD沉积二氧化硅层和氮化硅层。
进一步地,所述步骤三中,采用湿法腐蚀ONO结构中最上层的二氧化硅,形成倒梯形的平缓沟槽通孔,通过氢氟酸缓冲溶液的配比调整,所述平缓沟槽在5°至85°之间进行调整;或
采用干法刻蚀ONO结构中最上层的二氧化硅,形成倒梯形的平缓沟槽通孔,通过工艺气体、压强和功率的调整,所述平缓沟槽在5°至85°之间进行调整。
进一步地,所述步骤四中,采用干法刻蚀中间层氮化硅形成垂直沟槽通孔,并刻蚀至最底层的二氧化硅。
进一步地,所述步骤五中,采用干法刻蚀和湿法腐蚀结合的方式刻蚀最底层的二氧化硅形成横向凹槽结构,在距离该层底部
Figure PCTCN2015071458-appb-000004
处的沟槽存在横向凹槽结构,横向凹槽的以上部位为垂直通孔,并且碳化硅衬底有源区暴露出来。
进一步地,所述湿法腐蚀中的氢氟酸缓冲溶液氢氟酸:氟化铵的比例为1:1至1:50。
进一步地,所述干法刻蚀包括反应离子刻蚀RIE和电感耦合等离子刻蚀ICP
进一步地,采用干法刻蚀中的反应离子刻蚀RIE,使用的工艺气体三氟甲烷CHF3使用量为10~50sccm、六氟化硫SF6使用量为1~20sccm、氧气O2使用量为1~25sccm,反应离子刻蚀RIE的射频功率为100~500W,反应离子刻蚀RIE设备腔体内气压为500~2500mTorr。
进一步地,采用干法刻蚀中电感耦合等离子刻蚀ICP,使用的工艺气体三氟甲烷CHF3使用量为5~40sccm、六氟化硫SF6使用量为1~45sccm、氧气O2使用量为1~20sccm,电感耦合等离子刻蚀ICP的射频功率为100~500W、ICP功率为100~3000W,电感耦合等离子刻蚀ICP设备腔体内气压为5~60mTorr。
进一步地,所述步骤六中,采用的退火方式为快速退火,在氮气气氛或氧气气氛中,温度在400~1500摄氏度范围内,保持时间为1~20分钟。
进一步地,所述步骤七中,沉积金属采用电子束蒸发方式或磁控溅射方式;首先沉积厚度为1~15nm范围内的Ti,再沉积200~700nm范围内的Ni,最后沉积厚度为100~500nm范围内的Ag或Al或Cu。
与现有技术比,本发明达到的有益效果是:
1.采用湿法腐蚀ONO结构中最上层的二氧化硅形成倒梯形的平缓沟槽通孔,通过氢氟酸缓冲溶液的配比调整,该沟槽可根据需要在5°至85°之间进行调整。避免了金属场板拐角处存在断裂的可能。
2.采用干法刻蚀ONO结构中最上层的二氧化硅形成倒梯形的平缓沟槽通孔,通过工艺气体、压强、功率的调整,该沟槽可根据需要在5°至85°之间进行调整。避免了金属场板拐角处存在断裂的可能。
3.采用干法刻蚀能够有效控制刻蚀角度。干法刻蚀中间层氮化硅形成垂直沟槽通孔。
4.采用干法和湿法结合的方式刻蚀第三层二氧化硅形成特殊形貌的通孔,形貌分为两部分,上半部为垂直沟槽,下半部沟槽存在横向凹槽结构,制备该结构的目的在于避免了碳化硅衬底有源区的损伤。
5.采用快速退火方式处理刻蚀后的ONO结构,使ONO结构更加致密,相比较未经特殊处理的ONO结构,有着极稳的化学性质、绝缘性质和隔离金属离子污染的效果。
6.避免了碳化硅衬底有源区的损伤,避免金属场板拐角处出现断裂,有着极稳的化学性质、绝缘性质和隔离金属离子污染的效果。
附图说明
图1是现有技术的ONO结构加工后的示意图;
图2是ONO结构加工前的示意图;
图3是本发明实施例的ONO结构加工后的示意图;
图4是本发明实施例的ONO结构加工后并沉积金属场板的示意图;
其中:1-最上层的二氧化硅层;2-中间氮化硅;3-最底层二氧化硅;4-金属场板结构。
具体实施方式
下面结合附图对本发明的具体实施方式作进一步的详细说明。
本发明提供一种采用经特殊处理的ONO结构SiC终端结构的制备方法;经特殊处理后,该结构避免了刻槽时损伤有源区的可能,以及铺设金属场板时断裂的可能。优点:避免了碳化硅衬底有源区的损伤,避免金属场板拐角处出现断裂,有着极稳的化学性质、绝缘性质和隔离金属离子污染的效果。
本发明的方法包括下述步骤:
步骤一,在碳化硅衬底表面沉积ONO结构:在碳化硅衬底表面沉积一层
Figure PCTCN2015071458-appb-000005
的二氧化硅,在二氧化硅层上沉积一层
Figure PCTCN2015071458-appb-000006
的氮化硅,最后在氮化硅层上沉积一层
Figure PCTCN2015071458-appb-000007
的二氧化硅。
采用增强型等离子体化学气相沉积PECVD、低压化学气相沉积LPCVD、常压化学气相沉积APCVD,或电感耦合等离子体化学气相沉积ICP-CVD沉积二 氧化硅层和氮化硅层。
步骤二,在ONO结构上涂覆光刻胶,采用光刻工艺形成台面的图形转移:在ONO结构上采用光刻胶形成图形化的掩膜层,定义出ONO结构中需要开窗的区域。
步骤三,对ONO结构中最上层的二氧化硅进行刻蚀,暴露出中间层的氮化硅:采用湿法腐蚀ONO结构中最上层的二氧化硅,形成倒梯形的平缓沟槽通孔,通过氢氟酸缓冲溶液的配比调整,所述平缓沟槽在5°至85°之间进行调整;或
采用干法刻蚀ONO结构中最上层的二氧化硅,形成倒梯形的平缓沟槽通孔,通过工艺气体、压强和功率的调整,所述平缓沟槽在5°至85°之间进行调整。
步骤四,采用干法刻蚀ONO结构中的中间层氮化硅形成垂直沟槽通孔,并刻蚀至最底层的二氧化硅。
步骤五,对ONO结构中第三层剩余二氧化硅进行刻蚀,暴露出碳化硅衬底有源区;具体为:采用干法刻蚀和湿法腐蚀结合的方式刻蚀最底层的二氧化硅形成横向凹槽结构,在距离该层底部
Figure PCTCN2015071458-appb-000008
处的沟槽存在横向凹槽结构,横向凹槽的以上部位为垂直通孔,并且碳化硅衬底有源区暴露出来。
湿法腐蚀中的氢氟酸缓冲溶液氢氟酸:氟化铵的比例为1:1至1:50。
干法刻蚀包括反应离子刻蚀RIE和电感耦合等离子刻蚀ICP;
采用干法刻蚀中的反应离子刻蚀RIE,使用的工艺气体三氟甲烷CHF3使用量为10~50sccm、六氟化硫SF6使用量为1~20sccm、氧气O2使用量为1~25sccm,反应离子刻蚀RIE的射频功率为100~500W,反应离子刻蚀RIE设备腔体内气压为500~2500mTorr。
采用干法刻蚀中电感耦合等离子刻蚀ICP,使用的工艺气体三氟甲烷CHF3使用量为5~40sccm、六氟化硫SF6使用量为1~45sccm、氧气O2使用量为1~20sccm,电感耦合等离子刻蚀ICP的射频功率为100~500W、ICP功率为100~3000W,电感耦合等离子刻蚀ICP设备腔体内气压为5~60mTorr。
步骤六,对碳化硅衬底进行退火:采用的退火方式为快速退火,在氮气气氛或氧气气氛中,温度在400~1500摄氏度范围内,保持时间为1~20分钟。
步骤七,沉积金属,形成金属场板:沉积金属采用电子束蒸发方式或磁控溅射方式;首先沉积厚度为1~15nm范围内的Ti,再沉积200~700nm范围内的Ni, 最后沉积厚度为100~500nm范围内的Ag或Al或Cu。
实施例
步骤一,如图2所示,采用LPCVD按照顺序在碳化硅衬底表面首先沉积一层厚度为
Figure PCTCN2015071458-appb-000009
的二氧化硅3,优选厚度为
Figure PCTCN2015071458-appb-000010
再在沉积一层厚度为
Figure PCTCN2015071458-appb-000011
的氮化硅2,优选厚度为
Figure PCTCN2015071458-appb-000012
最后再在沉积一层厚度为
Figure PCTCN2015071458-appb-000013
的二氧化硅1,优选厚度为
Figure PCTCN2015071458-appb-000014
此时,已经形成了ONO结构。
步骤二,在ONO结构上采用光刻胶形成图形化的掩膜层,定义出ONO结构中需要开窗的区域。
步骤三,采用湿法腐蚀氢氟酸缓冲溶液(氢氟酸:氟化铵=1:30),腐蚀最上层的二氧化硅层1,腐蚀时间为2分钟。也可以采用反应离子刻蚀(RIE),三氟甲烷(CHF3)使用量为10~50sccm,优选参数为30sccm,六氟化硫(SF6)使用量为1~20sccm,优选参数为10sccm,氧气(O2)使用量为1^25sccm,优选参数为8sccm,射频功率为100~500W,优选参数为350W,气压为500~2500mTorr,优选参数为750mTorr。
也可以采用电感耦合等离子刻蚀(ICP),三氟甲烷(CHF3)使用量为5~40sccm,优选参数为25sccm,六氟化硫(SF6)使用量为1~45sccm,优选参数为15sccm,氧气(O2)使用量为1~20sccm,优选参数为4sccm,射频功率为100~500W,优选参数为400W,ICP功率为100~3000W,优选参数为1200W,气压为5~60mTorr,优选参数为30mTorr。此时二氧化硅层1出现了倒梯形的平缓沟槽,沟槽角度为40°,并且暴露出了中间层氮化硅层2。平缓沟槽的形成,消除了后续沉积金属场板存在断裂的可能。
步骤四,采用干法刻蚀氮化硅层2,干法刻蚀可以采用反应离子刻蚀(RIE),三氟甲烷(CHF3)使用量为10~50sccm,优选参数为40sccm,六氟化硫(SF6)使用量为1~20sccm,优选参数为12sccm,氧气(O2)使用量为1^25sccm,优选参数为8sccm,射频功率为100~500W,优选参数为100W,气压为500~2500mTorr,优选参数为1850mTorr。
干法刻蚀也可以采用电感耦合等离子刻蚀(ICP),三氟甲烷(CHF3)使用量为5~40sccm,优选参数为35sccm,六氟化硫(SF6)使用量为1~45sccm,优选参数为10sccm,氧气(O2)使用量为1~20sccm,优选参数为8sccm,射频功 率为100~500W,优选参数为300W,ICP功率为100~3000W,优选参数为200W,气压为5~60mTorr,优选参数为20mTorr。此时,氮化硅层2形成垂直通孔,并过刻到第三层的二氧化硅层3,使二氧化硅3剩余厚度为
Figure PCTCN2015071458-appb-000015
步骤五,湿法腐蚀第三层剩余的二氧化硅层3,暴露出有源区。避免由于干法刻蚀掌握不佳造成衬底有源区损伤。此时,第三层的二氧化硅层3经过刻蚀后,形成了不规则的通孔。通孔分为两部分,在沟槽内距离该层底部
Figure PCTCN2015071458-appb-000016
深处范围内,存在横向凹槽结构,横向凹槽的以上部位为垂直通孔。
步骤六,如图3所示,对上述经过刻蚀加工后的ONO结构,在氧气气氛中进行快速退火400~1500摄氏度,优选参数900摄氏度,保持1~20分钟,优选参数14分钟。使该结构在退火过程中变得更加致密,为阻挡Na+、K+等碱金属离子污染提供了有效保障。
步骤七,如图4所示,在暴露出的有缘区域上方采用电子束蒸发沉积金属。先沉积厚度为1~15nm范围内的Ti,优选厚度为8nm,再沉积200~700nm范围内的Ni,优选厚度为630nm,最后沉积厚度为100~500nm范围内的Cu,优选厚度为450nm。此时,形成了金属场板结构4。
最后应当说明的是:以上实施例仅用以说明本发明的技术方案而非对其限制,尽管参照上述实施例对本发明进行了详细的说明,所属领域的普通技术人员应当理解:依然可以对本发明的具体实施方式进行修改或者等同替换,而未脱离本发明精神和范围的任何修改或者等同替换,其均应涵盖在本发明的权利要求范围当中。

Claims (12)

  1. 一种基于ONO结构的SiC终端结构制备方法,其特征在于,所述方法包括下述步骤:
    步骤一,在碳化硅衬底表面沉积ONO结构;
    步骤二,在ONO结构上涂覆光刻胶,采用光刻工艺形成台面的图形转移;
    步骤三,对ONO结构中最上层的二氧化硅进行刻蚀,暴露出中间层的氮化硅;
    步骤四,对ONO结构中的中间层的氮化硅刻蚀,并刻蚀至最底层的二氧化硅;
    步骤五,对ONO结构中第三层剩余二氧化硅进行刻蚀,暴露出碳化硅衬底有源区;
    步骤六,对碳化硅衬底进行退火;
    步骤七,沉积金属,形成金属场板。
  2. 如权利要求1所述的SiC终端结构制备方法,其特征在于,所述步骤一中,在碳化硅衬底表面沉积一层
    Figure PCTCN2015071458-appb-100001
    的二氧化硅,在二氧化硅层上沉积一层
    Figure PCTCN2015071458-appb-100002
    的氮化硅,最后在氮化硅层上沉积一层
    Figure PCTCN2015071458-appb-100003
    的二氧化硅。
  3. 如权利要求2所述的SiC终端结构制备方法,其特征在于,所述步骤一中,采用增强型等离子体化学气相沉积PECVD、低压化学气相沉积LPCVD、常压化学气相沉积APCVD,或电感耦合等离子体化学气相沉积ICP-CVD沉积二氧化硅层和氮化硅层。
  4. 如权利要求1所述的SiC终端结构制备方法,其特征在于,所述步骤三中,采用湿法腐蚀ONO结构中最上层的二氧化硅,形成倒梯形的平缓沟槽通孔,通过氢氟酸缓冲溶液的配比调整,所述平缓沟槽在5°至85°之间进行调整;或
    采用干法刻蚀ONO结构中最上层的二氧化硅,形成倒梯形的平缓沟槽通孔,通过工艺气体、压强和功率的调整,所述平缓沟槽在5°至85°之间进行调整。
  5. 如权利要求1所述的SiC终端结构制备方法,其特征在于,所述步骤四中,采用干法刻蚀中间层氮化硅形成垂直沟槽通孔,并刻蚀至最底层的二氧化硅。
  6. 如权利要求1所述的SiC终端结构制备方法,其特征在于,所述步骤五 中,采用干法刻蚀和湿法腐蚀结合的方式刻蚀最底层的二氧化硅形成横向凹槽结构,在距离该层底部
    Figure PCTCN2015071458-appb-100004
    处的沟槽存在横向凹槽结构,横向凹槽的以上部位为垂直通孔,并且碳化硅衬底有源区暴露出来。
  7. 如权利要求4或6所述的SiC终端结构制备方法,其特征在于,所述湿法腐蚀中的氢氟酸缓冲溶液氢氟酸:氟化铵的比例为1:1至1:50。
  8. 如权利要求4或5所述的SiC终端结构制备方法,其特征在于,所述干法刻蚀包括反应离子刻蚀RIE和电感耦合等离子刻蚀ICP
  9. 如权利要求8所述的SiC终端结构制备方法,其特征在于,采用干法刻蚀中的反应离子刻蚀RIE,使用的工艺气体三氟甲烷CHF3使用量为10~50sccm、六氟化硫SF6使用量为1~20sccm、氧气O2使用量为1~25sccm,反应离子刻蚀RIE的射频功率为100~500W,反应离子刻蚀RIE设备腔体内气压为500~2500mTorr。
  10. 如权利要求8所述的SiC终端结构制备方法,其特征在于,采用干法刻蚀中电感耦合等离子刻蚀ICP,使用的工艺气体三氟甲烷CHF3使用量为5~40sccm、六氟化硫SF6使用量为1~45sccm、氧气O2使用量为1~20sccm,电感耦合等离子刻蚀ICP的射频功率为100~500W、ICP功率为100~3000W,电感耦合等离子刻蚀ICP设备腔体内气压为5~60mTorr。
  11. 如权利要求1所述的SiC终端结构制备方法,其特征在于,所述步骤六中,采用的退火方式为快速退火,在氮气气氛或氧气气氛中,温度在400~1500摄氏度范围内,保持时间为1~20分钟。
  12. 如权利要求1所述的SiC终端结构制备方法,其特征在于,所述步骤七中,沉积金属采用电子束蒸发方式或磁控溅射方式;首先沉积厚度为1~15nm范围内的Ti,再沉积200~700nm范围内的Ni,最后沉积厚度为100~500nm范围内的Ag或Al或Cu。
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