CN103811406B - 改善sonos器件自对准接触孔漏电的方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
Abstract
本发明公开了一种改善SONOS器件自对准接触孔漏电的方法,包括:1)进行SONOS器件自对准接触孔刻蚀;2)在接触孔的侧壁和底部以及SONOS器件中的未掺杂氧化膜上方,成长氮化硅膜;3)刻蚀氮化硅膜,使只在接触孔侧壁上保留氮化硅膜;4)用传统湿法流程清洗去除刻蚀产生的聚合物,得到SONOS器件自对准接触孔。本发明可以弥补常规自对准接触孔刻蚀中造成的栅极上侧墙的过度损耗,能够明显增加氮化硅膜侧墙残留的厚度,避免栅极与金属线短路,改善产品的自对准接触孔漏电,提高接触孔击穿电压,扩大SONOS器件自对准接触孔刻蚀工艺窗口。
Description
技术领域
本发明涉及一种改善自对准接触孔漏电的方法,特别是涉及一种改善SONOS(Silicon-Oxide-Nitride-Oxide-Silicon)器件自对准接触孔漏电的方法。
背景技术
SONOS(硅-氧化物-氮化物-氧化物-硅)器件,是一种和闪存联系较为紧密的非易失性存储器。
在SONOS器件自对准接触孔工艺中,为了降低光刻的对准难度,缩小芯片面积,提高产品的集成度,取消了作为阻挡层的氮化硅(SiN)阻挡层。在刻蚀穿过花苞状外壳图形时,很容易造成氮化膜侧墙损耗太多,接触孔与栅极(Poly)之间的阻挡过薄,在高电压下容易击穿导致金属线与栅极短路,造成自对准接触孔漏电,降低了器件的击穿电压,最终造成晶圆周边良率低下。其中,图1为清扫后自对准接触孔图形(极端情况),接触孔侧墙损耗过多,容易造成填充的金属与栅极短路,进而造成器件漏电。
因此,需要对SONOS器件自对准接触孔工艺进行进一步的研究改善,以改善自对准接触孔漏电情况。
发明内容
本发明要解决的技术问题是提供一种改善SONOS器件自对准接触孔漏电的方法。该方法通过在常规自对准接触孔刻蚀后,增加一步成膜和干法刻蚀的方案,可以改善接触孔漏电,增大SONOS器件自对准接触孔刻蚀工艺窗口。
为解决上述技术问题,本发明的改善SONOS器件自对准接触孔漏电的方法,包括步骤:
1)进行常规的SONOS器件自对准接触孔刻蚀;
2)在接触孔的侧壁和底部以及SONOS器件中的未掺杂氧化膜上方,成长氮化硅膜;
3)刻蚀氮化硅膜,使只在接触孔侧壁上保留氮化硅膜,即在接触孔侧壁上残留部分氮化硅膜;
4)清洗,得到SONOS器件自对准接触孔。
所述步骤2)中,成长氮化硅膜的工艺为低压成长氮化硅膜工艺。其中,工艺参数为:低压的压力范围为0.008Kpa~0.0266Kpa,温度为600~800℃,氮化硅膜的厚度为100~300埃。
所述步骤3)中,刻蚀的方法为干法刻蚀,选用较高的氮化硅/氧化硅(SiN/SiO2)选择比,如选择比为2~5。其中,该刻蚀的工艺参数包括:射频功率为100~300瓦,腔体压力为20~100毫托,静电吸盘(ESC)背部压力为0~20托,四氟乙烷(CF4)流量为0~50sccm,氩气(Ar)流量为0~600sccm,三氟甲烷(CHF3)流量为0~20sccm,氧气(O2)流量为0~20sccm,一氧化碳(CO)流量为0~200sccm。
所述步骤3)中,保留的氮化硅膜的厚度为20~80埃。
所述步骤4)中,清洗的方法可为采用湿法,清洗去除刻蚀产生的聚合物。
本发明在常规自对准接触孔刻蚀流程完成后,增加低压成长一定厚度氮化硅工序(LPN),并立即通过干法刻蚀方法去除孔顶部未掺杂氧化膜上的氮化硅。该步刻蚀要保证顶部氮化膜被全部去除,而由于干法刻蚀中侧壁有聚合物阻挡,控制适当时间和气体组分配比,可以调节横向刻蚀和纵向刻蚀速率,能保证孔顶全部刻蚀完,且侧壁有一定厚度氮化硅残留。因此,通过增加一步成膜和回刻(干法刻蚀)的方案,可以弥补常规自对准接触孔刻蚀中造成的栅极上侧墙的过度损耗,能够明显增加氮化硅膜侧墙残留的厚度,避免栅极与金属线短路,改善产品的自对准接触孔漏电特性,提高接触孔击穿电压,扩大SONOS器件自对准接触孔刻蚀工艺窗口。
附图说明
下面结合附图与具体实施方式对本发明作进一步详细的说明:
图1是清扫后自对准接触孔刻蚀图形;
图2是常规自对准接触孔示意图;
图3是氮化硅成膜后的示意图;
图4是氮化硅成膜后的局部SEM(扫描电子显微镜)视图,其中,a为接触孔顶部位置,b为接触孔底部位置;
图5是干法刻蚀后的示意图;
图6是本发明的成膜并回刻后的TEM(透射电子显微镜)视图,其中,a为接触孔全视图,b为接触孔底部放大图。
图中附图标记说明如下:
1为未掺杂氧化膜,2为磷硅玻璃,3为衬底,4为花苞状外壳,5为氧化硅,6为氮化硅,7为栅极,8为浅沟道隔离层,9为低压成长的氮化硅膜,10为刻蚀后残留的氮化硅,11为接触孔。
具体实施方式
本发明的改善SONOS器件自对准接触孔漏电的方法,具体步骤如下:
1)进行常规的SONOS器件自对准接触孔11刻蚀。在干法刻蚀机台上,自上而下依次刻穿有机抗反射层(BARC),磷硅玻璃(PSG)和未掺杂氧化硅三层薄膜(USG),并停在硅衬底上,其中,刻蚀后的示意图如图2所示;
本步骤中,氮化硅6覆盖于栅极7的周侧并用于做栅极7的侧墙,层间膜包括磷硅玻璃2即掺杂有磷的二氧化硅和未掺杂氧化膜1,其中,磷硅玻璃2在栅极7附近会形成包围栅极7的花苞状结构,花苞状结构如区域5和区域4处所对应的磷掺杂浓度不同。
2)在接触孔11的侧壁和底部以及SONOS器件中的未掺杂氧化膜1上方,经低压成长工艺,成长氮化硅膜9(如图3所示);
其中,低压成长的工艺参数为:低压的压力范围为0.008Kpa~0.0266Kpa,温度为600~800℃,氮化硅膜9的厚度为100~300埃。
本步骤中,氮化硅膜9各处成长较均匀,成膜后的形貌可如图4所示。该图中,孔顶部、侧壁和底部氮化硅膜厚均为100埃左右。
3)采用干法刻蚀工艺,选用选择比为2~5的氮化硅对氧化硅(SiN/SiO2)选择比,进行回刻,以刻蚀氮化硅膜9,最终在接触孔11侧壁上残留部分氮化硅膜,即刻蚀后残留的氮化硅10(如图5所示),残留的氮化硅10的厚度为20~80埃;
其中,刻蚀的主要工艺参数如下:
射频功率为100~300瓦,腔体压力为20~100毫托,静电吸盘(ESC)背部压力为0~20托,四氟乙烷(CF4)流量为0~50sccm,氩气(Ar)流量为0~600sccm,三氟甲烷(CHF3)流量为0~20sccm,氧气(O2)流量为0~20sccm,一氧化碳(CO)流量为0~200sccm。
本步骤中,由于接触孔11的孔顶未掺杂氧化膜1上方和侧壁的氮化硅膜覆盖较均匀,选用合适的气体组分,能保证有较高的纵向刻蚀速率和较低的刻蚀速率,因此,将顶部和底部氮化硅膜刚好刻蚀完时,此时侧壁氮化硅膜会有一部分残留,可以弥补栅极上氮化膜侧墙的损耗,其中,回刻后的形貌可如图6所示。图6a为接触孔全视图,图6b为底部放大图,侧壁残留氮化硅厚度在20~80埃。
4)用传统湿法流程,清洗去除刻蚀产生的聚合物,得到SONOS器件自对准接触孔。
综上所述,本发明在形成自对准接触孔形貌后,针对刻蚀后氮化膜侧墙损耗太多情况,增加一步新的工序:沿着孔周边成长一定厚度的氮化硅膜,然后立即通过干法刻蚀,利用干法刻蚀各向异性的特点,去除孔顶的氮化硅膜,而只保留侧壁的氮化膜。由于接触孔11的底部和顶部没有氮化硅膜残留,而侧墙有氮化硅膜残留,增加了侧墙厚度,可以提高SONOS器件击穿电压,避免栅极与金属线短路,改善自对准接触孔漏电。
Claims (5)
1.一种改善SONOS器件自对准接触孔漏电的方法,其特征在于,包括步骤:
1)进行SONOS器件自对准接触孔刻蚀;
在所述SONOS器件的栅极周侧覆盖有氮化硅侧墙,覆盖在所述SONOS器件表面的层间膜包括磷硅玻璃和未掺杂氧化膜;其中,所述磷硅玻璃在栅极附近会形成包围栅极的花苞状结构,利用所述花苞状结构本身具有的不同磷掺杂浓度的区域以及所述花苞状结构内部和外部的磷掺杂浓度不同以及磷硅玻璃的磷掺杂浓度不同时刻蚀速率不同的特征自对准形成所述接触孔,所述接触孔穿过相邻的所述花苞状结构之间的区域;
所述氮化硅侧墙不作为所述自对准接触孔刻蚀时的刻蚀阻挡层,在自对准接触孔刻蚀过程中所述氮化硅侧墙会有损耗;
2)在接触孔的侧壁和底部以及SONOS器件中的未掺杂氧化膜上方,成长氮化硅膜;
3)刻蚀氮化硅膜,使只在接触孔侧壁上保留氮化硅膜;保留于所述侧壁上的所述氮化硅膜用于补偿步骤1)中所述氮化硅侧墙的损耗;
4)清洗,得到SONOS器件自对准接触孔。
2.如权利要求1所述的方法,其特征在于:所述步骤2)中,成长氮化硅膜的工艺为低压成长氮化硅膜工艺;其中,工艺参数为:低压的压力范围为0.008Kpa~0.0266Kpa,温度为600~800℃,氮化硅膜的厚度为100~300埃。
3.如权利要求1所述的方法,其特征在于:所述步骤3)中,刻蚀的方法为干法刻蚀,选用对氮化硅/氧化硅选择比为2~5的干法刻蚀;
其中,该刻蚀的工艺参数包括:射频功率为100~300瓦,腔体压力为20~100毫托,静电吸盘背部压力为0~20托,四氟乙烷流量为0~50sccm,氩气流量为0~600sccm,三氟甲烷流量为0~20sccm,氧气流量为0~20sccm,一氧化碳流量为0~200sccm。
4.如权利要求1所述的方法,其特征在于:所述步骤3)中,保留的氮化硅膜的厚度为20~80埃。
5.如权利要求1所述的方法,其特征在于:所述步骤4)中,清洗的方法采用湿法清洗,清洗去除刻蚀产生的聚合物。
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