WO2015100989A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2015100989A1
WO2015100989A1 PCT/CN2014/081246 CN2014081246W WO2015100989A1 WO 2015100989 A1 WO2015100989 A1 WO 2015100989A1 CN 2014081246 W CN2014081246 W CN 2014081246W WO 2015100989 A1 WO2015100989 A1 WO 2015100989A1
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Prior art keywords
electrostatic discharge
lead
array substrate
short
discharge device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2014/081246
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English (en)
French (fr)
Inventor
闫岩
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/431,488 priority Critical patent/US9799259B2/en
Publication of WO2015100989A1 publication Critical patent/WO2015100989A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • Embodiments of the present invention relate to an array substrate, a display panel, and a display device. Background technique
  • the display device can use a plurality of different display panels, for example, an organic light-emitting diode (OLED) panel, and a thin film transistor liquid crystal display (TFT-LCD) panel.
  • OLED organic light-emitting diode
  • TFT-LCD thin film transistor liquid crystal display
  • a TFT-LCD is usually formed by an array substrate and a color filter substrate.
  • the gate lines and the data lines define pixel regions by crossing each other, and pixel electrodes and thin film transistors are disposed in the respective pixel regions.
  • a black matrix and a color filter layer corresponding to each pixel region are disposed on the color filter substrate.
  • a common electrode line is disposed on the array substrate.
  • a liquid crystal is filled between the array substrate and the color filter substrate.
  • the electric field is formed by loading the gate driving signal and the data signal (the voltage of the pixel electrode), the electric field controls the deflection of the liquid crystal to control the intensity of the light, and in combination with the color filter function of the color filter substrate, the display panel can display the desired expression.
  • Embodiments of the present invention provide an array substrate, a display panel, and a display device for avoiding circuit breakdown and damage caused by a large accumulation of electric charge in the circuit when the panel is subjected to pressing or rubbing.
  • An array substrate provided by an embodiment of the invention includes a plurality of data lines, a plurality of gate lines, a first lead, and/or a second lead.
  • the array substrate includes a first lead, at least one data line is connected to the first lead through at least one first electrostatic discharge device, and each first electrostatic discharge device is connected to only one data line; the first electrostatic discharge device Turning on when the voltage of the signal on the connected data line is greater than the first threshold, and turning off when the voltage of the signal on the connected data line is not greater than the second threshold, on the first lead The voltage of the signal is not greater than the second threshold.
  • each second electrostatic discharge device is connected to only one gate line; the second electrostatic discharge device is configured to be turned on when the voltage of the signal on the connected gate line is greater than a third threshold, and The voltage of the signal on the connected gate line is turned off when the voltage of the signal is not greater than the fourth threshold, and the voltage of the signal on the second lead is not greater than the fourth threshold.
  • the embodiment of the invention further provides a display panel comprising the array substrate provided by the embodiment of the invention.
  • a display device provided by an embodiment of the present invention includes a display panel provided by an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an electrostatic discharge device
  • FIG. 2a is a schematic structural view of one of the array substrates according to an embodiment of the present invention.
  • FIG. 2b is a schematic structural diagram of an array substrate 2 according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a third array substrate according to an embodiment of the present invention.
  • 4a is a schematic structural diagram of a fourth array substrate according to an embodiment of the present invention.
  • 4b is a schematic structural diagram of a fifth array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a sixth array substrate according to an embodiment of the present invention. detailed description
  • the inventors of the present application have noticed that during the manufacturing and transportation process, the display panel is easily squeezed or rubbed, and it is easy to accumulate a large amount of electric charge in the circuit of the display panel, and these static charges are likely to break through the display panel. The circuit, thereby causing damage to the circuit in the display panel.
  • At least one embodiment of the present invention provides an array substrate, in which at least one data line is connected to a first lead on the array substrate by at least one first electrostatic discharge device, and Each of the first electrostatic discharge devices is connected to only one data line, so that an electric charge is accumulated in a circuit connected to the data line connecting the first electrostatic discharge device in the display panel including the array substrate, and the accumulated electric charge enables the electric charge to be
  • the first electrostatic discharge device connected to the data line is turned on, the electric charge accumulated in the circuit connected to the data line can be discharged to the first lead through the first electrostatic discharge device, thereby preventing the accumulated electric charge from penetrating the circuit;
  • the data line can transmit a signal to the pixel connected thereto, which avoids the signal on the first lead
  • the pixels connected to the data lines cause interference, which ensures that the display panel including the array substrate can work normally.
  • At least one gate line is connected to the second lead on the array substrate by at least one second electrostatic discharge device, and each second electrostatic discharge device is connected to only one gate line, so that the A charge is accumulated in a circuit connected to a gate line connected to the second electrostatic discharge device in the display panel of the array substrate, and the accumulated charge can connect the gate line when the second electrostatic discharge device connected to the gate line is turned on
  • the charge accumulated in the circuit can be discharged to the second lead through the second electrostatic discharge device, thereby preventing the accumulated charge from penetrating the circuit; and, after the accumulated charge in the circuit connected to the gate line is released, the gate
  • the gate line can transmit a signal to the pixel connected thereto, which avoids the signal on the second lead to interfere with the pixel connected to the gate line, and the array is ensured
  • the display panel of the substrate can work normally.
  • At least one embodiment of the present invention provides an array substrate including a plurality of data lines, a plurality of gate lines, a first lead, and/or a second lead.
  • the at least one data line is connected to the first lead on the array substrate by at least one first electrostatic discharge device, and each of the first electrostatic discharge devices is connected to only one data line.
  • at least one gate line is connected to the second lead on the array substrate by at least one second electrostatic discharge device, and each second electrostatic discharge device is connected to only one gate line.
  • the first electrostatic discharge device is configured to be turned on when the voltage of the signal on the connected data line is greater than the first threshold, and the voltage of the signal on the connected data line is not When the value is greater than the second threshold, the voltage of the signal on the first lead is not greater than the second threshold.
  • the second electrostatic discharge device is configured to be turned on when the voltage of the signal on the connected gate line is greater than the third threshold. And turning off when the voltage of the signal on the connected gate line is not greater than the fourth threshold, and the voltage of the signal on the second lead is not greater than the fourth threshold.
  • the first threshold is related to the structure of the first electrostatic discharge device, and when the first electrostatic discharge device uses two thin film transistors, the first threshold is about several hundred volts to several kilovolts.
  • the second threshold is determined by the characteristics of the thin film transistor in the first electrostatic discharge device, about zero volts.
  • an electrostatic discharge device shown in Fig. 1 includes two thin film transistors TFT A and TFT B, and one end thereof is connected to the data line D or the gate line G, and the other end is connected to the short-circuit ring SR.
  • the working principle of the electrostatic discharge device is as follows: If the static electricity accumulation of the data line D or the gate line G needs to be released, the static electricity can be released to the SR by turning on the TFT A; on the contrary, the static electricity on the short-circuit ring SR can also be turned on by the TFT. B flows onto the data line D or the gate line G to disperse the charges as much as possible.
  • the first electrostatic discharge device uses two thin film transistors, if the voltage of the signal on the data line connected to the first electrostatic discharge device is greater than the first threshold, the first electrostatic discharge device is turned on, and the current is turned on. Very large, so that the static charge accumulated on the connected data line is quickly released, so that the voltage on the data line is equal to the voltage on the first lead, that is, not greater than the second threshold, and then the first electrostatic discharge device shut down.
  • the first electrostatic discharge device When the voltage on the data line connected to the first electrostatic discharge device is ten volts, the first electrostatic discharge device is also turned on, but the opening current is small, and the influence thereof can be ignored, so when the display panel including the array substrate works normally (For example, the voltage on the data line is about 10V, the voltage on the gate line is about 20V, and the voltage on the common electrode is about 5V), and the first electrostatic discharge device does not affect the normal operation of the display panel.
  • the third threshold is related to the structure of the second electrostatic discharge device, and when the second electrostatic discharge device uses two thin film transistors, the third threshold is about several hundred volts to several kilovolts.
  • the fourth threshold is determined by the characteristics of the thin film transistor in the second electrostatic discharge device, about zero volts.
  • the second electrostatic discharge device uses two thin film transistors, if the voltage of the signal on the data line connected to the second electrostatic discharge device is greater than the first threshold, the second electrostatic discharge device is turned on, and the opening current is large, so that The static charge accumulated on the connected gate line is quickly released, so that the voltage on the gate line is equal to the voltage on the second lead, that is, not greater than the fourth threshold, and then the second electrostatic discharge device is turned off.
  • the second electrostatic discharge device When the voltage on the gate line connected to the second electrostatic discharge device is ten volts, the second electrostatic discharge device is also turned on, but the turn-on current is small, and the influence can be ignored, so When the display panel including the array substrate is in normal operation (for example, the voltage on the data line is about 10V, the voltage on the gate line is about 20V, and the voltage on the common electrode is about 5V), the second electrostatic discharge device does not Affect the normal operation of the display panel.
  • the array substrate 11 shown in Fig. 2a includes a plurality of data lines D (longitudinal leads in the display area 12) and a plurality of gate lines G (horizontal leads in the display area 12).
  • the two data lines are respectively connected to the first lead L1 on the array substrate 11 through the corresponding first electrostatic discharge device ESDI, and each of the first electrostatic discharge devices ESDI is connected to only one data line.
  • Each of the data lines of the strip data lines is connected to the first lead L1 on the array substrate 11 through two first electrostatic discharge devices ESDI disposed at both ends thereof.
  • the first lead L1 may be located in the display area 12 or outside the display area 12, for example, the first lead L1 is located outside the display area 12.
  • the array substrate further includes source drive integrated circuits SIC1 and SIC2 connected to the data lines, and gate drive integrated circuits GIC1 and GIC2 connected to the gate lines.
  • the source driver integrated circuits SIC1 and SIC2 and the gate drive integrated circuits GIC1 and GIC2 may be located on the array substrate or on a flexible circuit board connected to the array substrate.
  • the source driving integrated circuits SIC1 and SIC2 and the gate driving integrated circuits GIC1 and GIC2 are located on the array substrate as an example.
  • the first lead L1 on the array substrate 11 may be provided in one piece or in a plurality of lines.
  • the first electrostatic discharge device connected to the data line When the static charge accumulated in the integrated circuit connected to the data line connected to the first electrostatic discharge device causes the voltage on the data line to be greater than the first threshold, the first electrostatic discharge device connected to the data line is turned on, so that The static charge accumulated in the integrated circuit connected to the data line can be discharged to the first lead L1 through the first electrostatic discharge device connected to the data line, which prevents the accumulated static charge from penetrating the integrated circuit connected to the data line. After the static charge is released, when the voltage on the data line is not greater than the second threshold, the first electrostatic discharge device connected to the data line is turned off, so that the signal on the data line is not received by the first lead L1.
  • the array substrate 11 shown in Fig. 2b includes a plurality of data lines D (longitudinal leads in the display region 12) and a plurality of gate lines G (leaves in the lateral direction of the display region 12).
  • three The gate lines are respectively connected to the second leads L2 on the array substrate 11 through the corresponding second electrostatic discharge devices ESD2, and each second electrostatic discharge device ESD2 is connected to only one gate line, one of the three gate lines
  • the second lead L2 on the array substrate 11 is connected through a second electrostatic discharge device ESD2, and each of the other two of the three gate lines passes through two second portions disposed at both ends thereof
  • the electrostatic discharge device is connected to the second lead L2 on the array substrate 11.
  • the second lead L2 may be located in the display area 12 or outside the display area 12, for example, the second lead L2 is located outside the display area 12.
  • the array substrate further includes source drive integrated circuits SIC1 and SIC2 connected to the data lines, and gate drive integrated circuits GIC1 and GIC2 connected to the gate lines.
  • the source driver integrated circuits SIC1 and SIC2 and the gate drive integrated circuits GIC1 and GIC2 may be located on the array substrate or on a flexible circuit board connected to the array substrate.
  • the second lead L2 on the array substrate 11 may be provided in one piece or in a plurality of lines.
  • the second electrostatic discharge device connected to the gate line is turned on, Causing static charge accumulated in the integrated circuit connected to the gate line to be discharged to the second lead L2 through the second electrostatic discharge device connected to the gate line, which avoids accumulated static charge breakdown and the gate Wire-connected integrated circuits.
  • the second electrostatic discharge device connected to the gate line is turned off, so that the signal on the gate line is not subjected to the second The interference of the signal on the lead L2, which is capable of transmitting the signal output by the gate drive integrated circuit to the pixel (not shown in Figure 2b).
  • each of the data lines on the array substrate is coupled to the first lead on the array substrate by at least one first electrostatic discharge device.
  • each of the gate lines on the array substrate is connected to the second leads on the array substrate by at least one second electrostatic discharge device.
  • each data line on the array substrate 11 passes through a first electrostatic discharge device.
  • the ESDI is connected to the first lead L1 on the array substrate 11; each of the gate lines on the array substrate 11 is connected to the second lead L2 on the array substrate 11 via a second electrostatic discharge device ESD2.
  • the array substrate provided by at least one embodiment of the present invention may further include at least one first shorting ring and a third electrostatic discharge device, for example, on the array substrate, and the first shorting ring releases the first electrostatic discharge device and the third electrostatic discharge
  • the devices are connected in series.
  • each first shorting ring At least one first electrostatic discharge device is connected, and each of the first short circuit rings is connected to a first lead on the array substrate by a third electrostatic discharge device.
  • the third electrostatic discharge device is configured to be turned on when the voltage of the signal on the first shorting ring connected thereto is greater than the fifth threshold, and is off when the voltage of the signal on the first shorting ring connected thereto is not greater than the sixth threshold The voltage of the signal on the first lead is not greater than the sixth threshold.
  • the first shorting ring may also be connected to the second lead or simultaneously connected to the first lead and the second lead, which are not limited herein.
  • the fifth threshold is related to the structure of the third electrostatic discharge device.
  • the third electrostatic discharge device uses two thin film transistors, the fifth threshold is about several hundred volts to several kilovolts.
  • the sixth threshold is determined by the characteristics of the thin film transistor in the third electrostatic discharge device, about zero volts.
  • the third electrostatic discharge device uses two thin film transistors, if the voltage of the signal on the first short circuit ring connected to the third electrostatic discharge device is greater than the fifth threshold, the third electrostatic discharge device is turned on, and the opening current is large. So that the static charge on the first shorting ring connected thereto is quickly released, so that the voltage on the first shorting ring is equal to the voltage on the first lead, that is, not greater than the sixth threshold, and the third electrostatic discharge device shut down.
  • the array substrate 11 shown in FIG. 4a includes a plurality of data lines D (longitudinal leads in the display area 12), a plurality of gate lines G (horizontal leads in the display area 12), and two on the array substrate 11.
  • the six data lines are connected to the first shorting ring SR1 on the array substrate 11 through the corresponding first electrostatic discharge device ESDI, and each of the first electrostatic discharge devices ESDI is connected to only one data line; there are four data lines.
  • Each of the wires is respectively connected to a first electrostatic discharge device ESDI, and two data lines are respectively connected to two first electrostatic discharge devices ESDI disposed at two ends thereof; each of the first short circuit rings SR1 passes through two third electrostatic discharge devices ESD3
  • the first lead L1 is connected.
  • the first shorting ring SR1 may be located in the display area 12 or outside the display area 12, for example, the first shorting ring SR1 is located outside the display area 12; the first lead L1 may be located in the display area 12, It may be located outside the display area 12, for example, the first lead L1 is located outside the display area 12.
  • the 4a further includes source driver integrated circuits SIC1 and SIC2 connected to the data lines, and gate drive integrated circuits GIC1 and GIC2 connected to the gate lines.
  • the source driver integrated circuits SIC1 and SIC2 and the gate drive integrated circuits GIC1 and GIC2 may be located on the array substrate or on a flexible circuit board connected to the array substrate.
  • the first lead L1 on the array substrate 11 may be provided in one piece or in a plurality of lines.
  • First short circuit on the array substrate The ring SRI can be set one or more. It should be noted that in at least one embodiment, the first shorting ring SR1 may also be connected to the gate line through an electrostatic discharge device.
  • the third electrostatic discharge device connected to the first shorting ring When the voltage of the signal on the first shorting ring is greater than the fifth threshold, the third electrostatic discharge device connected to the first shorting ring is turned on, so that the static charge on the first shorting ring can pass through the first shorting ring The connected third electrostatic discharge device is released onto the first lead L1. After the static charge is released, when the voltage of the signal on the first shorting ring is not greater than the sixth threshold, the third electrostatic discharge device connected to the first shorting ring is turned off, so that the first connecting the first shorting ring is connected.
  • the signals on the data line connected to the electrostatic discharge device are not interfered by the signals on the first lead L1, and the data lines can transmit the signals output from the source drive integrated circuit to the pixels without interference (not shown in FIG. 4a). Shown).
  • At least one embodiment of the present invention may provide ⁇ first shorting rings in the array substrate,
  • Each first shorting ring is connected to ⁇ + first electrostatic discharge devices; one first shorting ring
  • Each of the other first shorting rings in the middle is connected to the first first electrostatic discharge device; mod represents a remainder function, and K is less than or equal to M.
  • three first shorting rings, seven first electrostatic discharge devices, and one of the three first shorting rings are connected to three first electrostatic discharge devices, and three first short circuit rings are disposed on the array substrate.
  • Each of the other two first shorting rings in the middle connects the two first electrostatic discharge devices.
  • a first shorting ring connects the first electrostatic discharge device and the third electrostatic discharge device in series, that is, to discharge a static charge accumulated on a data line and its connected source driving integrated circuit, the first static electricity is required to be discharged
  • the release device and the third electrostatic discharge device can improve the reliability of the circuit and avoid signal crosstalk when the first electrostatic discharge device or the third electrostatic discharge device is short-circuited.
  • K first short-circuit rings that is, K strips of electrostatic discharge paths, can alleviate the pressure of electrostatic discharge and improve the efficiency of electrostatic discharge.
  • the array substrate provided by at least one embodiment of the present invention may further include at least one, for example, located A second shorting ring on the array substrate, each of the second shorting rings is connected to at least one second electrostatic discharge device, and each of the second shorting rings is connected to the second lead on the array substrate by a fourth electrostatic discharge device.
  • a fourth electrostatic discharge device configured to be turned on when a voltage of a signal on the second short-circuit ring connected thereto is greater than a seventh threshold, and when a voltage of a signal on the second short-circuit ring connected thereto is not greater than an eighth threshold Turned off, the voltage of the signal on the second lead is not greater than the eighth threshold.
  • the first shorting ring may also be connected to the second lead or simultaneously connected to the first lead and the second lead, which are not limited herein.
  • the seventh threshold is related to the structure of the fourth electrostatic discharge device, and when the fourth electrostatic discharge device uses two thin film transistors, the seventh threshold is about several hundred volts to several kilovolts.
  • the eighth threshold is determined by the characteristics of the thin film transistor in the fourth electrostatic discharge device, which is about zero volts.
  • the fourth electrostatic discharge device uses two thin film transistors, if the voltage of the signal on the second short circuit ring connected to the fourth electrostatic discharge device is greater than the seventh threshold, the fourth electrostatic discharge device is turned on, and the opening current is large. Therefore, the static charge accumulated on the second short-circuit ring connected thereto is quickly released, so that the voltage on the second short-circuit ring is equal to the voltage on the second lead, that is, not greater than the eighth threshold, and the fourth electrostatic discharge The device is turned off.
  • the array substrate 11 shown in FIG. 4b includes a plurality of data lines D (longitudinal leads in the display area 12), a plurality of gate lines G (horizontal leads in the display area 12), and two on the array substrate 11.
  • the second shorting ring SR2, and one second shorting ring connects the second electrostatic discharge device and the fourth electrostatic discharge device in series.
  • the four gate lines are connected to the second short-circuit ring SR2 on the array substrate 11 through the second electrostatic discharge device ESD2, and each of the second electrostatic discharge devices ESD2 is connected to only one gate line.
  • two gate lines are respectively connected to a second electrostatic discharge device ESD2, and two gate lines are respectively connected to two second electrostatic discharge devices ESD2; each second short-circuit ring SR2 passes through two The fourth electrostatic discharge device ESD4 is connected to the second lead L2.
  • the second shorting ring SR2 may be located in the display area 12 or outside the display area 12, for example, the second shorting ring SR2 is located outside the display area 12; the second lead L2 may be located in the display area 12, It may be located outside the display area 12, for example, the second lead L2 is located outside the display area 12.
  • Source driver integrated circuits SIC1 and SIC2 connected to the data lines, and gate drive integrated circuits GIC1 and GIC2 connected to the gate lines.
  • Source driver integrated circuits SIC1 and SIC2 and gate drive integrated circuits GIC1 and GIC2 are available On the array substrate, it may also be located on a flexible circuit board connected to the array substrate.
  • the second lead L2 on the array substrate 11 may be provided in one piece or in a plurality of lines.
  • the second shorting ring SR2 on the array substrate may be provided in one piece or in multiple pieces. It should be noted that in at least one embodiment, the second shorting ring SR2 can also be connected to the data line through an electrostatic discharge device.
  • the fourth electrostatic discharge device connected to the second shorting ring When the voltage of the signal on the second shorting ring is greater than the seventh threshold, the fourth electrostatic discharge device connected to the second shorting ring is opened, so that the static charge on the second shorting ring can pass through the second shorting ring The connected fourth electrostatic discharge device is released onto the second lead L2. After the static charge is released, when the voltage of the signal on the second shorting ring is not greater than the eighth threshold, the fourth electrostatic discharge device connected to the second shorting ring is turned off, so that the second connecting ring is connected. The signal on the gate line connected to the second electrostatic discharge device is not interfered by the signal on the second lead L2, and the gate line can transmit the signal outputted by the gate drive integrated circuit to the pixel without interference (Fig.
  • At least one embodiment of the present invention may provide L second shorting rings on the array substrate,
  • Two second shorting rings are connected to I + second electrostatic discharge devices; L second shorting rings
  • Each of the other second shorting rings is connected to the L second electrostatic discharge devices, mod represents a remainder function, and L is less than or equal to N.
  • each of the three second shorting rings of the four second shorting rings is connected to two second electrostatic discharges.
  • Device there are four second shorting rings and seven second electrostatic discharge devices, and each of the three second shorting rings of the four second shorting rings is connected to two second electrostatic discharges.
  • Another second shorting ring of the four second shorting rings is connected to one second electrostatic discharge device.
  • a second shorting ring connects the second electrostatic discharge device and the fourth electrostatic discharge device in series, that is, a static charge accumulated on a gate line and its connected gate driving integrated circuit is required to pass through a second
  • the electrostatic discharge device and the fourth electrostatic discharge device improve the reliability of the circuit and avoid signal crosstalk when the second electrostatic discharge device or the fourth electrostatic discharge device is short-circuited.
  • L second shorting rings that is, L strips of electrostatic discharge
  • the first lead L1 and the second lead L2 in the drawing are merely illustrative, but the embodiment of the present invention is not limited thereto, for example, the positions of the first lead and the second lead may be interchanged. Or the first lead and the second lead are the same lead.
  • the first lead on the array substrate and/or the second lead on the array substrate can be a common electrode line. Of course, there are other settings, which are not limited here.
  • the array substrate 11 includes a plurality of data lines D (longitudinal leads in the display area 12), a plurality of gate lines G (horizontal leads in the display area 12), a common electrode line Vcom on the array substrate 11, and four first The short circuit ring SR1 and the two second short circuit rings SR2; each of the data lines is connected to the first short circuit ring SR1 on the array substrate 11 through two first electrostatic discharge devices ESDI, and each first electrostatic discharge device ESDI is connected to only one data.
  • each of the gate lines is connected to the second on the array substrate 11 through two second electrostatic discharge devices ESD2 Short circuit ring SR2, each second electrostatic discharge device ESD2 is connected to only one gate line; each first short circuit ring SR1 is connected to the common electrode line Vcom (ie, the first lead and the second lead) through two third electrostatic discharge devices ESD3 Each of the second shorting rings SR2 is connected to the common electrode line Vcom (ie, the first lead and the second lead) through the two fourth electrostatic discharge devices ESD4.
  • Vcom common electrode line
  • FIG. 5 further includes source driving integrated circuits SIC1 and SIC2 connected to the data lines. , gate drive integrated circuits GIC1 and GIC2 connected to the gate lines.
  • the array substrate of the above embodiment can be used for an organic light emitting diode panel, a thin film transistor liquid crystal display panel, or the like, which is not limited herein.
  • the first and second leads, as well as the first and second shorting rings may have other arrangements as long as they are capable of providing an electrostatic discharge path.
  • the embodiment of the invention further provides a display panel comprising the above array substrate.
  • the embodiment of the invention further provides a display device comprising the above display panel.
  • the display device can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. Any product or component with display function.
  • the spirit and scope of the invention Thus, if such modifications and variations of the present invention are claimed in the present invention The invention is also intended to cover such modifications and variations within the scope of the invention.
  • the present application claims the priority of the Chinese Patent Application No. 201310745801.6 filed on Dec. 30, 2013, the entire disclosure of which is hereby incorporated by reference.

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Abstract

一种阵列基板、显示面板和显示装置，该阵列基板(11)包括：多条数据线(D)、多条栅极线(G)、第一引线(L1)和/或第二引线(L2)。当所述阵列基板包括第一引线(L1)时，至少一条数据线(D)通过至少一个第一静电释放装置(ESD1)连接所述阵列基板(11)上的第一引线(L1)，每个第一静电释放装置(ESD1)仅连接一条数据线(D)；当所述阵列基板包括第二引线(L2)时，至少一条栅极线(G)通过至少一个第二静电释放装置(ESD2)连接所述阵列基板(11)上的第二引线(L2)，每个第二静电释放装置(ESD2)仅连接一条栅极线(G)。该阵列基板(11)能够避免显示面板在受到挤压或者摩擦时因电路中电荷的大量积累造成的电路击穿和损伤。

Description

阵列基板、 显示面板和显示装置 技术领域
本发明实施例涉及一种阵列基板、 显示面板和显示装置。 背景技术
显示装置可以釆用多种不同的显示面板，例如，有机发光二极管（ OLED， Organic Light-Emitting Diode )面板， 薄膜晶体管液晶显示（TFT-LCD, Thin Film Transistor Liquid Crystal Display )面板。 下面以 TFT-LCD为例说明显示 面板中的组成部分阵列基板。
TFT-LCD通常是由阵列基板和彩膜基板 ( color filter substrate )对盒而形 成的。 在阵列基板中， 栅极线和数据线通过相互交叉限定了像素区域， 在各 像素区域中配置有像素电极和薄膜晶体管。 在彩膜基板上配置有黑矩阵和对 应于各像素区域的滤色层。 阵列基板上配置有公共电极线。 在阵列基板和彩 膜基板二者之间充入液晶。 通过加载栅极驱动信号和数据信号（像素电极的 电压）来形成电场， 该电场控制液晶的偏转从而控制光线的强弱， 再配合彩 膜基板的滤色功能， 显示面板就能显示出所要表达的图像。 发明内容
本发明实施例提供了一种阵列基板、 显示面板和显示装置， 用以避免显 示面板在受到挤压或者摩擦时因电路中电荷的大量积累造成的电路击穿和损 伤。
本发明实施例提供的一种阵列基板， 包括多条数据线、 多条栅极线、 第 一引线和 /或第二引线。 当所述阵列基板包括第一引线时， 至少一条数据线通 过至少一个第一静电释放装置连接所述第一引线， 每个第一静电释放装置仅 连接一条数据线； 所述第一静电释放装置用于在其连接的数据线上的信号的 电压大于第一阔值时开启， 并在其连接的数据线上的信号的电压不大于第二 阔值时关断， 所述第一引线上的信号的电压不大于第二阔值。 当所述阵列基 板包括第二引线时， 至少一条栅极线通过至少一个第二静电释放装置连接所 述第二引线， 每个第二静电释放装置仅连接一条栅极线； 所述第二静电释放 装置用于在其连接的栅极线上的信号的电压大于第三阔值时开启， 并在其连 接的栅极线上的信号的电压不大于第四阔值时关断， 所述第二引线上的信号 的电压不大于第四阔值。
本发明实施例还提供一种显示面板，包括本发明实施例提供的阵列基板。 本发明实施例提供的一种显示装置，包括本发明实施例提供的显示面板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为一种静电释放装置的结构示意图；
图 2a为本发明实施例提供的阵列基板之一的结构示意图；
图 2b为本发明实施例提供的阵列基板之二的结构示意图；
图 3为本发明实施例提供的阵列基板之三的结构示意图；
图 4a为本发明实施例提供的阵列基板之四的结构示意图；
图 4b为本发明实施例提供的阵列基板之五的结构示意图；
图 5为本发明实施例提供的阵列基板之六的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本申请的发明人注意到， 显示面板在制作和运输过程中， 由于受到挤压 或者摩擦的作用， 很容易在显示面板的电路中积累大量的电荷， 这些静电荷 很可能会击穿显示面板中的电路， 从而对显示面板中的电路造成损伤。
本发明至少一个实施例提供了一种阵列基板， 在该阵列基板中， 至少一 条数据线通过至少一个第一静电释放装置连接该阵列基板上的第一引线， 且 每个第一静电释放装置仅连接一条数据线， 这样能够使得包括该阵列基板的 显示面板中的与连接第一静电释放装置的数据线相连的电路中积累了电荷， 且积累的电荷能够使该数据线连接的第一静电释放装置开启时， 连接该数据 线的电路中积累的电荷能够通过第一静电释放装置释放到第一引线上， 从而 避免了积累的电荷击穿该电路； 并且， 在该数据线连接的电路中积累的电荷 释放后， 该数据线连接的第一静电释放装置关断时， 该数据线能够向与其连 接的像素传输信号， 这避免了第一引线上的信号对该数据线连接的像素造成 干扰， 保证了包括该阵列基板的显示面板能够正常工作。
在该阵列基板中， 至少一条栅极线通过至少一个第二静电释放装置连接 该阵列基板上的第二引线， 且每个第二静电释放装置仅连接一条栅极线， 这 样能够得使包括该阵列基板的显示面板中与连接第二静电释放装置的栅极线 相连的电路中积累了电荷， 且积累的电荷能够使连接该栅极线的第二静电释 放装置开启时， 连接该栅极线的电路中积累的电荷能够通过第二静电释放装 置释放到第二引线上， 从而避免积累的电荷击穿该电路； 并且， 在该栅极线 连接的电路中积累的电荷释放后，该栅极线连接的第二静电释放装置关断时， 该栅极线能够向与其连接的像素传输信号， 这避免了第二引线上的信号对该 栅极线连接的像素造成干扰， 保证了包括该阵列基板的显示面板能够正常工 作。
下面结合说明书附图， 对本发明至少一个实施例提供的一种阵列基板、 显示面板和显示装置进行说明。
本发明的至少一个实施例提供的一种阵列基板， 包括多条数据线、 多条 栅极线、 第一引线和 /或第二引线。 在本发明的至少一个实施例中， 至少一条 数据线通过至少一个第一静电释放装置连接该阵列基板上的第一引线， 每个 第一静电释放装置仅连接一条数据线。 在本发明的至少一个实施例中， 至少 一条栅极线通过至少一个第二静电释放装置连接该阵列基板上的第二引线， 每个第二静电释放装置仅连接一条栅极线。 在本发明的至少一个实施例中， 第一静电释放装置， 用于在其连接的数据线上的信号的电压大于第一阔值时 开启， 并在其连接的数据线上的信号的电压不大于第二阔值时关断， 第一引 线上的信号的电压不大于第二阔值。 在本发明的至少一个实施例中， 第二静 电释放装置， 用于在其连接的栅极线上的信号的电压大于第三阔值时开启， 并在其连接的栅极线上的信号的电压不大于第四阔值时关断， 第二引线上的 信号的电压不大于第四阔值。
在一个示例中， 第一阔值与第一静电释放装置的结构有关， 当第一静电 释放装置釆用两个薄膜晶体管时， 第一阔值约为几百伏至几千伏。
在一个示例中， 第二阔值由第一静电释放装置中的薄膜晶体管的特性决 定， 大约在零伏左右。
例如， 图 1所示的一种静电释放装置， 包括两个薄膜晶体管 TFT A和 TFT B , 并且其一端连接数据线 D或栅极线 G， 另一端连接短路环 SR。 该静 电释放装置的工作原理为： 如果数据线 D或栅极线 G的静电积累需要释放， 则可以通过开启 TFT A将静电释放到 SR上； 反之， 短路环 SR上的静电也 可以通过开启 TFT B流通到数据线 D或栅极线 G上， 使电荷尽可能地分散。 由此可知， 当第一静电释放装置釆用两个薄膜晶体管时， 若第一静电释放装 置连接的数据线上的信号的电压大于第一阔值， 则第一静电释放装置开启， 并且开启电流很大， 这样其连接的数据线上积累的静电荷会迅速被释放掉， 使得该数据线上的电压与第一引线上的电压相等， 即不大于第二阔值， 然后 第一静电释放装置关闭。 在第一静电释放装置连接的数据线上的电压为十几 伏时， 第一静电释放装置也会开启， 但是开启电流很小， 可以忽略其影响， 所以当包括该阵列基板的显示面板正常工作时 (例如，数据线上的电压为 10V 左右， 栅极线上的电压为 20V左右， 公共电极上的电压为 5V左右）， 第一静 电释放装置是不会影响该显示面板正常工作的。
在一个示例中， 第三阔值与第二静电释放装置的结构有关， 当第二静电 释放装置釆用两个薄膜晶体管时， 第三阔值约为几百伏至几千伏。
在一个示例中， 第四阔值由第二静电释放装置中的薄膜晶体管的特性决 定， 大约在零伏左右。
当第二静电释放装置釆用两个薄膜晶体管时， 若第二静电释放装置连接 的数据线上的信号的电压大于第一阔值， 则第二静电释放装置开启， 并且开 启电流很大， 这样其连接的栅极线上积累的静电荷会迅速被释放掉， 使得该 栅极线上的电压与第二引线上的电压相等， 即不大于第四阔值， 然后第二静 电释放装置关闭。 在第二静电释放装置连接的栅极线上的电压为十几伏时， 第二静电释放装置也会开启， 但是开启电流很小， 可以忽略其影响， 所以当 包括该阵列基板的显示面板正常工作时 (例如， 数据线上的电压为 10V左右， 栅极线上的电压为 20V左右， 公共电极上的电压为 5V左右）， 第二静电释放 装置是不会影响该显示面板正常工作的。
图 2a所示的阵列基板 11包括多条数据线 D (显示区 12中纵向的引线） 和多条栅极线 G (显示区 12中横向的引线） 。 在图 2a所示的情形中， 两条 数据线分别通过相应的第一静电释放装置 ESDI连接阵列基板 11上的第一引 线 Ll， 每个第一静电释放装置 ESDI仅连接一条数据线， 这两条数据线中的 每一条数据线均通过设置在其两端的两个第一静电释放装置 ESDI连接阵列 基板 11上的第一引线 Ll。 在不同的示例中， 第一引线 L1可以位于显示区 12中， 也可以位于显示区 12以外， 例如， 第一引线 L1位于显示区 12以外。 在一个示例中，如图 2a所示， 阵列基板还包括与数据线相连的源极驱动集成 电路 SIC1和 SIC2， 与栅极线相连的栅极驱动集成电路 GIC1和 GIC2。 源极 驱动集成电路 SIC1和 SIC2以及栅极驱动集成电路 GIC1和 GIC2可以位于 阵列基板上， 也可以位于与阵列基板相连的柔性电路板上。 在本发明实施例 中以源极驱动集成电路 SIC1和 SIC2以及栅极驱动集成电路 GIC1和 GIC2 位于阵列基板上为例进行说明。阵列基板 11上的第一引线 L1可以设置一条， 也可以设置多条。
当与连接第一静电释放装置的数据线相连的集成电路中积累的静电荷使 得该数据线上的电压大于第一阔值时， 与该数据线相连的第一静电释放装置 开启， 使得与该数据线相连的集成电路中积累的静电荷能够通过与该数据线 相连的第一静电释放装置释放到第一引线 L1 上， 这避免了积累的静电荷击 穿与该数据线相连的集成电路。 而在静电荷释放后， 该数据线上的电压不大 于第二阔值时， 与该数据线相连的第一静电释放装置关断， 使得该数据线上 的信号不会受到第一引线 L1 上的信号的干扰， 从而该数据线能够将源极驱 动集成电路输出的信号传输到像素 (图 2a中未示出 )上。 需要注意的是， 本 实施例及以下实施例中仅是以集成电路为例进行说明， 但可通过本发明实施 例释放的阵列基板中的静电荷并不局限于此， 例如阵列基板电路中产生的静 电荷也可以通过本发明实施例释放出去。
图 2b所示的阵列基板 11包括多条数据线 D (显示区 12中纵向的引线） 和多条栅极线 G (显示区 12中横向的引线） 。 在图 2b所示的情形中， 三条 栅极线分别通过相应的第二静电释放装置 ESD2连接阵列基板 11上的第二引 线 L2， 每个第二静电释放装置 ESD2仅连接一条栅极线， 这三条栅极线中的 一条栅极线通过一个第二静电释放装置 ESD2连接阵列基板 11上的第二引线 L2, 这三条栅极线中的另外两条栅极线中的每一条栅极线均通过设置在其两 端的两个第二静电释放装置连接阵列基板 11上的第二引线 L2。 在不同的示 例中， 第二引线 L2可以位于显示区 12中， 也可以位于显示区 12以外， 例 如， 第二引线 L2位于显示区 12以外。 在一个示例中， 如图 2b所示， 阵列 基板还包括与数据线相连的源极驱动集成电路 SIC1和 SIC2， 与栅极线相连 的栅极驱动集成电路 GIC1和 GIC2。源极驱动集成电路 SIC1和 SIC2以及栅 极驱动集成电路 GIC1和 GIC2可以位于阵列基板上，也可以位于与阵列基板 相连的柔性电路板上。 阵列基板 11上的第二引线 L2可以设置一条， 也可以 设置多条。
当与连接第二静电释放装置的栅极线相连的集成电路中积累的静电荷使 得该栅极线上的电压大于第三阔值时， 与该栅极线相连的第二静电释放装置 开启， 使得与该栅极线相连的集成电路中积累的静电荷能够通过与该栅极线 相连的第二静电释放装置释放到第二引线 L2上， 这避免了积累的静电荷击 穿与该栅极线相连的集成电路。 而在静电荷释放后， 该栅极线上的电压不大 于第四阔值时， 与该栅极线相连的第二静电释放装置关断， 使得该栅极线上 的信号不会受到第二引线 L2上的信号的干扰， 该栅极线能够将栅极驱动集 成电路输出的信号传输到像素 （图 2b中未示出）上。
在一个示例中， 阵列基板上的每一条数据线均通过至少一个第一静电释 放装置连接该阵列基板上的第一引线。
在一个示例中， 阵列基板上的每一条栅极线均通过至少一个第二静电释 放装置连接该阵列基板上的第二引线。
如图 3所示， 阵列基板 11上每一条数据线通过一个第一静电释放装置
ESDI连接阵列基板 11上的第一引线 L1 ; 阵列基板 11上每一条栅极线通过 一个第二静电释放装置 ESD2连接阵列基板 11上的第二引线 L2。
本发明的至少一个实施例提供的阵列基板还可以包括至少一个例如位于 该阵列基板上的第一短路环和第三静电释放装置， 并且第一短路环将第一静 电释放装置和第三静电释放装置串联起来。 在一个示例中， 每个第一短路环 连接至少一个第一静电释放装置， 每个第一短路环通过一个第三静电释放装 置连接例如位于该阵列基板上的第一引线。 第三静电释放装置用于在其连接 的第一短路环上的信号的电压大于第五阔值时开启， 并在其连接的第一短路 环上的信号的电压不大于第六阔值时关断， 第一引线上的信号的电压不大于 第六阔值。 需要注意的是， 在至少一个实施例中， 第一短路环还可以连接到 第二引线， 或者同时连接到第一引线和第二引线， 此处不做限定。
在一个示例中， 第五阔值与第三静电释放装置的结构有关， 当第三静电 释放装置釆用两个薄膜晶体管时， 第五阔值约为几百伏至几千伏。
在一个示例中， 第六阔值由第三静电释放装置中的薄膜晶体管的特性决 定， 大约在零伏左右。
当第三静电释放装置釆用两个薄膜晶体管时， 若第三静电释放装置连接 的第一短路环上的信号的电压大于第五阔值， 则第三静电释放装置开启， 并 且开启电流很大， 这样其连接的第一短路环上的静电荷会迅速被释放掉， 使 得该第一短路环上的电压与第一引线上的电压相等， 即不大于第六阔值， 第 三静电释放装置关闭。
如图 4a所示的阵列基板 11中包括多条数据线 D (显示区 12中纵向的引 线） 、 多条栅极线 G (显示区 12中横向的引线）和两条位于阵列基板 11上 的第一短路环 SR1。在图 4a所示的情形中，六条数据线通过相应的第一静电 释放装置 ESDI连接阵列基板 11上的第一短路环 SR1，每个第一静电释放装 置 ESDI仅连接一条数据线； 有四条数据线各自分别连接一个第一静电释放 装置 ESDI , 有两条数据线各自分别连接设置在其两端的两个第一静电释放 装置 ESDI ; 每条第一短路环 SR1通过两个第三静电释放装置 ESD3连接第 一引线 Ll。 在不同示例中， 第一短路环 SR1可以位于显示区 12中， 也可以 位于显示区 12以外， 例如， 第一短路环 SR1位于显示区 12以外； 第一引线 L1可以位于显示区 12中， 也可以位于显示区 12以外， 例如， 第一引线 L1 位于显示区 12以外。 在一个示例中， 图 4a还包括与数据线相连的源极驱动 集成电路 SIC1和 SIC2， 与栅极线相连的栅极驱动集成电路 GIC1和 GIC2。 源极驱动集成电路 SIC1和 SIC2以及栅极驱动集成电路 GIC1和 GIC2可以 位于阵列基板上， 也可以位于与阵列基板相连的柔性电路板上。 阵列基板 11 上的第一引线 L1 可以设置一条， 也可以设置多条。 阵列基板上的第一短路 环 SRI可以设置一条， 也可以设置多条。 需要注意的是， 在至少一个实施例 中， 第一短路环 SR1还可以通过静电释放装置与栅极线连接。
当第一短路环上的信号的电压大于第五阔值时， 与该第一短路环相连的 第三静电释放装置开启， 使得该第一短路环上的静电荷能够通过与该第一短 路环相连的第三静电释放装置释放到第一引线 L1 上。 而在静电荷释放后， 该第一短路环上的信号的电压不大于第六阔值时， 与该第一短路环相连的第 三静电释放装置关断， 使得连接该第一短路环的第一静电释放装置所连接的 数据线上的信号不会受到第一引线 L1 上的信号的干扰， 这些数据线能够不 受干扰地将源极驱动集成电路输出的信号传输到像素 (图 4a中未示出 )上。 釆用这种两级静电释放装置串联的结构， 可以更好地避免第一引线 L1 上的 信号对数据线上的信号的干扰。 当然， 也可以釆用更多级的静电释放装置串 联的结构， 在此不再赘述。
本发明的至少一个实施例提供的阵列基板中可以设置 κ个第一短路环，
M个第一静电释放装置， K个第一短路环中的 mod(M/K)个第一短路环中的
M - mod{M I K) | 1
每个第一短路环连接 Κ + 个第一静电释放装置； Κ个第一短路环
Μ - ναοά{Μ I Κ)
中的其它第一短路环中的每个第一短路环连接 Κ 个第一静电释 放装置； mod代表取余函数， K小于等于M。
例如， 阵列基板上设置了 3 个第一短路环， 7 个第一静电释放装置， 3 个第一短路环中的一个第一短路环连接 3个第一静电释放装置， 3个第一短 路环中的另外两个第一短路环中的每一个第一短路环连接 2个第一静电释放 装置。
一条第一短路环将第一静电释放装置和第三静电释放装置串联起来， 也 就是说，要将一条数据线及其连接的源极驱动集成电路上积累的静电荷释放， 需要经过第一静电释放装置和第三静电释放装置， 这样可以提高电路的可靠 性， 避免第一静电释放装置或第三静电释放装置短路时， 发生信号串扰。 另 夕卜， K个第一短路环即 K条静电释放的路径，这样可以緩解静电释放的压力， 提高静电释放的效率。
本发明的至少一个实施例提供的阵列基板还可以包括至少一个例如位于 该阵列基板上的第二短路环， 每个第二短路环连接至少一个第二静电释放装 置， 每个第二短路环通过一个第四静电释放装置连接该阵列基板上的第二引 线。 第四静电释放装置， 用于在其连接的第二短路环上的信号的电压大于第 七阔值时开启， 并在其连接的第二短路环上的信号的电压不大于第八阔值时 关断， 第二引线上的信号的电压不大于第八阔值。 需要注意的是， 在至少一 个实施例中， 第一短路环还可以连接到第二引线， 或者同时连接到第一引线 和第二引线， 此处不做限定。
在一个示例中， 第七阔值与第四静电释放装置的结构有关， 当第四静电 释放装置釆用两个薄膜晶体管时， 第七阔值约为几百伏至几千伏。
在一个示例中， 第八阔值由第四静电释放装置中的薄膜晶体管的特性决 定， 大约在零伏左右。
当第四静电释放装置釆用两个薄膜晶体管时， 若第四静电释放装置连接 的第二短路环上的信号的电压大于第七阔值， 则第四静电释放装置开启， 并 且开启电流很大，这样其连接的第二短路环上积累的静电荷会迅速被释放掉， 使得该第二短路环上的电压与第二引线上的电压相等， 即不大于第八阔值， 第四静电释放装置关闭。
如图 4b所示的阵列基板 11中包括多条数据线 D (显示区 12中纵向的引 线） 、 多条栅极线 G (显示区 12中横向的引线）和两条位于阵列基板 11上 的第二短路环 SR2， 并且一条第二短路环将第二静电释放装置和第四静电释 放装置串联起来。在图 4b所示的情形中，四条栅极线通过第二静电释放装置 ESD2连接阵列基板 11上的第二短路环 SR2， 每个第二静电释放装置 ESD2 仅连接一条栅极线。 在一个示例中， 有两条栅极线各自分别连接一个第二静 电释放装置 ESD2， 有两条栅极线各自分别连接两个第二静电释放装置 ESD2; 每条第二短路环 SR2通过两个第四静电释放装置 ESD4连接第二引 线 L2。 在不同示例中， 第二短路环 SR2可以位于显示区 12中， 也可以位于 显示区 12以外， 例如， 第二短路环 SR2位于显示区 12以外； 第二引线 L2 可以位于显示区 12中， 也可以位于显示区 12以外， 例如， 第二引线 L2位 于显示区 12以外。 在一个示例中， 图 4b还包括与数据线相连的源极驱动集 成电路 SIC1和 SIC2， 与栅极线相连的栅极驱动集成电路 GIC1和 GIC2。 源 极驱动集成电路 SIC1和 SIC2以及栅极驱动集成电路 GIC1和 GIC2可以位 于阵列基板上， 也可以位于与阵列基板相连的柔性电路板上。 阵列基板 11 上的第二引线 L2可以设置一条， 也可以设置多条。 阵列基板上的第二短路 环 SR2可以设置一条， 也可以设置多条。 需要注意的是， 在至少一个实施例 中， 第二短路环 SR2还可以通过静电释放装置与数据线连接。
当第二短路环上的信号的电压大于第七阔值时， 与该第二短路环相连的 第四静电释放装置开启， 使得该第二短路环上的静电荷能够通过与该第二短 路环相连的第四静电释放装置释放到第二引线 L2上。 而在静电荷释放后， 该第二短路环上的信号的电压不大于第八阔值时， 与该第二短路环相连的第 四静电释放装置关断， 使得连接该第二短路环的第二静电释放装置所连接的 栅极线上的信号不会受到第二引线 L2上的信号的干扰， 该栅极线能够不受 干扰地将栅极驱动集成电路输出的信号传输到像素（图 4b中未示出）上。 釆 用这种两级静电释放装置串联的结构， 可以更好地避免第二引线 L2上的信 号对栅极线上的信号的干扰。 当然， 也可以釆用更多级的静电释放装置串联 的结构。
本发明的至少一个实施例提供的阵列基板上可以设置 L个第二短路环，
N个第二静电释放装置， L个第二短路环中的 mod(N/L)个第二短路环中的每
N - mod(N/ L) | 1
个第二短路环连接 I + 个第二静电释放装置； L个第二短路环中
N - mod(N / L)
的其它第二短路环中的每个第二短路环连接 L 个第二静电释放装 置， mod代表取余函数， L小于等于N。
例如， 第二短路环为 4个， 第二静电释放装置为 7个， 则 4个第二短路 环中的 3个第二短路环中的每个第二短路环分别连接 2个第二静电释放装置，
4个第二短路环中的另外一个第二短路环连接 1个第二静电释放装置。
一条第二短路环将第二静电释放装置和第四静电释放装置串联起来， 也 就是说，要将一条栅极线及其连接的栅极驱动集成电路上积累的静电荷释放， 需要经过第二静电释放装置和第四静电释放装置， 从而提高电路的可靠性， 避免第二静电释放装置或第四静电释放装置短路时， 发生信号串扰。 另外，
L个第二短路环即 L条静电释放的路径， 这样可以緩解静电释放的压力， 提 高静电释放的效率。 需要注意的是， 附图中的第一引线 L1和第二引线 L2仅是示例性说明， 但本发明的实施例不局限于此，例如，第一引线和第二引线的位置可以互换， 或者第一引线与第二引线为同一引线。 在不同示例中， 阵列基板上的第一引 线和 /或该阵列基板上的第二引线可以为公共电极线。 当然， 还可以有其他设 置， 此处不做限定。
例如， 图 5所示的情形为第一引线和第二引线为同一引线， 且该引线为 公共电极线， 即第一引线和第二引线均为公共电极线。该阵列基板 11包括多 条数据线 D (显示区 12中纵向的引线） 、 多条栅极线 G (显示区 12中横向 的引线） 、 位于阵列基板 11 上的公共电极线 Vcom、 四条第一短路环 SR1 和两条第二短路环 SR2; 每条数据线分别通过两个第一静电释放装置 ESDI 连接阵列基板 11上的第一短路环 SR1，每个第一静电释放装置 ESDI仅连接 一条数据线， 相邻两条数据线分别通过第一静电释放装置 ESDI连接在不同 的第一短路环 SR1上； 每条栅极线分别通过两个第二静电释放装置 ESD2连 接阵列基板 11上的第二短路环 SR2，每个第二静电释放装置 ESD2仅连接一 条栅极线； 每条第一短路环 SR1通过两个第三静电释放装置 ESD3连接公共 电极线 Vcom (即第一引线和第二引线）， 每条第二短路环 SR2通过两个第 四静电释放装置 ESD4连接公共电极线 Vcom (即第一引线和第二引线） 。 在图 5的所示的情形中，四条第一短路环 SR1和两条第二短路环 SR2均位于 显示区 12以外； 此外， 图 5还包括与数据线相连的源极驱动集成电路 SIC1 和 SIC2， 与栅极线相连的栅极驱动集成电路 GIC1和 GIC2。
需要注意的是， 上述实施例的阵列基板可以用于有机发光二极管面板， 薄膜晶体管液晶显示面板等， 在此不做限定。 此外， 第一和二引线， 以及第 一和第二短路环也可以有其他设置方式， 只要这些设置方式能够起到提供静 电释放路径的作用即可。
本发明实施例还提供一种显示面板， 包括上述阵列基板。
本发明实施例还提供一种显示装置， 包括上述显示面板。 显示装置可以 为： 电子纸、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。 本申请要求于 2013年 12月 30日递交的中国专利申请第 201310745801.6 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种阵列基板， 包括多条数据线、 多条栅极线、 第一引线和 /或第二 引线， 其中，
当所述阵列基板包括第一引线时， 至少一条数据线通过至少一个第一静 电释放装置连接所述第一引线， 每个第一静电释放装置仅连接一条数据线， 所述第一静电释放装置用于在其连接的数据线上的信号的电压大于第一阔值 时开启， 并在其连接的数据线上的信号的电压不大于第二阔值时关断， 所述 第一引线上的信号的电压不大于所述第二阔值；
当所述阵列基板包括第二引线时， 至少一条栅极线通过至少一个第二静 电释放装置连接所述第二引线， 每个所述第二静电释放装置仅连接一条栅极 线， 所述第二静电释放装置用于在其连接的栅极线上的信号的电压大于第三 阔值时开启， 并在其连接的栅极线上的信号的电压不大于第四阔值时关断， 所述第二引线上的信号的电压不大于所述第四阔值。
2、如权利要求 1所述的阵列基板， 其中，每一条数据线通过至少一个第 一静电释放装置连接所述第一引线。
3、如权利要求 1或 2所述的阵列基板， 其中，每一条栅极线通过至少一 个第二静电释放装置连接所述第二引线。
4、如权利要求 1-3任一所述的阵列基板，还包括第三静电释放装置和至 少一个第一短路环， 其中，
每个第一短路环连接至少一个第一静电释放装置， 每个第一短路环通过 至少一个第三静电释放装置连接所述第一引线和 /或所述第二引线； 并且 所述第三静电释放装置， 用于在其连接的第一短路环上的信号的电压大 于第五阔值时开启， 并在其连接的第一短路环上的信号的电压不大于第六阔 值时关断，所述第一引线和 /或所述第二引线上的信号的电压不大于所述第六 阔值。
5、 如权利要求 4所述的阵列基板， 其中， 第一短路环有 K个， 第一静 电释放装置有 M个， K个第一短路环中的 mod(M/K)个第一短路环中的每个
M - mod(M / K) + 1
第一短路环连接 K + 个第一静电释放装置，其它第一短路环中的 M - mod(M / K)
每个第一短路环连接 Κ 个第一静电释放装置， 所述 mod代表取 余函数， K小于等于M。
6、如权利要求 1-5任一所述的阵列基板，还包括第四静电释放装置和至 少一个第二短路环， 其中，
每个第二短路环连接至少一个第二静电释放装置， 每个第二短路环通过 至少一个第四静电释放装置连接所述第一引线和 /或所述第二引线； 并且 所述第四静电释放装置用于在其连接的第二短路环上的信号的电压大于 第七阔值时开启， 并在其连接的第二短路环上的信号的电压不大于第八阔值 时关断，所述第一引线和 /或所述第二引线上的信号的电压不大于所述第八阔 值。
7、 如权利要求 6所述的阵列基板， 其中， 第二短路环有 L个， 第二静 电释放装置有 N个， L个第二短路环中的 mod(N/L)个第二短路环中的每个第
N - mod(N / L) | 1
二短路环连接 L + 个第二静电释放装置， 其它第二短路环中的每
N - mod(N / L)
个第二短路环连接 I 个第二静电释放装置， 所述 mod代表取余函 数， L小于等于
8、 如权利要求 1-7任一所述的阵列基板， 其中， 所述第一引线和 /或所 述第二引线为公共电极线。
9、 如权利要求 6-8任一所述的阵列基板， 其中， 所述第一引线、 第二引 线、 第一短路环以及第二短路环中的任意一个或几个的组合位于显示区中； 和 /或
所述第一引线、 第二引线、 第一短路环以及第二短路环中的任意一个或 几个的组合位于显示区以外。
10、 如权利要求 1-9任一所述的阵列基板， 其中，
所述第一引线设置为一条或多条； 和 /或
所述第二引线设置为一条或多条。
11、 如权利要求 1-10任一所述的阵列基板， 还包括与数据线相连的源极 驱动集成电路和与栅极线相连的栅极驱动集成电路， 其中， 所述源极驱动集成电路位于阵列基板上或位于与阵列基板相连的柔性电 路板上； 和 /或
所述栅极驱动集成电路位于阵列基板上或位于与阵列基板相连的柔性电 路板上。
12、 如权利要求 8所述的阵列基板， 包括公共电极线、 四条第一短路环 以及两条第二短路环， 其中，
每条数据线分别通过两个第一静电释放装置连接第一短路环； 每个第一静电释放装置仅连接一条数据线；
相邻两条数据线分别通过第一静电释放装置连接在不同的第一短路环 上；
每条栅极线分别通过两个第二静电释放装置连接第二短路环； 每个第二静电释放装置仅连接一条栅极线；
每条第一短路环通过两个第三静电释放装置连接公共电极线； 并且 每条第二短路环通过两个第四静电释放装置连接公共电极线。
13、 一种显示面板， 包括权利要求 1-12任一所述的阵列基板。
14、 一种显示装置， 包括如权利要求 13所述的显示面板。
PCT/CN2014/081246 2013-12-30 2014-06-30 阵列基板、显示面板和显示装置 Ceased WO2015100989A1 (zh)

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