CN106935222A - 保护电路、阵列基板以及显示装置 - Google Patents

保护电路、阵列基板以及显示装置 Download PDF

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Publication number
CN106935222A
CN106935222A CN201710364479.0A CN201710364479A CN106935222A CN 106935222 A CN106935222 A CN 106935222A CN 201710364479 A CN201710364479 A CN 201710364479A CN 106935222 A CN106935222 A CN 106935222A
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Prior art keywords
film transistor
tft
thin film
protection circuit
pole
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CN201710364479.0A
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郝学光
乔勇
吴新银
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201710364479.0A priority Critical patent/CN106935222A/zh
Publication of CN106935222A publication Critical patent/CN106935222A/zh
Priority to AU2017404569A priority patent/AU2017404569B2/en
Priority to JP2018550703A priority patent/JP7152313B2/ja
Priority to KR1020187029992A priority patent/KR102112714B1/ko
Priority to BR112018071713-4A priority patent/BR112018071713A2/pt
Priority to EP17901336.2A priority patent/EP3633665A4/en
Priority to PCT/CN2017/112561 priority patent/WO2018214434A1/zh
Priority to MX2018012661A priority patent/MX2018012661A/es
Priority to US16/072,863 priority patent/US10658352B2/en
Priority to RU2018136204A priority patent/RU2731838C1/ru
Pending legal-status Critical Current

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Abstract

本发明涉及一种保护电路、阵列基板以及显示装置。该保护电路包括控制模块和放电模块，所述控制模块一端电连接电压输入端，另一端电连接放电模块，所述放电模块与至少一条数据线电连接；所述控制模块包括第一薄膜晶体管和第二薄膜晶体管；所述放电模块包括至少一行第三薄膜晶体管。该保护电路能够及时释放由于显示装置瞬间断电而引起的数据线上积累的电荷，避免了关机闪烁和静电损伤，从而提高了液晶显示装置的显示品质。

Description

保护电路、阵列基板以及显示装置
技术领域
本发明涉及显示技术领域，具体涉及一种保护电路、阵列基板和显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor liquid crystal display,TFT-LCD)断电瞬间，由于数据线上的电荷未能及时释放，显示屏内部容易造成电荷积累，造成关机闪烁不良；当显示屏内部的电荷积累到一定程度，容易导致数据线之间发生静电放电，从而损伤薄膜晶体管器件，造成液晶显示装置显示功能失效；为了解决上述技术问题中国专利CN101217026A公开了采用电源检测外部电源电压的切断并提供放电信号，栅极驱动器响应于该放电信号将栅极驱动信号同时提供给多条栅极线，放大器响应于该放电信号，将公共电压提供给多条数据线，该电路保护技术的外部电路设计结构复杂，且未能将更多的外部电路集成在显示面板内部，降低了液晶显示面板的附加值。
发明内容
为了解决现有技术中数据线上的电荷在液晶显示屏断电瞬间，不能完全迅速释放，容易导致LCD出现关机闪烁、静电放电损伤的问题，本发明实施例提供了一种保护电路、阵列基板、液晶显示面板及显示装置。所述技术方案如下：
第一方面，提供了一种保护电路，所述保护电路包括控制模块、放电模块，所述控制模块一端电连接电压输入端，另一端电连接放电模块，所述放电模块与至少一条数据线电连接；所述控制模块通过放电模块控制数据线上的电荷释放。
进一步地，所述控制模块包括第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的第一极与所述第一薄膜晶体管的第三极、电压输入端电连接，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第二极电连接；所述第二薄膜晶体管的第一极与所述第一薄膜晶体管的第一极电连接，所述第二薄膜薄膜晶体管的第二极与所述第二薄膜晶体管的第三极、控制模块的输出信号线电连接。
进一步地，所述放电模块包括至少一行第三薄膜晶体管，所述第三薄膜晶体管的第一极与数据线电连接，所述第三薄膜晶体管的第二极与所述第三薄膜晶体管的第三极、控制模块的输出信号线电连接。
进一步地，所述放电模块包括至少一行第三薄膜晶体管，所述第三薄膜晶体管的第一极与数据线电连接，所述第三薄膜晶体管的第二极与电荷共享线电连接，所述第三薄膜晶体管的第三极与控制模块的输出信号线电连接。
进一步地，所述放电模块包括至少一行第三薄膜晶体管，所述第三薄膜晶体管的第一极、第二极与相邻的数据线电连接，所述第三薄膜晶体管的第三极与放电模块的输出信号线电连接。
具体地，所述电荷共享线的电位为悬浮电位。
具体地，所述控制模块的电压输入端电连接公共电压信号。
具体地，所述第一薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管,所述第二薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管,所述第三薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
第二方面，提供了一种阵列基板，所述阵列基板包括所述保护电路。
具体地，保护电路设置于阵列基板的数据据线信号输入端和/或数据线信号输入端的对侧。
第三方面，提供了一种显示装置，所述显示装置包括所述阵列基板。
本发明实施例提供的技术方案带来的有益效果是：
本发明控制模块的一端电连接电压输入端、另一端电连接放电模块，放电模块与至少一条数据线电连接；控制模块通过放电模块控制数据线上的电荷释放。显示装置断电瞬间，控制模块的输出信号控制放电模块的第三薄膜晶体管导通，将数据线上的电荷快速释放，避免因数据线上的电荷不能快速释放，导致薄膜晶体管损伤，显示装置出现关机闪烁不良或静电损伤的不良状况发生。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的保护电路的结构示意图；
图2为本发明又一实施例提供的保护电路的结构示意图；
图3为本发明又一实施例提供的保护电路的结构示意图；
图4为本发明任一实施例的保护电路设置于数据线信号输入端；
图5为本发明任一实施例的保护电路设置于数据线信号输入端的对侧；
图6为本发明任一实施例的保护电路设置于数据线信号输入端和数据线信号输入端的对侧。
附图标记：
100-保护电路；101-控制模块；102-放电模块；10-电压输入端；20-控制模块的输出信号线；30-电荷共享线；40-阵列基板；50-数据线驱动芯片；01-第一薄膜晶体管；011-第一源极；012-第一漏极；013-第一栅极；02-第二薄膜晶体管；021-第二源极；022-第二漏极；023-第二栅极；03-第三薄膜晶体管；031-第三源极；032-第三漏极；033-第三栅极；DL1、DL2…DL_N-1、DL_N-第一数据线、第二数据线…第N-1数据线、第N数据线。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开中，薄膜晶体管(Thin Film Transistor，TFT)简写为TFT。相应的，第一薄膜晶体管简写为TFT01，第二薄膜晶体管简写为TFT02，第三薄膜晶体管简写为TFT03。并且，本公开中，源极和漏极相对而言，可相互替换。例如，将源极替换为漏极的情况下，漏极亦替换为源极。
实施例一
如图1，本发明实施例提供了一种保护电路，该保护电路包括控制模块101和放电模块102；控制模块101包括第一薄膜晶体管和第二薄膜晶体管；第一薄膜晶体管的栅电极和源电极电连接电压输入端10，电压输入端10电连接公共电压信号，第一薄膜晶体管的漏电极电连接第二薄膜晶体管的栅电极和源电极；第二薄膜晶体管的漏电极电连接第一薄膜晶体管的源电极和栅电极，第二薄膜晶体管的源电极和栅电极电连接放电模块的输出信号线20；放电模块的输出信号线20包括横向和纵向电连接的多条信号线。第一薄膜晶体管和第二薄膜晶体管，用于在电压输入端10输入的公共电压信号的作用下将公共电压信号输出到放电模块的输出信号线20。
放电模块102包括至少一行第三薄膜晶体管，第三薄膜晶体管横向的数量和数据线的条数相对应，第三薄膜晶体管的漏电极电连接数据线、第三薄膜晶体管的源电极和栅电极电连接放电模块的输出信号线20；第三薄膜晶体管，用于在控制模块102的输出的公共电压信号的作用下将数据线上的电荷释放到放电模块的输出信号线20。
阵列基板包括衬底基板、保护电路、像素单元以及形成在衬底基板上的栅线和数据线，在本发明实施例中，保护电路的控制模块输出信号线20与栅线同层设置，其中，输出信号线20包括纵向的信号线和横向的信号线，控制模块的第二薄膜晶体管的栅电极、源电极与纵向的信号线电连接；保护电路的放电模块的第三薄膜晶体管的栅电极、源电极与横向的信号线电连接；第三薄膜晶体管的漏电极与数据线电连接。
在显示装置断电过程中，栅极信号控制端经栅线控制像素单元的薄膜晶体管关闭，此时数据线上的电荷未能及时释放，出现了电荷积累，则像素单元不能立即停止工作，会导致显示装置出现关机闪烁、静电放电损伤等不良情况。
在本发明实施例中，放电模块102的第三薄膜晶体管的栅电极、源电极经放电模块的输出信号线20、控制模块101与电压输入端10电连接，第三薄膜晶体管的漏电极与数据线电连接，放电模块的输出信号线20和电压输入端10形成在阵列基板的衬底基板上。当在阵列基板上使用本发明的实施例提供的保护电路时，显示装置断电过程中数据线上出现了电荷积累，则电压输入端10输出公共电压信号，控制放电模块的第一薄膜晶体管和第二薄膜晶体管导通，放电模块输出信号线20输出控制信号，控制放电模块102的第三薄膜晶体管导通，数据线上的电荷经第三薄膜晶体管释放到放电模块102的输出信号线20；避免因数据线上的电荷不能完全迅速释放，显示装置出现闪烁、静电放电损伤的不良状况发生。
在本发明实施例中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管可以为N型薄膜晶体管或P型薄膜晶体管。第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管为N型薄膜晶体管，电压输入端10输入高电平信号时第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管导通；若第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管为P型薄膜晶体管，则电压输入端10输入低电平信号时第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管导通。
实施例二
如图2，本发明实施例提供了一种保护电路，该保护电路包括控制模块101和放电模块102；控制模块101包括第一薄膜晶体管和第二薄膜晶体管；第一薄膜晶体管的栅电极和源电极电连接电压输入端10，电压输入端10电连接公共电压信号，第一薄膜晶体管的漏电极电连接第二薄膜晶体管的栅电极和源电极；第二薄膜晶体管的漏电极电连接第一薄膜晶体管的源电极和栅电极，第二薄膜晶体管的源电极和栅电极电连接放电模块的输出信号线20；放电模块的输出信号线20包括横向和纵向电连接的多条信号线。第一薄膜晶体管和第二薄膜晶体管，用于在电压输入端10输入的公共电压信号的作用下将公共电压信号输出到放电模块的输出信号线20。
放电模块102包括至少一行第三薄膜晶体管管，第三薄膜晶体管横向的数量和数据线的条数相对应，第三薄膜晶体管的漏电极电连接数据线、第三薄膜晶体管的栅电极电连接输出信号线20、第三薄膜晶体管的源电极电连接电荷共享线30；第三薄膜晶体管，用于在控制模块102的输出的公共电压信号的作用下将数据线上的电荷释放到电荷共享线30。
阵列基板包括衬底基板、保护电路、像素单元以及形成在衬底基板上的栅线和数据线，在本发明实施例中，保护电路的控制模块输出信号线20与栅线同层设置，电荷共享线30与数据线同层设置，其中，输出信号线20包括纵向的信号线和横向的信号线，控制模块的第二薄膜晶体管的栅电极、源电极与纵向的信号线电连接；放电模块的第三薄膜晶体管的源电极与数据线电连接，第三薄膜晶体管的栅电极与横向的信号线电连接，第三薄膜晶体管的漏电极与电荷共享线30电连接。
在显示装置断电过程中，栅极信号控制端经栅线控制像素单元的薄膜晶体管关闭，此时数据线上的电荷未能及时释放，出现了电荷积累，则像素单元不能立即停止工作，会导致显示装置出现关机闪烁、静电放电损伤等不良情况。
在本发明实施例中，放电模块102的第三薄膜晶体管的栅电极经放电模块的输出信号线20、控制模块101与电压输入端10电连接，第三薄膜晶体管的漏电极与数据线电连接，第三薄膜晶体管的源电极与电荷共享线30电连接，放电模块的输出信号线20、电荷共享线30、电压输入端10形成在阵列基板的衬底基板上。当在阵列基板上使用本发明的实施例提供的电荷共享电路时，显示装置断电过程中数据线上出现了电荷积累，则电压输入端10输出公共电压信号，控制放电模块的第一薄膜晶体管和第二薄膜晶体管导通，放电模块输出信号线20输出控制信号，控制放电模块102的第三薄膜晶体管导通，数据线上的电荷经第三薄膜晶体管释放到放电模块102的电荷共享线30；避免因数据线上的电荷不能完全迅速释放，显示装置出现闪烁、静电放电损伤的不良状况发生。
在本发明实施例中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管可以为N型薄膜晶体管或P型薄膜晶体管；第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管为N型薄膜晶体管，电压输入端10输入高电平信号时第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管导通；若第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管为P型薄膜晶体管，则电压输入端10输入低电平信号时第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管导通。
实施例三
如图3，本发明实施例提供了一种保护电路，该保护电路包括控制模块101和放电模块102；控制模块101包括第一薄膜晶体管和第二薄膜晶体管；第一薄膜晶体管的栅电极和源电极电连接电压输入端10，电压输入端10电连接公共电压信号，第一薄膜晶体管的漏电极电连接第二薄膜晶体管的栅电极和源电极；第二薄膜晶体管的漏电极电连接第一薄膜晶体管的源电极和栅电极，第二薄膜晶体管的源电极和栅电极电连接放电模块的输出信号线20；放电模块的输出信号线20包括横向和纵向电连接的多条信号线。第一薄膜晶体管和第二薄膜晶体管，用于在电压输入端10输入的公共电压信号的作用下将公共电压信号输出到放电模块的输出信号线20。
放电模块102包括至少一行第三薄膜晶体管，第三薄膜晶体管横向的数量和数据线的条数相对应，第三薄膜晶体管的第一极、第二极与相邻的数据线电连接，第三薄膜晶体管的控制极与输出信号线20电连接。第三薄膜晶体管，用于在控制模块102输出的公共电压信号的作用下将相邻列数据线上的正负电荷相互中和。
阵列基板包括衬底基板、保护电路、像素单元以及形成在衬底基板上的栅线和数据线，在本发明实施例中，保护电路的控制模块输出信号线20与栅线同层设置，其中，输出信号线20包括纵向的信号线和横向的信号线，控制模块的第二薄膜晶体管的栅电极、源电极与纵向的信号线电连接；放电模块的第三薄膜晶体管的源电极、漏电极与数据线电连接，第三薄膜晶体管的栅电极与横向的信号线电连接。
在显示装置断电过程中，栅极信号控制端经栅线控制像素单元的薄膜晶体管关闭，此时数据线上的电荷未能及时释放，出现了电荷积累，则像素单元不能立即停止工作，会导致显示装置出现关机闪烁、静电放电损伤等不良情况。
在本发明实施例中，放电模块102的第三薄膜晶体管的栅电极经放电模块的输出信号线20、控制模块101与电压输入端10电连接，第三薄膜晶体管的漏电极、源电极与数据线电连接，放电模块的输出信号线20、电压输入端10形成在阵列基板的衬底基板上。当在阵列基板上使用本发明的实施例提供的保护电路时，显示装置断电过程中数据线上出现了电荷积累，则电压输入端10输出控制信号，控制放电模块的第一薄膜晶体管和第二薄膜晶体管导通，放电模块输出信号线20输出控制信号，控制放电模块102的第三薄膜晶体管导通，相邻列数据线上的正负电荷发生中和；避免因数据线上的电荷不能完全迅速释放，显示装置出现闪烁、静电放电损伤的不良状况发生。
在本发明实施例中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管可以为N型薄膜晶体管或P型薄膜晶体管；第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管为N型薄膜晶体管，电压输入端10输入高电平信号时第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管导通；若第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管为P型薄膜晶体管，则电压输入端10输入低电平信号时第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管导通。
实施例四
本发明实施例提供了一种显示装置，该显示装置包括实施例一、实施例二、实施例三所述的保护电路中的至少一种。
本发明在液晶显示面板中的阵列基板上设置保护电路，该保护电路结构如图1-图3所示；如图4，该保护电路可以设置于液晶显示面板的数据线信号输入端，如图5，该保护电路也可以设置于液晶显示面板的数据线信号输入端的对侧，如图6，该保护电路还可以同时设置于液晶显示面板的数据线信号输入端和数据线信号输入端的对侧。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种显示装置的保护电路，其特征在于，该保护电路包括控制模块(101)、放电模块(102)，所述控制模块(101)一端电连接电压输入端(10)，另一端电连接放电模块(102)，所述放电模块(102)与至少一条数据线电连接；所述控制模块(101)通过放电模块(102)控制数据线上的电荷释放。
2.根据权利要求1所述的保护电路，其特征在于，所述控制模块(101)包括第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的第一极与所述第一薄膜晶体管的第三极、电压输入端(10)电连接，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第二极电连接；所述第二薄膜晶体管的第一极与所述第一薄膜晶体管的第一极电连接，所述第二薄膜薄膜晶体管的第二极与所述第二薄膜晶体管的第三极、控制模块的输出信号线(20)电连接。
3.根据权利要求1所述的保护电路，其特征在于，所述放电模块(102)包括至少一行第三薄膜晶体管，所述第三薄膜晶体管的第一极与数据线电连接，所述第三薄膜晶体管的第二极与所述第三薄膜晶体管的第三极、控制模块(101)的输出信号线(20)电连接。
4.根据权利要求1所述的保护电路，其特征在于，所述放电模块(102)包括至少一行第三薄膜晶体管，所述第三薄膜晶体管的第一极与数据线电连接，所述第三薄膜晶体管的第二极与电荷共享线(30)电连接，所述第三薄膜晶体管的第三极与控制模块(101)的输出信号线(20)电连接。
5.根据权利要求1所述的保护电路，其特征在于，所述放电模块(102)包括至少一行第三薄膜晶体管，所述第三薄膜晶体管的第一极、第二极与相邻的数据线电连接，所述第三薄膜晶体管的第三极与放电模块(101)的输出信号线(20)电连接。
6.根据权利要求4所述的保护电路，其特征在于，所述电荷共享线(30)的电位为悬浮电位。
7.根据权利要求1-5任意一项所述的保护电路，其特征在于，所述控制模块(101)的电压输入端(10)电连接公共电压信号。
8.根据权利要求1-5任意一项所述的保护电路，其特征在于，所述第一薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管,所述第二薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管,所述第三薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
9.一种阵列基板，其特征在于，包括权利要求1-8任一项所述的保护电路，所述保护电路设置于阵列基板的数据据线信号输入端和/或数据线信号输入端的对侧。
10.一种显示装置，其特征在于，包括权利要求9所述的阵列基板。
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