WO2015096433A1 - Appareil et procédé d'extension de la largeur de bande d'échantillonnage d'un convertisseur analogique/numérique - Google Patents

Appareil et procédé d'extension de la largeur de bande d'échantillonnage d'un convertisseur analogique/numérique Download PDF

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Publication number
WO2015096433A1
WO2015096433A1 PCT/CN2014/080770 CN2014080770W WO2015096433A1 WO 2015096433 A1 WO2015096433 A1 WO 2015096433A1 CN 2014080770 W CN2014080770 W CN 2014080770W WO 2015096433 A1 WO2015096433 A1 WO 2015096433A1
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WIPO (PCT)
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sampling
adc
circuit
group
delay
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PCT/CN2014/080770
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English (en)
Chinese (zh)
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蓝翱华
田建伟
王珊
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中兴通讯股份有限公司
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Publication of WO2015096433A1 publication Critical patent/WO2015096433A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Definitions

  • the present invention relates to the field of wireless communications, and in particular, to an extended ADC (Analog to Digital) Converter, analog to digital converter) device and method for sampling bandwidth.
  • ADC Analog to Digital
  • FIG. 1 The principle of the existing ADC sampling is shown in Figure 1.
  • the analog circuit is taken by an ADC.
  • the sampling frequency is fixed, along with the input signal.
  • the number of relative sampling points becomes less and less, and the recovered signals become more and more inaccurate.
  • the restored signal is not aliased, it is necessary to satisfy the Nyquist sampling law.
  • Sampling to restore higher frequencies requires a higher sampling rate.
  • the existing ADC cannot adapt to the change of the input signal due to the sampling rate, and the relative sampling The number of points is too small, so the bandwidth that can be handled is limited.
  • an embodiment of the present invention provides an extended ADC sampling band. Wide device and method.
  • Embodiments of the present invention provide an apparatus for extending an ADC sampling bandwidth, where the apparatus includes sampling a clock circuit, a multi-channel ADC circuit, and a combining circuit;
  • the sampling clock circuit is coupled to the multi-channel ADC circuit and configured to provide the multi-channel ADC
  • the circuit provides a sampling clock
  • the multi-channel ADC circuit is configured to input an analog signal under the control of a sampling clock Multi-channel sampling, with sampling delay between each sample;
  • the combining circuit is connected to the multi-channel ADC circuit and configured to perform multi-channel sampling data merge.
  • the multi-channel ADC circuit includes n sets of ADCs and n-1 sets of delay circuits.
  • the delay circuit is located between the analog circuit and the ADC, configured to input The analog signal is delayed.
  • each group of delay circuits is connected to the analog circuit, and the delay of the first group to the n-1th group
  • the outputs of the circuits are connected to the inputs of the Group 2 to Group n ADCs, respectively.
  • the delay circuits of the first group to the n-1th group are sequentially connected in series, and the input ends of the delay circuits of the first group Connected to the analog circuit, the output terminals of the first group to the n-1th delay circuit are respectively connected to the second group to the nth The inputs of the group ADC are connected.
  • the delay circuit is located between the sampling clock circuit and the ADC, and is configured to be The sample clock signal is delayed.
  • each group of delay circuits is connected to the sampling clock circuit, and the first group to the n-1th
  • the output terminals of the group delay circuit are respectively connected to the sampling control terminals of the second to nth groups of ADCs.
  • the delay circuits of the first group to the n-1th group are sequentially connected in series, and the input ends of the delay circuits of the first group Connected to the sampling clock circuit, the output ends of the first group to the n-1th delay circuit are respectively the second The sampling control terminals of the group to the nth group of ADCs are connected.
  • the sampling delay between adjacent ADC circuits is Wherein, in the multi-channel ADC circuit, the sampling delay between adjacent ADC circuits is Where T is the sampling period of the sampling clock circuit, and n is the number of paths of the ADC circuit.
  • the combining circuit is an OR gate circuit.
  • An embodiment of the present invention further provides a method for extending an ADC sampling bandwidth, where the method includes Next steps:
  • the input analog signal is multi-channel sampled, and each sample is sampled. With a sampling delay;
  • the multi-channel sampling of the input analog signal is: the sampling clock is unchanged, and the input is The incoming analog signal is sampled after a delay.
  • the multi-channel sampling of the input analog signal is: the analog signal is unchanged, The sample clock signal is sampled after a delay.
  • the sampling delay between adjacent paths is Wherein, the sampling delay between adjacent paths is Where T is the sampling period and n is the number of paths.
  • the combining the multi-channel sampling data into: multi-channel sampling data is performed on the signal phase plus.
  • the embodiment of the invention uses a multi-channel ADC circuit, and each ADC circuit sampling time is relatively Delay; cross-combining the data acquired by these ADC circuits after sampling to resolve relative sampling The problem of too few points can increase the sampling bandwidth at a low sampling rate.
  • FIG. 1 is a structural diagram of a prior art ADC sampling device
  • 2a is a sampling effect diagram of a prior art low input signal
  • 2b is a sampling effect diagram of a prior art high input signal
  • FIG. 3 is a structural diagram of an apparatus for extending an ADC sampling bandwidth according to an embodiment of the present invention.
  • FIG. 4a is a specific structural diagram of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention
  • FIG. 4b is another specific structure of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention.
  • FIG. 4d is a specific structure of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention.
  • Figure 5a is a schematic diagram of a prior art single ADC sampling
  • FIG. 5b is a schematic diagram of joint interleaved sampling using two ADCs according to an embodiment of the present invention.
  • 6a is a schematic diagram of joint interleaved sampling using two ADCs according to an embodiment of the present invention
  • 6b is a schematic diagram of sampling after the single ADC rate is increased by one time in the prior art
  • FIG. 7a is a device for expanding an ADC sampling bandwidth using two ADCs according to an embodiment of the present invention.
  • FIG. 7b is another device for expanding the sampling bandwidth of an ADC by using two ADCs according to an embodiment of the present invention.
  • FIG. Structure diagram is another device for expanding the sampling bandwidth of an ADC by using two ADCs according to an embodiment of the present invention.
  • FIG. 8a is a schematic diagram of signal sampling of a 40 MHz signal taken by a two-way ADC according to an embodiment of the present invention
  • FIG. 8b is a schematic diagram of signal sampling of a 60 MHz signal when two ADCs are used in an embodiment of the present invention.
  • FIG. 9a is a diagram of expanding an ADC using four ADCs according to an embodiment of the present invention. a structural diagram of a device for sampling bandwidth;
  • FIG. 9b is another embodiment of the present invention according to an embodiment of the present invention using four ADCs to expand A block diagram of the device for sampling the bandwidth of the ADC;
  • FIG. 10a is a schematic diagram of signal sampling of a 40 MHz signal when a four-channel ADC is used according to an embodiment of the present invention
  • FIG. 10b is a schematic diagram of signal sampling of a 60 MHz signal when a four-channel ADC is used according to an embodiment of the present invention.
  • FIG. 10c is a schematic diagram of signal sampling of a 140 MHz signal when a four-channel ADC is used according to an embodiment of the present invention.
  • FIG. 10d is a schematic diagram of signal sampling of a 160 MHz signal when a four-channel ADC is used in an embodiment of the present invention.
  • the embodiment of the present invention provides An apparatus and method for expanding an ADC sampling bandwidth, the following is a combination of the drawings and the embodiments Ming will be further elaborated. It should be understood that the specific embodiments described herein are only used to solve The present invention is not limited by the invention.
  • an apparatus for expanding an ADC sampling bandwidth includes a sampling clock circuit 31, a multi-channel ADC circuit 32, and a combining circuit 33.
  • the sampling clock circuit 31 is connected to the multi-channel ADC circuit 32. Configuring to provide a sampling clock to the multi-channel ADC circuit 32; the multi-channel ADC circuit 32 is configured to multi-sample the input analog signal under the control of the sampling clock, with sampling delay between each sampling
  • the combining circuit 33 is connected to the multi-channel ADC circuit 32 and configured to combine the multi-channel sampling data.
  • the combining circuit adopts an OR gate circuit.
  • the multiplex ADC circuit 32 includes n sets of ADCs 321 and n-1 sets of delay circuits 322, and the first to nth sets of delay circuits are respectively connected to the second to nth sets of ADCs.
  • the sampling delay between adjacent ADCs 321 is Where T is the sampling period of the sampling clock circuit 31, and n is the number of paths of the ADC circuit.
  • connection mode of the ADC 321 and the delay circuit 322 are divided into two types, one is a delay circuit. 322 is located between the analog circuit and the ADC 321 for delaying the input analog signal; One is that the delay circuit 322 is located between the sampling clock circuit 31 and the ADC 321 for sampling The clock signal is delayed.
  • connection mode The first type is shown in FIG. 4a, and the input end of each group of delay circuits 322 is connected to an analog circuit. The output terminals of the first group to the n-1th group delay circuit 322 are respectively associated with the second group to the nth group AD C321 The input is connected. Second, as shown in FIG. 4b, the delay circuits 322 of the first group to the n-1th group are sequentially connected in series. The input end of the first group delay circuit 322 is connected to the analog circuit, and the first group to the n-1th group delay circuit The output of 322 is connected to the input of the second to nth groups of ADCs 321 respectively.
  • the delay circuit 322 When the delay circuit 322 is located between the sampling clock circuit 31 and the ADC 321, it is further divided into the following Two connection modes: the first type is shown in Figure 4c, the input end of each set of delay circuit 322 and the extraction The sample clock circuit 31 is connected, and the output ends of the first group to the n-1th group delay circuit 322 are respectively connected to the second The sampling control terminals of the group to the nth group ADC321 are connected.
  • the second type is shown in Figure 4d, the first group ⁇ the first The n-1 group delay circuit 322 is sequentially connected in series, and the input end of the first group delay circuit 322 and the sampling time The clock circuit 31 is connected, and the output terminals of the first group to the n-1th group delay circuit 322 are respectively connected to the second group to the first The sampling control terminals of the n groups of ADC321 are connected.
  • the input analog signal is multi-channel sampled, and each sample has a sampling delay.
  • the sampling delay between adjacent paths is Where T is the sampling period and n is the number of paths.
  • FIG. 5a is A schematic diagram of a single ADC sampling in the prior art
  • FIG. 5b is a joint interleaving using two ADCs in this embodiment. Sampling schematic.
  • FIG. 6a The sampling result of this embodiment is similar to that of the ADC which is doubled by using one sampling rate.
  • the sampling effects are compared, as shown in FIG. 6a and FIG. 6b, wherein FIG. 6a uses two for the embodiment.
  • the ADC is combined with the interleaved sampling diagram, and FIG. 6b is a schematic diagram of sampling after the single ADC rate is doubled.
  • the above comparison shows that the two ADCs delay sampling and achieve an ADC
  • the sampling effect is doubled after the sampling rate is doubled; thus, the two ADCs delay sampling can be used.
  • the sample bandwidth is extended to twice, and the same four ADCs are delayed by 0, 1/4 clock, 1/2 clock, 3/4 Clock sampling and then merging can extend the sampling bandwidth by a factor of four. Therefore, the present invention can be based on It is necessary to increase the number of ADCs connected in parallel to increase the sampling bandwidth at low sampling rates.
  • an analysis is performed by using two ADCs to expand the sampling bandwidth of the ADC.
  • This implementation The following two ways are used: the first one is shown in Figure 7a, in the case of clock synchronization, through the input After the signal is split, the delay is obtained from the combined data of the ADC; the second is shown in Figure 7b, which is the sampling time. The clock difference is half a sample period, and the ADC's clock delay is used to obtain the combined data of the ADC.
  • a sampling clock of 100 MHz is used for signals of 40 MHz and 60 MHz, respectively.
  • Sampling, 40MHz signal sampling diagram shown in Figure 8a, 60MHz signal sampling The intent is shown in Figure 8b.
  • N1, N2 are single ADCs
  • N4 is the combined data of two ADCs
  • FFT Fast Fourier Transformation, Fast Fourier Transform
  • the sampling rate of 100MHz due to aliasing Unable to distinguish between 40MHz and 60MHz frequencies, all recovered to the first Nyquist 40MHz Signal; while the two ADC data are combined, they can be distinguished; the sampling bandwidth is from the original one.
  • This embodiment analyzes the sampling bandwidth of the ADC by using four ADCs as an example.
  • This implementation The following two ways are used: the first one is shown in Figure 9a, which is 1/4 sample of the adjacent sampling clock difference. Cycle, the ADC's clock delay gets the combined data of the ADC; the second is shown in Figure 9b, In the case of clock synchronization, the combined data of the ADC is obtained by delaying the input signal after the delay.
  • a sampling clock of 100 MHz is used for 40 MHz, 60 MHz, and 140 MHz, respectively.
  • the 160MHz signal is sampled, and the 40MHz signal sampling diagram is shown in Figure 10a.
  • the signal sampling diagram is shown in Figure 10b, and the 140MHz signal sampling diagram is shown in Figure 10c.
  • the embodiment of the invention uses a multi-channel ADC circuit, and each ADC circuit sampling time is relatively Delay; cross-combining the data acquired by these ADC circuits after sampling to resolve relative sampling The problem of too few points can increase the sampling bandwidth at a low sampling rate.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Cette invention concerne un appareil d'extension de la largeur de bande d'échantillonnage d'un convertisseur analogique/numérique (CAN), ledit appareil comprenant un circuit d'horloge d'échantillonnage, un circuit CAN multicanaux et un circuit multiplexeur Ledit circuit d'horloge d'échantillonnage est connecté au circuit CAN multicanaux et il est conçu pour former une horloge d'échantillonnage pour le circuit CAN multicanaux. Ledit circuit CAN multicanaux est conçu pour assurer l'échantillonnage multicanaux d'un signal analogique reçu en entrée sous le contrôle de l'horloge d'échantillonnage, un retard d'échantillonnage existant entre deux canaux d'échantillonnage. Ledit circuit multiplexeur est connecté au circuit CAN multicanaux et il est conçu pour combiner plusieurs canaux de données d'échantillonnage. L'invention concerne en outre un procédé d'extension de la largeur de bande d'échantillonnage d'un CAN.
PCT/CN2014/080770 2013-12-27 2014-06-25 Appareil et procédé d'extension de la largeur de bande d'échantillonnage d'un convertisseur analogique/numérique WO2015096433A1 (fr)

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CN201310739224.XA CN104753534A (zh) 2013-12-27 2013-12-27 一种扩展adc采样带宽的装置和方法
CN201310739224.X 2013-12-27

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CN111095430A (zh) * 2019-11-29 2020-05-01 深圳市汇顶科技股份有限公司 生物特征数据的采样方法及其采样管理装置
WO2021004439A1 (fr) * 2019-07-08 2021-01-14 中兴通讯股份有限公司 Procédé et appareil de détection de phase de signal d'horloge, et dispositif de communication

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CN110350920B (zh) * 2019-08-09 2023-04-07 成都铭科思微电子技术有限责任公司 多通道adc系统同步采样的装置及方法
CN111130648B (zh) * 2019-12-31 2021-06-08 中国科学院微电子研究所 一种光通信信号接收方法、信号接收装置和电子设备
CN112067868B (zh) * 2020-09-07 2023-04-21 中电科思仪科技股份有限公司 一种具有自动校准功能的数字示波器多路adc交叉采样电路及其校准方法

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WO2021004439A1 (fr) * 2019-07-08 2021-01-14 中兴通讯股份有限公司 Procédé et appareil de détection de phase de signal d'horloge, et dispositif de communication
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CN111095430A (zh) * 2019-11-29 2020-05-01 深圳市汇顶科技股份有限公司 生物特征数据的采样方法及其采样管理装置
CN111095430B (zh) * 2019-11-29 2024-02-27 深圳市汇顶科技股份有限公司 生物特征数据的采样方法及其采样管理装置

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