WO2015096433A1

WO2015096433A1 - Apparatus and method for expanding adc sampling bandwidth

Info

Publication number: WO2015096433A1
Application number: PCT/CN2014/080770
Authority: WO
Inventors: 蓝翱华; 田建伟; 王珊
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-12-27
Filing date: 2014-06-25
Publication date: 2015-07-02
Also published as: CN104753534A

Abstract

Disclosed is an apparatus for expanding an ADC sampling bandwidth, wherein the apparatus comprises a sampling clock circuit, a multi-channel ADC circuit and combiner circuit. The sampling clock circuit is connected to the multi-channel ADC circuit, and is configured to provide a sampling clock for the multi-channel ADC circuit. The multi-channel ADC circuit is configured to perform multi-channel sampling on an analog signal that is input under control of the sampling clock, wherein a sampling delay exists between two channels of sampling. The combiner circuit is connected to the multi-channel ADC circuit, and is configured to combine multiple channels of sampling data. Also disclosed is a method for expanding the ADC sampling bandwidth.

Description

Apparatus and method for expanding ADC sampling bandwidth

Technical field

The present invention relates to the field of wireless communications, and in particular, to an extended ADC (Analog to Digital) Converter, analog to digital converter) device and method for sampling bandwidth.

Background technique

With the development of wireless communication and the application of mixed mode technology, the bandwidth of transmitting and receiving signals is more The wider the width; for DPD (Digital Pre-Distortion) feedback sampling, In order to obtain sufficient nonlinear information, it is generally necessary to obtain a reverse of 5 to 7 times the bandwidth of the carrier signal. Feed signal; for example, 50MHz carrier signal, feedback needs to sample 250MHz ~ 350MHz, Pre-IQ (In-phase Quadrature) demodulator can be used to achieve 2 times sampling band Wide widening, according to the sampling rate of 184.32MHz, generally can be around 150MHz bandwidth, also It is not enough; there is a similar problem for the receiving ADC. After the bandwidth is widened, the aliasing is over. The band is sharply narrowed, and the requirements for the IF filter are getting higher and higher.

The principle of the existing ADC sampling is shown in Figure 1. The analog circuit is taken by an ADC. As shown in Figure 2a and Figure 2b, the sampling frequency is fixed, along with the input signal. As the frequency increases, the number of relative sampling points becomes less and less, and the recovered signals become more and more inaccurate. Under normal circumstances, if the restored signal is not aliased, it is necessary to satisfy the Nyquist sampling law. Sampling to restore higher frequencies requires a higher sampling rate.

However, the existing ADC cannot adapt to the change of the input signal due to the sampling rate, and the relative sampling The number of points is too small, so the bandwidth that can be handled is limited.

Summary of the invention

In order to solve the existing technical problems, an embodiment of the present invention provides an extended ADC sampling band. Wide device and method.

Embodiments of the present invention provide an apparatus for extending an ADC sampling bandwidth, where the apparatus includes sampling a clock circuit, a multi-channel ADC circuit, and a combining circuit;

The sampling clock circuit is coupled to the multi-channel ADC circuit and configured to provide the multi-channel ADC The circuit provides a sampling clock;

The multi-channel ADC circuit is configured to input an analog signal under the control of a sampling clock Multi-channel sampling, with sampling delay between each sample;

The combining circuit is connected to the multi-channel ADC circuit and configured to perform multi-channel sampling data merge.

The multi-channel ADC circuit includes n sets of ADCs and n-1 sets of delay circuits.

Wherein the delay circuit is located between the analog circuit and the ADC, configured to input The analog signal is delayed.

Wherein, the input end of each group of delay circuits is connected to the analog circuit, and the delay of the first group to the n-1th group The outputs of the circuits are connected to the inputs of the Group 2 to Group n ADCs, respectively.

Wherein, the delay circuits of the first group to the n-1th group are sequentially connected in series, and the input ends of the delay circuits of the first group Connected to the analog circuit, the output terminals of the first group to the n-1th delay circuit are respectively connected to the second group to the nth The inputs of the group ADC are connected.

The delay circuit is located between the sampling clock circuit and the ADC, and is configured to be The sample clock signal is delayed.

Wherein, the input end of each group of delay circuits is connected to the sampling clock circuit, and the first group to the n-1th The output terminals of the group delay circuit are respectively connected to the sampling control terminals of the second to nth groups of ADCs.

Wherein, the delay circuits of the first group to the n-1th group are sequentially connected in series, and the input ends of the delay circuits of the first group Connected to the sampling clock circuit, the output ends of the first group to the n-1th delay circuit are respectively the second The sampling control terminals of the group to the nth group of ADCs are connected.

Wherein, in the multi-channel ADC circuit, the sampling delay between adjacent ADC circuits is

Where T is the sampling period of the sampling clock circuit, and n is the number of paths of the ADC circuit.

Wherein, the combining circuit is an OR gate circuit.

An embodiment of the present invention further provides a method for extending an ADC sampling bandwidth, where the method includes Next steps:

Under the control of the sampling clock, the input analog signal is multi-channel sampled, and each sample is sampled. With a sampling delay;

Combine multiple sampled data.

Wherein, the multi-channel sampling of the input analog signal is: the sampling clock is unchanged, and the input is The incoming analog signal is sampled after a delay.

Wherein, the multi-channel sampling of the input analog signal is: the analog signal is unchanged, The sample clock signal is sampled after a delay.

Wherein, the sampling delay between adjacent paths is

Where T is the sampling period and n is the number of paths.

Wherein, the combining the multi-channel sampling data into: multi-channel sampling data is performed on the signal phase plus.

The beneficial effects of the embodiments of the present invention are as follows:

The embodiment of the invention uses a multi-channel ADC circuit, and each ADC circuit sampling time is relatively Delay; cross-combining the data acquired by these ADC circuits after sampling to resolve relative sampling The problem of too few points can increase the sampling bandwidth at a low sampling rate.

DRAWINGS

1 is a structural diagram of a prior art ADC sampling device;

2a is a sampling effect diagram of a prior art low input signal;

2b is a sampling effect diagram of a prior art high input signal;

3 is a structural diagram of an apparatus for extending an ADC sampling bandwidth according to an embodiment of the present invention;

4a is a specific structural diagram of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention;

FIG. 4b is another specific structure of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention; Figure

4c is another specific structure of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention; Figure

4d is a specific structure of an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention. Figure

Figure 5a is a schematic diagram of a prior art single ADC sampling;

FIG. 5b is a schematic diagram of joint interleaved sampling using two ADCs according to an embodiment of the present invention; FIG.

6a is a schematic diagram of joint interleaved sampling using two ADCs according to an embodiment of the present invention;

6b is a schematic diagram of sampling after the single ADC rate is increased by one time in the prior art;

7a is a device for expanding an ADC sampling bandwidth using two ADCs according to an embodiment of the present invention; Structure diagram

FIG. 7b is another device for expanding the sampling bandwidth of an ADC by using two ADCs according to an embodiment of the present invention; FIG. Structure diagram

FIG. 8a is a schematic diagram of signal sampling of a 40 MHz signal taken by a two-way ADC according to an embodiment of the present invention; FIG.

FIG. 8b is a schematic diagram of signal sampling of a 60 MHz signal when two ADCs are used in an embodiment of the present invention; FIG.

FIG. 9a is a diagram of expanding an ADC using four ADCs according to an embodiment of the present invention. a structural diagram of a device for sampling bandwidth;

FIG. 9b is another embodiment of the present invention according to an embodiment of the present invention using four ADCs to expand A block diagram of the device for sampling the bandwidth of the ADC;

FIG. 10a is a schematic diagram of signal sampling of a 40 MHz signal when a four-channel ADC is used according to an embodiment of the present invention; FIG.

FIG. 10b is a schematic diagram of signal sampling of a 60 MHz signal when a four-channel ADC is used according to an embodiment of the present invention; FIG.

FIG. 10c is a schematic diagram of signal sampling of a 140 MHz signal when a four-channel ADC is used according to an embodiment of the present invention; FIG.

FIG. 10d is a schematic diagram of signal sampling of a 160 MHz signal when a four-channel ADC is used in an embodiment of the present invention.

detailed description

In order to solve the problem that the processing bandwidth of the ADC in the prior art is limited, the embodiment of the present invention provides An apparatus and method for expanding an ADC sampling bandwidth, the following is a combination of the drawings and the embodiments Ming will be further elaborated. It should be understood that the specific embodiments described herein are only used to solve The present invention is not limited by the invention.

Example 1

As shown in FIG. 3, an apparatus for expanding an ADC sampling bandwidth according to an embodiment of the present invention includes a sampling clock circuit 31, a multi-channel ADC circuit 32, and a combining circuit 33. The sampling clock circuit 31 is connected to the multi-channel ADC circuit 32. Configuring to provide a sampling clock to the multi-channel ADC circuit 32; the multi-channel ADC circuit 32 is configured to multi-sample the input analog signal under the control of the sampling clock, with sampling delay between each sampling The combining circuit 33 is connected to the multi-channel ADC circuit 32 and configured to combine the multi-channel sampling data. In this embodiment, the combining circuit adopts an OR gate circuit. The multiplex ADC circuit 32 includes n sets of ADCs 321 and n-1 sets of delay circuits 322, and the first to nth sets of delay circuits are respectively connected to the second to nth sets of ADCs. In the multiplex ADC circuit 32, the sampling delay between adjacent ADCs 321 is

Where T is the sampling period of the sampling clock circuit 31, and n is the number of paths of the ADC circuit.

The connection mode of the ADC 321 and the delay circuit 322 are divided into two types, one is a delay circuit. 322 is located between the analog circuit and the ADC 321 for delaying the input analog signal; One is that the delay circuit 322 is located between the sampling clock circuit 31 and the ADC 321 for sampling The clock signal is delayed.

When the delay circuit 322 is located between the analog circuit and the ADC 321, it is further divided into the following two types. Connection mode: The first type is shown in FIG. 4a, and the input end of each group of delay circuits 322 is connected to an analog circuit. The output terminals of the first group to the n-1th group delay circuit 322 are respectively associated with the second group to the nth group AD C321 The input is connected. Second, as shown in FIG. 4b, the delay circuits 322 of the first group to the n-1th group are sequentially connected in series. The input end of the first group delay circuit 322 is connected to the analog circuit, and the first group to the n-1th group delay circuit The output of 322 is connected to the input of the second to nth groups of ADCs 321 respectively.

When the delay circuit 322 is located between the sampling clock circuit 31 and the ADC 321, it is further divided into the following Two connection modes: the first type is shown in Figure 4c, the input end of each set of delay circuit 322 and the extraction The sample clock circuit 31 is connected, and the output ends of the first group to the n-1th group delay circuit 322 are respectively connected to the second The sampling control terminals of the group to the nth group ADC321 are connected. The second type is shown in Figure 4d, the first group ~ the first The n-1 group delay circuit 322 is sequentially connected in series, and the input end of the first group delay circuit 322 and the sampling time The clock circuit 31 is connected, and the output terminals of the first group to the n-1th group delay circuit 322 are respectively connected to the second group to the first The sampling control terminals of the n groups of ADC321 are connected.

Example 2

A method for extending an ADC sampling bandwidth according to an embodiment of the present invention includes the following steps:

(1) Under the control of the sampling clock, the input analog signal is multi-channel sampled, and each sample has a sampling delay. In this embodiment, the sampling delay between adjacent paths is

Where T is the sampling period and n is the number of paths. When multi-channel sampling of the input analog signal, the sampling clock may be used unchanged, and the input analog signal may be sampled after delay; or the analog signal may be unchanged, and the sampling clock signal may be sampled after delay. .

(2) Combine the multi-channel sampling data.

Taking two ADCs as an example, each ADC sampling time is relatively delayed, this embodiment The sampling of the two ADCs is half a sampling period, and the data collected by these ADCs is handed over after sampling. The fork combination is to add signals to multiple samples of data. As shown in Figure 5a and Figure 5b, Figure 5a is A schematic diagram of a single ADC sampling in the prior art, and FIG. 5b is a joint interleaving using two ADCs in this embodiment. Sampling schematic.

The sampling result of this embodiment is similar to that of the ADC which is doubled by using one sampling rate. The sampling effects are compared, as shown in FIG. 6a and FIG. 6b, wherein FIG. 6a uses two for the embodiment. The ADC is combined with the interleaved sampling diagram, and FIG. 6b is a schematic diagram of sampling after the single ADC rate is doubled.

The above comparison shows that the two ADCs delay sampling and achieve an ADC The sampling effect is doubled after the sampling rate is doubled; thus, the two ADCs delay sampling can be used. The sample bandwidth is extended to twice, and the same four ADCs are delayed by 0, 1/4 clock, 1/2 clock, 3/4 Clock sampling and then merging can extend the sampling bandwidth by a factor of four. Therefore, the present invention can be based on It is necessary to increase the number of ADCs connected in parallel to increase the sampling bandwidth at low sampling rates.

Example 3

In this embodiment, an analysis is performed by using two ADCs to expand the sampling bandwidth of the ADC. This implementation The following two ways are used: the first one is shown in Figure 7a, in the case of clock synchronization, through the input After the signal is split, the delay is obtained from the combined data of the ADC; the second is shown in Figure 7b, which is the sampling time. The clock difference is half a sample period, and the ADC's clock delay is used to obtain the combined data of the ADC.

In this embodiment, a sampling clock of 100 MHz is used for signals of 40 MHz and 60 MHz, respectively. Sampling, 40MHz signal sampling diagram shown in Figure 8a, 60MHz signal sampling The intent is shown in Figure 8b. Referring to Figures 8a and 8b, the results are as follows, N1, N2 are single ADCs Sampling data, N4 is the combined data of two ADCs, and then doing FFT (Fast Fourier Transformation, Fast Fourier Transform) (in order to display the aliasing position, also use the interpolation N1 does FFT), from the results, for a single ADC, the sampling rate of 100MHz, due to aliasing Unable to distinguish between 40MHz and 60MHz frequencies, all recovered to the first Nyquist 40MHz Signal; while the two ADC data are combined, they can be distinguished; the sampling bandwidth is from the original one. The 斯特 domain 50MHz is extended to 50 x 2 = 100 MHz.

Example 4

This embodiment analyzes the sampling bandwidth of the ADC by using four ADCs as an example. This implementation The following two ways are used: the first one is shown in Figure 9a, which is 1/4 sample of the adjacent sampling clock difference. Cycle, the ADC's clock delay gets the combined data of the ADC; the second is shown in Figure 9b, In the case of clock synchronization, the combined data of the ADC is obtained by delaying the input signal after the delay.

In this embodiment, a sampling clock of 100 MHz is used for 40 MHz, 60 MHz, and 140 MHz, respectively. The 160MHz signal is sampled, and the 40MHz signal sampling diagram is shown in Figure 10a. 60MHz The signal sampling diagram is shown in Figure 10b, and the 140MHz signal sampling diagram is shown in Figure 10c. A schematic diagram of 160 MHz signal sampling is shown in Figure 10d. Referring to Figures 10a, 10b, 10c and Figure 10d, the results are as follows, N1, N2, N3, N4 are single ADC sampling data, Na is four The combined data of the ADCs, Na is the FFT (in order to display the aliasing position, the interpolated N2 is FFT). It can be seen from the results that the four ADC data are combined to distinguish 40MHz and 60MHz. And 140MHz, 160MHz frequency signal, the sampling bandwidth is from the original Nyquist domain 50MHz is extended to 50×4=200MHz.

Although preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art Members will be aware that various improvements, additions and substitutions are also possible, and therefore the scope of the invention should It is not limited to the above embodiment.

Claims

An apparatus for extending an ADC sampling bandwidth, the apparatus comprising a sampling clock circuit, Multiple ADC circuits and combining circuits;

The sampling clock circuit is connected to the multi-channel ADC circuit and configured to give the multi-channel The ADC circuit provides a sampling clock;

The multi-channel ADC circuit is configured to input an analog signal under the control of a sampling clock Perform multi-channel sampling with a sampling delay between each sample;

The combining circuit is connected to the multi-channel ADC circuit and configured to input multi-channel sampling data Line merge.
The apparatus for expanding an ADC sampling bandwidth according to claim 1, wherein said plurality of The circuit ADC circuit includes n sets of ADCs and n-1 sets of delay circuits.
The apparatus for expanding an ADC sampling bandwidth according to claim 2, wherein said delay The time circuit is located between the analog circuit and the ADC and is configured to delay the input analog signal Time.
The apparatus for expanding an ADC sampling bandwidth according to claim 3, wherein each group of delays The input end of the circuit is connected to the analog circuit, and the output ends of the delay circuits of the first group to the n-1th group are divided. Do not connect to the inputs of the Group 2 to Group n ADCs.
The apparatus for expanding an ADC sampling bandwidth according to claim 3, wherein the first group - The delay circuit of the n-1th group is connected in series, and the input end of the delay circuit of the first group is connected with the analog circuit. The output terminals of the delay circuits of the first group to the n-1th group are respectively input to the ADCs of the second group to the nth group connection.
The apparatus for expanding an ADC sampling bandwidth according to claim 2, wherein said delay a time circuit is disposed between the sampling clock circuit and the ADC, configured to perform a sampling clock signal Delay.
The apparatus for expanding an ADC sampling bandwidth according to claim 6, wherein each group of delays The input end of the circuit is connected to the sampling clock circuit, and the delay circuits of the first group to the n-1th group The output terminals are respectively connected to the sampling control ends of the second to nth groups of ADCs.
The apparatus for expanding an ADC sampling bandwidth according to claim 6, wherein the first group - The n-1th group delay circuit is sequentially connected in series, and the input end of the first group delay circuit is electrically connected to the sampling clock The connection of the first group to the n-1th delay circuit is respectively connected to the second group to the nth group ADC. The sampling control terminal is connected.
The apparatus for expanding an ADC sampling bandwidth according to any one of claims 1 to 8, wherein in said multi-channel ADC circuit, a sampling delay between adjacent ADC circuits is
Where T is the sampling period of the sampling clock circuit, and n is the number of paths of the ADC circuit.
An apparatus for expanding an ADC sampling bandwidth according to any one of claims 1 to 8, The combined circuit is an OR circuit.
A method of extending an ADC sampling bandwidth, the method comprising the steps of:

Under the control of the sampling clock, multi-channel sampling of the input analog signal, each sampling Having a sampling delay between;

Combine multiple sampled data.
A method of expanding an ADC sampling bandwidth as recited in claim 11 wherein said Multi-channel sampling the input analog signal: the sampling clock is unchanged, and the input analog signal Sampling after the delay.
A method of expanding an ADC sampling bandwidth as recited in claim 11 wherein said Multi-channel sampling the input analog signal: the analog signal is unchanged, and the sampling clock signal is delayed. Samples are taken afterwards.
A method of expanding an ADC sampling bandwidth according to any one of claims 11 to 13, wherein a sampling delay between adjacent paths is
Where T is the sampling period and n is the number of paths.
A method of expanding an ADC sampling bandwidth according to any one of claims 11 to 13, The combining the multi-channel sampling data into: adding the multi-channel sampling data to the signals.