WO2015087511A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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Publication number
WO2015087511A1
WO2015087511A1 PCT/JP2014/006031 JP2014006031W WO2015087511A1 WO 2015087511 A1 WO2015087511 A1 WO 2015087511A1 JP 2014006031 W JP2014006031 W JP 2014006031W WO 2015087511 A1 WO2015087511 A1 WO 2015087511A1
Authority
WO
WIPO (PCT)
Prior art keywords
coil
substrate
insulating film
semiconductor device
wiring
Prior art date
Application number
PCT/JP2014/006031
Other languages
English (en)
Japanese (ja)
Inventor
吉原　晋二
北村　康宏
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Publication of WO2015087511A1 publication Critical patent/WO2015087511A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors

Definitions

  • the present disclosure relates to a semiconductor device in which a coil is disposed on one side of a substrate and a manufacturing method thereof.
  • Patent Document 1 has proposed the following.
  • this semiconductor device a plurality of wiring portions and insulating films are alternately stacked on one surface side of the substrate in the normal direction to the one surface. Then, the wiring layers of the respective layers are appropriately connected through contact holes formed in the insulating films of the respective layers, so that a coil wound around the normal direction with respect to one surface of the substrate is configured.
  • a plurality of such coils are arranged in the surface direction of the substrate. That is, in this semiconductor device, it can be said that the substrate has a plurality of coil forming regions, and the coils are arranged on the respective coil forming regions.
  • the recessed part is formed in the part located between each coil among insulating films from the part on the opposite side to a board
  • the thermal stress caused by the difference in thermal expansion coefficient between the insulating film and the substrate can be relieved by the concave portion, and the warpage of the substrate can be suppressed.
  • the semiconductor device in which a coil is disposed on one surface side of a substrate, the semiconductor device capable of suppressing the substrate from being warped by stress generated between the insulating film covering the coil and the substrate, and the semiconductor device
  • An object is to provide a manufacturing method.
  • a semiconductor device covers a substrate having one surface, a coil formed on the one surface side of the substrate, and wound around a normal direction to the one surface of the substrate, and the coil And an insulating film.
  • the one surface of the substrate has at least one coil forming region in which the coil is formed.
  • the insulating film is disposed so as to surround the coil, and regions located inside and outside the coil in the coil forming region of the substrate are It is exposed from the insulating film.
  • a portion of the one surface of the substrate exposed from the insulating film can relieve stress generated between the insulating film covering the coil and the substrate, and the substrate is warped. This can be suppressed.
  • FIG. 4A is a plan view showing a fourth wiring layer when viewed from the normal direction to one surface of the circuit board.
  • FIG. 4B is a plan view showing the fifth wiring layer when viewed from the normal direction to one surface of the circuit board.
  • FIG. 4C is a plan view showing the sixth wiring layer when viewed from the normal direction to one surface of the circuit board.
  • FIG. 5A is a cross-sectional view showing a part of the manufacturing process of the semiconductor device in the first embodiment.
  • FIG. 5B is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 5C is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment.
  • the semiconductor device has a configuration in which a coil 20 is disposed on one surface 10 a of a circuit board 10 and the coil 20 is covered with an insulating film 30.
  • the entire one surface 10a of the circuit board 10 is one coil formation region in the present disclosure.
  • the circuit board 10 corresponds to the board of the present disclosure.
  • the pads 11a to 11d are made of copper, gold, aluminum, or the like.
  • the pads 11a and 11b are connected to the coil 20, and the pads 11c and 11d are for connecting the circuit board 10 and an external circuit.
  • the pads 11a to 11d are provided point-symmetrically with respect to the center point of the circuit board 10 outside the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10.
  • the coil 20 is wound by appropriately connecting a plurality of first to sixth wiring layers 40 to 90 formed on the circuit board 10 with the normal direction to the one surface 10a of the circuit board 10 as an axis. It is said that.
  • the configuration of the first to sixth wiring layers 40 to 90 will be specifically described with reference to FIGS. 1, 3A to 3C, and 4A to 4C.
  • the circuit board 10 in FIG. 1 corresponds to a cross section taken along the line II in FIG.
  • the first to sixth wiring layers 40 to 90 in FIG. 1 correspond to the cross sections along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.
  • the first wiring layer 40 is formed closest to the circuit board 10 among the first to sixth wiring layers 40 to 90. 1 and 3A, the spiral first wiring portion 41 wound inwardly from the outside, and the circuit board 10 side from the outer end portion of the first wiring portion 41 And a first connection portion 42 that connects the end portion and the pad 11a. Moreover, it has the 1st drawer
  • the second wiring layer 50 is formed on the first wiring layer 40 via the insulating film 30 as shown in FIG. Then, as shown in FIGS. 1 and 3B, the spiral second wiring part 51 wound from the inside to the outside, and the circuit board 10 side from the inner end of the second wiring part 51 And a second connection portion 52 that connects this end portion to the inner end portion of the first wiring portion 41. Further, the second lead portion 53 is stacked on the first lead portion 43.
  • the first to fifth wiring portions 41 to 81 have the center point of the spiral structure and the center point of the circuit board 10 coincided when viewed from the normal direction to the one surface 10a of the circuit board 10. It is a pattern.
  • the sixth wiring layer 90 is formed on the fifth wiring layer 80 via the insulating film 30 as shown in FIGS. 1 and 4C. And it has the 6th wiring part 91 formed toward the 5th drawer
  • the insulating film 30 is disposed so as to surround only the periphery of the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10. That is, when viewed from the normal direction to the one surface 10 a of the circuit board 10, the inner and outer regions of the coil 20 are exposed from the insulating film 30 in the circuit board 10.
  • a substrate 12 on which various circuit elements are formed and four pads 11a to 11d electrically connected to the various circuit elements is prepared. Then, after an insulating film 13 is formed on one surface 12a of the substrate 12 by a CVD (Chemical Vapor Deposition) method or the like, contact holes 13a that expose the pads 11a to 11d are formed by etching using a mask (not shown). As a result, the circuit board 10 is formed.
  • CVD Chemical Vapor Deposition
  • an insulating paste containing a thixotropic polyimide, liquid glass, or the like is selectively pattern printed by a screen printing method using a mask (not shown) having a predetermined area opened.
  • a mask not shown
  • pattern printing is performed so that the insulating paste is disposed only around the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10.
  • the insulating paste is pattern-printed so that the pads 11a and 11b are also exposed.
  • the first interlayer insulating film 31 is configured by removing the resin component by performing thermal baking or the like.
  • a resin containing metal nanoparticles such as copper, powder, or a mixture thereof is used.
  • the second interlayer insulating film 32 is formed by performing the same process as the process of forming the first interlayer insulating film 31.
  • the second interlayer insulating film 32 is formed by selectively pattern-printing an insulating paste on the first interlayer insulating film 31 by a screen printing method and then performing thermal baking or the like.
  • the second connection part 52 disposed in the contact hole 32a and connected to the first wiring part 41, the second wiring part 51 connected to the second connection part 52, the first A second wiring layer 50 having a second lead portion 53 connected to the lead portion 43 is formed.
  • the second wiring layer 50 is formed by performing the same process as the process of forming the first wiring layer 40. That is, pattern printing is performed by screen printing so that the conductive paste has the pattern of FIG. 3B and is embedded in the contact hole 32a. And the 2nd wiring layer 50 which has the 2nd wiring part 51, the 2nd connection part 52, and the 2nd drawer
  • FIG. 6A Thereafter, as shown in FIG. 6A, the same steps as in FIGS. 5D and 5E were repeated to form the third interlayer insulating film 33, the third wiring layer 60, and the contact holes 34a in which the contact holes 33a were formed.
  • a fourth interlayer insulating film 34 and a fourth wiring layer 70 are formed.
  • a fifth interlayer insulating film 35 in which the contact hole 35a is formed, a fifth wiring layer 80, and a sixth interlayer insulating film 36 in which the contact hole 36a is formed are formed.
  • the inside of the coil 20 is an air layer. For this reason, the parasitic capacitance generated in the coil 20 can be reduced, and the self-resonance frequency can be increased.
  • the first to seventh interlayer insulating films 31 to 37 are pattern printed. Therefore, compared with the case where the semiconductor device is manufactured by forming the insulating film on the entire surface 10a of the circuit board 10 and then partially removing the insulating film, the circuit board 10 and the circuit board 10 It is possible to suppress the circuit board 10 from being warped by the stress generated between the first to seventh interlayer insulating films 31 to 37.
  • one surface 10a of the circuit board 10 may be divided into a plurality of coil forming regions.
  • the inner and outer portions of the coil 20 of the circuit board 10 are exposed from the insulating film 30. The same effect as the form can be obtained.
  • the regions located inside and outside the coil 20 when viewed from the normal direction to the one surface 10 a of the circuit board 10.
  • a magnetic layer 100 of nickel, manganese zinc, ferrite, or the like is disposed.
  • the magnetic layer 100 is disposed such that a predetermined gap is formed between the magnetic layer 100 and the insulating film 30 covering the coil 20.
  • the magnetic layer 100 is disposed inside and outside the coil 20, the same effect as the first embodiment can be obtained while improving the inductance of the coil 20.
  • the magnetic layer 100 is arranged so that a predetermined gap is formed between the magnetic layer 100 and the insulating film 30 covering the coil 20. For this reason, it can suppress that a stress generate
  • a magnetic layer 100 in which magnetic films 100a and insulating layers 100b are alternately stacked may be used. According to this, generation
  • the insulating layer 100b is formed by baking an insulating paste containing polyimide, liquid glass, or the like, as with the insulating film 30 (first to seventh interlayer insulating films 31 to 37), for example.
  • the circuit board 10 and the magnetic layer 100 in FIG. 9 correspond to a cross section taken along line VII-VII in FIG.
  • the first to sixth wiring layers 40 to 90 in FIG. 9 correspond to the cross section taken along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.
  • FIG. 1 A third embodiment of the present disclosure will be described. This embodiment is different from the second embodiment in that the magnetic layer 100 is disposed on the opposite side of the coil 20 to the circuit board 10 side, and the rest is the same as the second embodiment. The description is omitted here.
  • the magnetic layer 100 is also disposed on the opposite side of the coil 20 to the circuit board 10 side through the insulating film 30. Specifically, the magnetic layer 100 is also disposed on the fifth and sixth wiring portions 81 and 91 via the insulating film 30.
  • the magnetic layer 100 is also arranged on the side (upper side) of the coil 20 opposite to the circuit board 10 side. For this reason, the effect similar to the said 2nd Embodiment can be acquired, improving the inductance of the coil 20 further. Further, it is possible to suppress the magnetic flux generated from the coil 20 from leaking to the outside, or the magnetic flux from the outside from entering the coil 20.
  • the magnetic layer 100 is disposed on the fifth and sixth wiring portions 81 and 91 with the insulating film 30 interposed therebetween, but the first to sixth lead portions 43 to The magnetic layer 100 may be disposed so that 93 is covered. That is, the entire coil 20 may be completely covered with the magnetic layer 100.
  • a protective film 110 of about 10 to 50 ⁇ m is disposed on one surface 10a of the circuit board 10.
  • the protective film 110 is formed in at least a region located inside the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10.
  • the circuit board 10 is formed with a concave portion 14 on the other surface opposite to the one surface 10a, thereby forming a diaphragm 15 that becomes a thin portion on the one surface 10a side. ing.
  • the diaphragm 15 is formed with a gauge resistance (not shown) whose resistance value changes in accordance with the pressure applied to the diaphragm.
  • the circuit board 10 is formed with a sensing unit 16 that outputs a sensor signal corresponding to the pressure applied to the diaphragm 15.
  • the present disclosure can also be applied to a semiconductor device in which the coil 20 is arranged on the circuit board 10 on which the sensing unit 16 for detecting pressure is formed.
  • the coil 20 and the insulating film 30 are formed so as to surround the diaphragm 15 when viewed from the normal direction to the one surface 10 a of the circuit board 10. For this reason, compared with the case where the coil 20 and the insulating film 30 are formed on the diaphragm 15, it can suppress that the stress from the coil 20 and the insulating film 30 is applied to the diaphragm 15. FIG. Therefore, it is possible to obtain the same effect as that of the first embodiment while suppressing a decrease in pressure detection accuracy.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un dispositif à semi-conducteurs qui comporte un substrat (10) qui possède une surface (10a), une bobine (20) qui est formée sur la surface susmentionnée du substrat et qui est enroulée de telle sorte que la ligne normale par rapport à la surface susmentionnée du substrat fonctionne en tant qu'axe, et un film isolant (30) qui recouvre la bobine. La surface susmentionnée du substrat possède au moins une région de formation de bobine dans laquelle la bobine est formée. Lors d'une visualisation depuis la direction de ligne normale par rapport à la surface susmentionnée du substrat, le film d'isolation est disposé afin d'entourer la bobine, et une région située à l'intérieur et à l'extérieur de la bobine sur la région de formation de bobine sur le substrat est mise à nu depuis le film d'isolation.
PCT/JP2014/006031 2013-12-12 2014-12-03 Dispositif à semi-conducteurs et son procédé de fabrication WO2015087511A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013257285A JP6191434B2 (ja) 2013-12-12 2013-12-12 半導体装置およびその製造方法
JP2013-257285 2013-12-12

Publications (1)

Publication Number Publication Date
WO2015087511A1 true WO2015087511A1 (fr) 2015-06-18

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PCT/JP2014/006031 WO2015087511A1 (fr) 2013-12-12 2014-12-03 Dispositif à semi-conducteurs et son procédé de fabrication

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WO (1) WO2015087511A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6500720B2 (ja) * 2015-09-15 2019-04-17 株式会社デンソー 電子装置、および電子装置の製造方法
JP7345251B2 (ja) * 2018-12-27 2023-09-15 新科實業有限公司 薄膜インダクタ、コイル部品および薄膜インダクタの製造方法
JP7345253B2 (ja) * 2018-12-28 2023-09-15 新科實業有限公司 薄膜インダクタ、コイル部品および薄膜インダクタの製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1074626A (ja) * 1996-06-27 1998-03-17 Kiyoto Yamazawa 薄型磁気素子およびその製造方法とトランス
JP2003304047A (ja) * 2002-04-08 2003-10-24 Sumitomo Electric Ind Ltd 薄型配線体および配線形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1074626A (ja) * 1996-06-27 1998-03-17 Kiyoto Yamazawa 薄型磁気素子およびその製造方法とトランス
JP2003304047A (ja) * 2002-04-08 2003-10-24 Sumitomo Electric Ind Ltd 薄型配線体および配線形成方法

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JP6191434B2 (ja) 2017-09-06
JP2015115498A (ja) 2015-06-22

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