WO2015087511A1

WO2015087511A1 - Semiconductor device, and method for producing same

Info

Publication number: WO2015087511A1
Application number: PCT/JP2014/006031
Authority: WO
Inventors: 吉原　晋二; 北村　康宏
Original assignee: 株式会社デンソー
Priority date: 2013-12-12
Filing date: 2014-12-03
Publication date: 2015-06-18
Also published as: JP6191434B2; JP2015115498A

Abstract

A semiconductor device is provided with a substrate (10) which has a surface (10a), a coil (20) which is formed on the aforementioned surface of the substrate and which is wound so that the direction of a normal line of the aforementioned surface of the substrate functions as the axis, and an insulating film (30) which covers the coil. The aforementioned surface of the substrate has at least one coil formation region in which the coil is formed. When viewed from the direction of the normal line of the aforementioned surface of the substrate, the insulating film is disposed so as to surround the coil, and a region located inside and outside of the coil on the coil formation region on the substrate is exposed from the insulating film.

Description

Semiconductor device and manufacturing method thereof

Cross-reference of related applications

This disclosure is based on Japanese Patent Application No. 2013-257285 filed on December 12, 2013, the contents of which are incorporated herein.

The present disclosure relates to a semiconductor device in which a coil is disposed on one side of a substrate and a manufacturing method thereof.

Conventionally, as this type of semiconductor device, for example, Patent Document 1 has proposed the following.

That is, in this semiconductor device, a plurality of wiring portions and insulating films are alternately stacked on one surface side of the substrate in the normal direction to the one surface. Then, the wiring layers of the respective layers are appropriately connected through contact holes formed in the insulating films of the respective layers, so that a coil wound around the normal direction with respect to one surface of the substrate is configured.

In this semiconductor device, a plurality of such coils are arranged in the surface direction of the substrate. That is, in this semiconductor device, it can be said that the substrate has a plurality of coil forming regions, and the coils are arranged on the respective coil forming regions.

And the recessed part is formed in the part located between each coil among insulating films from the part on the opposite side to a board | substrate side. This recess does not reach one surface of the substrate, and the portion of the insulating film on the substrate side is not separated.

According to this, the thermal stress caused by the difference in thermal expansion coefficient between the insulating film and the substrate can be relieved by the concave portion, and the warpage of the substrate can be suppressed.

However, in such a semiconductor device, although the thermal stress can be relieved in the recess, the recess does not reach one surface of the substrate, so that one surface of the substrate is covered with an insulating film that covers the coil. For this reason, there exists a problem that a board | substrate may warp by the thermal stress resulting from the difference in the thermal expansion coefficient of this insulating film and a board | substrate.

JP-A-7-263863

In view of the above points, in the present disclosure, in a semiconductor device in which a coil is disposed on one surface side of a substrate, the semiconductor device capable of suppressing the substrate from being warped by stress generated between the insulating film covering the coil and the substrate, and the semiconductor device An object is to provide a manufacturing method.

A semiconductor device according to one embodiment of the present disclosure covers a substrate having one surface, a coil formed on the one surface side of the substrate, and wound around a normal direction to the one surface of the substrate, and the coil And an insulating film. The one surface of the substrate has at least one coil forming region in which the coil is formed. When viewed from the normal direction with respect to the one surface of the substrate, the insulating film is disposed so as to surround the coil, and regions located inside and outside the coil in the coil forming region of the substrate are It is exposed from the insulating film.

According to the semiconductor device, a portion of the one surface of the substrate exposed from the insulating film can relieve stress generated between the insulating film covering the coil and the substrate, and the substrate is warped. This can be suppressed.

A manufacturing method according to a second aspect of the present disclosure is a manufacturing method of a semiconductor device according to the first aspect, and one layer when the coil is divided into a plurality along a direction parallel to the one surface of the substrate. And forming an interlayer insulating film constituting one layer when the insulating film is divided into a plurality along the direction parallel to the one surface of the substrate. . By alternately and repeatedly forming the wiring layer and forming the interlayer insulating film, the coil is constituted by a plurality of wiring layers, and the insulating film is constituted by a plurality of interlayer insulating films. To do. The interlayer insulating film is formed by selectively forming the interlayer insulating film so as to surround only the coil when viewed from the normal direction to the one surface of the substrate when the coil is formed. including.

According to the manufacturing method, compared with the case of manufacturing a semiconductor device by forming an insulating film on the entire surface of the substrate and then partially removing the insulating film, the substrate and the interlayer insulation are manufactured during the manufacturing process. The substrate can be prevented from warping due to stress generated between the film (insulating film).

The above and other objects, configurations, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the following drawings. In the drawing
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 when viewed from the normal direction to one surface of the circuit board. FIG. 3A is a plan view showing the first wiring layer when viewed from the normal direction to one surface of the circuit board. FIG. 3B is a plan view showing the second wiring layer when viewed from the normal direction to one surface of the circuit board. FIG. 3C is a plan view showing the third wiring layer when viewed from the normal direction to one surface of the circuit board. FIG. 4A is a plan view showing a fourth wiring layer when viewed from the normal direction to one surface of the circuit board. FIG. 4B is a plan view showing the fifth wiring layer when viewed from the normal direction to one surface of the circuit board. FIG. 4C is a plan view showing the sixth wiring layer when viewed from the normal direction to one surface of the circuit board. FIG. 5A is a cross-sectional view showing a part of the manufacturing process of the semiconductor device in the first embodiment. FIG. 5B is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5C is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5D is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5E is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6A is a cross-sectional view showing a part of the manufacturing process of the semiconductor device in the first embodiment. FIG. 6B is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6C is a cross-sectional view illustrating a part of the manufacturing process of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view of the semiconductor device according to the second embodiment of the present disclosure. FIG. 8 is a plan view of the semiconductor device shown in FIG. 7 when viewed from the normal direction to one surface of the circuit board. FIG. 9 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment of the present disclosure. FIG. 10 is a cross-sectional view of the semiconductor device according to the third embodiment of the present disclosure. FIG. 11 is a cross-sectional view of a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 12 is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present disclosure will be described with reference to the drawings. As shown in FIG. 1, the semiconductor device has a configuration in which a coil 20 is disposed on one surface 10 a of a circuit board 10 and the coil 20 is covered with an insulating film 30.

In the present embodiment, an example in which one coil 20 is arranged on the circuit board 10 will be described. That is, in the present embodiment, the entire one surface 10a of the circuit board 10 is one coil formation region in the present disclosure. In the present embodiment, the circuit board 10 corresponds to the board of the present disclosure.

The circuit board 10 has a rectangular plate shape, and various circuit elements are formed, and four pads 11a to 11d electrically connected to the various circuit elements through aluminum wiring or the like are formed. The substrate 12 is provided. An insulating film 13 in which contact holes 13a for exposing the pads 11a to 11d are formed is disposed on one surface 12a of the substrate 12. That is, in the present embodiment, the one surface 10 a of the circuit board 10 is configured by the insulating film 13.

In the present embodiment, the pads 11a to 11d are made of copper, gold, aluminum, or the like. The

pads

11a and 11b are connected to the coil 20, and the

pads

11c and 11d are for connecting the circuit board 10 and an external circuit. The pads 11a to 11d are provided point-symmetrically with respect to the center point of the circuit board 10 outside the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10.

The coil 20 is wound by appropriately connecting a plurality of first to sixth wiring layers 40 to 90 formed on the circuit board 10 with the normal direction to the one surface 10a of the circuit board 10 as an axis. It is said that. Hereinafter, the configuration of the first to sixth wiring layers 40 to 90 will be specifically described with reference to FIGS. 1, 3A to 3C, and 4A to 4C. The circuit board 10 in FIG. 1 corresponds to a cross section taken along the line II in FIG. Further, the first to sixth wiring layers 40 to 90 in FIG. 1 correspond to the cross sections along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.

As shown in FIG. 1, the first wiring layer 40 is formed closest to the circuit board 10 among the first to sixth wiring layers 40 to 90. 1 and 3A, the spiral first wiring portion 41 wound inwardly from the outside, and the circuit board 10 side from the outer end portion of the first wiring portion 41 And a first connection portion 42 that connects the end portion and the pad 11a. Moreover, it has the 1st drawer | drawing-out part 43 formed on the pad 11b and connected with the said pad 11b.

The second wiring layer 50 is formed on the first wiring layer 40 via the insulating film 30 as shown in FIG. Then, as shown in FIGS. 1 and 3B, the spiral second wiring part 51 wound from the inside to the outside, and the circuit board 10 side from the inner end of the second wiring part 51 And a second connection portion 52 that connects this end portion to the inner end portion of the first wiring portion 41. Further, the second lead portion 53 is stacked on the first lead portion 43.

The third to fifth wiring layers 60 to 80 are sequentially formed on the second wiring layer 50 via the insulating film 30. As shown in FIGS. 1, 3C, 4A, and 4B, the configuration is basically the same as that of the second wiring layer 50. That is, the third to fifth wiring portions 61 to 81 each having a spiral shape are connected to one end of the third to fifth wiring portions 61 to 81 and one end of the lower wiring portion. To fifth connecting portions 62 to 82. Further, third to fifth lead portions 63 to 83 are sequentially stacked on the second lead portion 53.

In the present embodiment, the first to fifth wiring portions 41 to 81 have the center point of the spiral structure and the center point of the circuit board 10 coincided when viewed from the normal direction to the one surface 10a of the circuit board 10. It is a pattern.

The sixth wiring layer 90 is formed on the fifth wiring layer 80 via the insulating film 30 as shown in FIGS. 1 and 4C. And it has the 6th wiring part 91 formed toward the 5th drawer | drawing-out part 83 from the edge part inside the 5th wiring part 81. As shown in FIG. Further, a sixth connection portion 92 that protrudes from the inner end portion of the sixth wiring portion 91 toward the circuit board 10 and connects this end portion to the outer end portion of the fifth wiring portion 81, and a fifth drawer And a sixth lead portion 93 that is stacked on the portion 83 and connected to the sixth wiring portion 91.

In this embodiment, in this way, the first connection part 42, the first wiring part 41, the second connection part 52, the second wiring part 51, the third connection part 62, the third wiring part 61, the fourth connection part. 72, the fourth wiring portion 71, the fifth connection portion 82, the fifth wiring portion 81, the sixth connection portion 92, the sixth wiring portion 91, and the sixth to first lead portions 93 to 43 are connected in order. 20 is configured. Therefore, for example, when an input current is applied to the pad 11a, the first connection part 42, the first wiring part 41, the second connection part 52, the second wiring part 51, the third connection part 62, and the third wiring part. 61, the fourth connection portion 72, the fourth wiring portion 71, the fifth connection portion 82, the fifth wiring portion 81, the sixth connection portion 92, and the sixth wiring portion 91 in this order, A current flows to the pad 11b through the lead portions 93 to 43.

The insulating film 30 is disposed so as to surround only the periphery of the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10. That is, when viewed from the normal direction to the one surface 10 a of the circuit board 10, the inner and outer regions of the coil 20 are exposed from the insulating film 30 in the circuit board 10.

As described above, the insulating film 30 is also disposed between the first to sixth wiring layers 40 to 90 (first to sixth wiring portions 41 to 91). That is, the first to sixth wiring parts 41 to 91 are secured by the insulating film 30.

The above is the configuration of the semiconductor device in this embodiment. Next, a method for manufacturing such a semiconductor device will be described with reference to FIGS. 5A to 5E and FIGS. 6A to 6C.

First, as shown in FIG. 5A, a substrate 12 on which various circuit elements are formed and four pads 11a to 11d electrically connected to the various circuit elements is prepared. Then, after an insulating film 13 is formed on one surface 12a of the substrate 12 by a CVD (Chemical Vapor Deposition) method or the like, contact holes 13a that expose the pads 11a to 11d are formed by etching using a mask (not shown). As a result, the circuit board 10 is formed.

Subsequently, as shown in FIG. 5B, a first interlayer insulating film 31 that forms part of the insulating film 30 and has contact holes 31a exposing the

pads

11a and 11b is formed on the circuit board 10. Form. In other words, the first interlayer insulating film 31 constituting one layer when the insulating film 30 is divided into a plurality of parts along the direction parallel to the one surface 10a of the circuit board 10 is formed.

Specifically, first, an insulating paste containing a thixotropic polyimide, liquid glass, or the like is selectively pattern printed by a screen printing method using a mask (not shown) having a predetermined area opened. At this time, when the coil 20 is formed, pattern printing is performed so that the insulating paste is disposed only around the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10. The insulating paste is pattern-printed so that the

pads

11a and 11b are also exposed.

Then, after pattern printing of the insulating paste, the first interlayer insulating film 31 is configured by removing the resin component by performing thermal baking or the like.

Next, as shown in FIG. 5C, the first connection part 42 connected to the pad 11a, the first wiring part 41 connected to the first connection part 42, and the first lead part 43 connected to the pad 11b are provided. A first wiring layer 40 is formed. In other words, the first wiring layer 40 constituting one layer when the coil 20 is divided into a plurality of parts along the direction parallel to the one surface 10a of the circuit board 10 is formed.

Specifically, first, a conductive paste is pattern-printed by a screen printing method using a mask (not shown) having a predetermined area opened. At this time, pattern printing is performed so that the conductive paste has the pattern of FIG. 3A and is also embedded in the contact hole 31a.

Then, after pattern printing of the conductive paste, thermal baking is performed in an oxygen atmosphere and a reducing atmosphere to remove the resin component and the oxide, thereby removing the first wiring portion 41, the first connection portion 42, and the first lead portion 43. A first wiring layer 40 is formed.

In addition, as the conductive paste, a resin containing metal nanoparticles such as copper, powder, or a mixture thereof is used.

Subsequently, as illustrated in FIG. 5D, the contact that covers the first wiring layer 40 on the first interlayer insulating film 31 and exposes the outer end portion of the first wiring portion 41 and the first lead portion 43. A second interlayer insulating film 32 in which the holes 32a are formed is formed.

The second interlayer insulating film 32 is formed by performing the same process as the process of forming the first interlayer insulating film 31. In other words, the second interlayer insulating film 32 is formed by selectively pattern-printing an insulating paste on the first interlayer insulating film 31 by a screen printing method and then performing thermal baking or the like.

Next, as shown in FIG. 5E, the second connection part 52 disposed in the contact hole 32a and connected to the first wiring part 41, the second wiring part 51 connected to the second connection part 52, the first A second wiring layer 50 having a second lead portion 53 connected to the lead portion 43 is formed.

The second wiring layer 50 is formed by performing the same process as the process of forming the first wiring layer 40. That is, pattern printing is performed by screen printing so that the conductive paste has the pattern of FIG. 3B and is embedded in the contact hole 32a. And the 2nd wiring layer 50 which has the 2nd wiring part 51, the 2nd connection part 52, and the 2nd drawer | drawing-out part 53 is formed by performing heat baking in oxygen atmosphere and reducing atmosphere.

Thereafter, as shown in FIG. 6A, the same steps as in FIGS. 5D and 5E were repeated to form the third interlayer insulating film 33, the third wiring layer 60, and the contact holes 34a in which the contact holes 33a were formed. A fourth interlayer insulating film 34 and a fourth wiring layer 70 are formed. Further, a fifth interlayer insulating film 35 in which the contact hole 35a is formed, a fifth wiring layer 80, and a sixth interlayer insulating film 36 in which the contact hole 36a is formed are formed.

Next, as shown in FIG. 6B, the same process as that in FIG. 5E is performed, and a sixth connection portion that is arranged in a contact hole 36a formed in a different cross section from that in FIG. 6B and is connected to the fifth wiring portion 81. 92, a sixth wiring part 91 connected to the sixth connection part 92, a sixth lead part 93 connected to the fifth wiring part 91 and connected to the fifth lead part 83. Thus, the coil 20 is constituted by the first to sixth wiring layers 40 to 90.

Thereafter, as shown in FIG. 6C, a seventh interlayer insulating film 37 covering the sixth wiring layer 90 is formed by performing the same process as in FIG. 5D. Thus, the insulating film 30 is constituted by the first to seventh interlayer insulating films 31 to 37, and the semiconductor device is manufactured.

As described above, in the semiconductor device of this embodiment, the insulating film 30 is arranged so as to surround the coil 20. When viewed from the normal direction to the one surface 10 a of the circuit board 10, the inner and outer regions of the coil 20 on the one surface 10 a of the circuit board 10 are exposed from the insulating film 30. For this reason, the stress that is generated between the insulating film 30 covering the coil 20 and the substrate 10 can be relieved by the portion of the one surface 10a of the circuit substrate 10 that is exposed from the insulating film 30, and the circuit substrate 10 is warped. Can be suppressed.

In the present embodiment, the inside of the coil 20 is an air layer. For this reason, the parasitic capacitance generated in the coil 20 can be reduced, and the self-resonance frequency can be increased.

Furthermore, when the semiconductor device is manufactured, the first to seventh interlayer insulating films 31 to 37 are pattern printed. Therefore, compared with the case where the semiconductor device is manufactured by forming the insulating film on the entire surface 10a of the circuit board 10 and then partially removing the insulating film, the circuit board 10 and the circuit board 10 It is possible to suppress the circuit board 10 from being warped by the stress generated between the first to seventh interlayer insulating films 31 to 37.

In the above, one surface 10a of the circuit board 10 may be divided into a plurality of coil forming regions. In this case, in each coil formation region, when viewed from the normal direction to the one surface 10a of the circuit board 10, the inner and outer portions of the coil 20 of the circuit board 10 are exposed from the insulating film 30. The same effect as the form can be obtained.

(Second Embodiment)
A second embodiment of the present disclosure will be described. In the present embodiment, a magnetic layer is arranged with respect to the first embodiment, and the other aspects are the same as those of the first embodiment, and thus the description thereof is omitted here.

As shown in FIG. 7 and FIG. 8, in this embodiment, the regions located inside and outside the coil 20 (the insulating film 30 covering the coil 20) when viewed from the normal direction to the one surface 10 a of the circuit board 10. Further, a magnetic layer 100 of nickel, manganese zinc, ferrite, or the like is disposed. In the present embodiment, the magnetic layer 100 is disposed such that a predetermined gap is formed between the magnetic layer 100 and the insulating film 30 covering the coil 20.

Note that the circuit board 10 and the magnetic layer 100 in FIG. 7 correspond to a cross section taken along line VII-VII in FIG. Further, the first to sixth wiring layers 40 to 90 in FIG. 7 correspond to the cross sections taken along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.

According to this, since the magnetic layer 100 is disposed inside and outside the coil 20, the same effect as the first embodiment can be obtained while improving the inductance of the coil 20.

In this embodiment, the magnetic layer 100 is arranged so that a predetermined gap is formed between the magnetic layer 100 and the insulating film 30 covering the coil 20. For this reason, it can suppress that a stress generate | occur | produces between the insulating film 30 which covers the coil 20, and the magnetic body layer 100, and can suppress that the circuit board 10 warps.

Here, an example in which a gap is formed between the insulating film 30 and the magnetic layer 100 has been described, but no gap is formed between the insulating film 30 and the magnetic layer 100. May be in close contact. Even in such a semiconductor device, the inductance of the coil 20 can be improved.

(Modification of the second embodiment)
In the second embodiment, as shown in FIG. 9, a magnetic layer 100 in which magnetic films 100a and insulating layers 100b are alternately stacked may be used. According to this, generation | occurrence | production of an eddy current in the magnetic body layer 100 by the insulating layer 100b can be reduced, and it can suppress that the characteristic of the coil 20 deteriorates.

Note that the insulating layer 100b is formed by baking an insulating paste containing polyimide, liquid glass, or the like, as with the insulating film 30 (first to seventh interlayer insulating films 31 to 37), for example. Further, the circuit board 10 and the magnetic layer 100 in FIG. 9 correspond to a cross section taken along line VII-VII in FIG. The first to sixth wiring layers 40 to 90 in FIG. 9 correspond to the cross section taken along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.

(Third embodiment)
A third embodiment of the present disclosure will be described. This embodiment is different from the second embodiment in that the magnetic layer 100 is disposed on the opposite side of the coil 20 to the circuit board 10 side, and the rest is the same as the second embodiment. The description is omitted here.

As shown in FIG. 10, in this embodiment, the magnetic layer 100 is also disposed on the opposite side of the coil 20 to the circuit board 10 side through the insulating film 30. Specifically, the magnetic layer 100 is also disposed on the fifth and

sixth wiring portions

81 and 91 via the insulating film 30.

This semiconductor device is manufactured by forming the magnetic layer 100 using a dispenser or the like after performing the steps of FIGS. 5A to 5E and FIGS. 6A to 6C. Further, the circuit board 10 in FIG. 10 corresponds to a cross section taken along line II in FIG. The first to sixth wiring layers 40 to 90 in FIG. 10 correspond to the cross section taken along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.

According to this, the magnetic layer 100 is also arranged on the side (upper side) of the coil 20 opposite to the circuit board 10 side. For this reason, the effect similar to the said 2nd Embodiment can be acquired, improving the inductance of the coil 20 further. Further, it is possible to suppress the magnetic flux generated from the coil 20 from leaking to the outside, or the magnetic flux from the outside from entering the coil 20.

10 shows that the magnetic layer 100 is disposed on the fifth and

sixth wiring portions

81 and 91 with the insulating film 30 interposed therebetween, but the first to sixth lead portions 43 to The magnetic layer 100 may be disposed so that 93 is covered. That is, the entire coil 20 may be completely covered with the magnetic layer 100.

(Fourth embodiment)
A fourth embodiment of the present disclosure will be described. In the present embodiment, a protective film is disposed on one surface 10a of the circuit board 10 with respect to the first embodiment, and the others are the same as those in the first embodiment, and thus the description thereof is omitted here.

As shown in FIG. 11, in this embodiment, a protective film 110 of about 10 to 50 μm is disposed on one surface 10a of the circuit board 10. Specifically, the protective film 110 is formed in at least a region located inside the coil 20 when viewed from the normal direction to the one surface 10a of the circuit board 10.

The protective film 110 is formed of, for example, an oxide film that is formed by a CVD method or the like and then densified by heat treatment or the like. Further, the circuit board 10 in FIG. 11 corresponds to a cross section taken along the line II in FIG. The first to sixth wiring layers 40 to 90 in FIG. 11 correspond to the cross section taken along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.

According to this, it is possible to suppress the magnetic flux generated in the coil 20 from penetrating the circuit board 10 and to suppress the generation of eddy current in the circuit board 10. For this reason, the effect similar to the said 1st Embodiment can be acquired, suppressing that the circuit board 10 malfunctions.

(Fifth embodiment)
A fifth embodiment of the present disclosure will be described. In the present embodiment, the configuration of the circuit board 10 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment, and thus the description thereof is omitted here.

As shown in FIG. 12, in the present embodiment, the circuit board 10 is formed with a concave portion 14 on the other surface opposite to the one surface 10a, thereby forming a diaphragm 15 that becomes a thin portion on the one surface 10a side. ing. The diaphragm 15 is formed with a gauge resistance (not shown) whose resistance value changes in accordance with the pressure applied to the diaphragm. In other words, the circuit board 10 is formed with a sensing unit 16 that outputs a sensor signal corresponding to the pressure applied to the diaphragm 15.

The coil 20 and the insulating film 30 are formed so as to surround the diaphragm 15 when viewed from the normal direction to the one surface 10 a of the circuit board 10. In other words, the coil 20 and the insulating film 30 are formed so that the diaphragm 15 is exposed from the coil 20 and the insulating film 30.

Note that the circuit board 10 in FIG. 12 corresponds to a cross section taken along line II in FIG. Further, the first to sixth wiring layers 40 to 90 in FIG. 12 correspond to the cross sections taken along the line II in FIGS. 3A to 3C and FIGS. 4A to 4C.

As described above, the present disclosure can also be applied to a semiconductor device in which the coil 20 is arranged on the circuit board 10 on which the sensing unit 16 for detecting pressure is formed. In the present embodiment, the coil 20 and the insulating film 30 are formed so as to surround the diaphragm 15 when viewed from the normal direction to the one surface 10 a of the circuit board 10. For this reason, compared with the case where the coil 20 and the insulating film 30 are formed on the diaphragm 15, it can suppress that the stress from the coil 20 and the insulating film 30 is applied to the diaphragm 15. FIG. Therefore, it is possible to obtain the same effect as that of the first embodiment while suppressing a decrease in pressure detection accuracy.

(Other embodiments)
The present disclosure is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims.

For example, in each of the above embodiments, the first to sixth wiring layers 40 to 90 may be formed by plating.

In the fourth embodiment, the protective film 110 may be made of a magnetic material.

Furthermore, the above embodiments can be combined as appropriate. For example, the modification of the second embodiment may be combined with the third embodiment, and the magnetic layer 100 may be formed by alternately laminating the magnetic film 100a and the insulating layer 100b. In addition, the semiconductor device having the magnetic layer 100 and the protective film 110 can be formed by combining the second and third embodiments with the fourth embodiment.

Claims

A substrate (10) having one surface (10a);
A coil (20) formed on the one surface side of the substrate and wound around a normal direction to the one surface of the substrate;
A semiconductor device comprising an insulating film (30) covering the coil,
The one surface of the substrate has at least one coil forming region in which the coil is formed,
When viewed from the normal direction with respect to the one surface of the substrate, the insulating film is disposed so as to surround the coil, and regions located inside and outside the coil in the coil forming region of the substrate are A semiconductor device exposed from an insulating film.
A magnetic layer (100);
The said magnetic body layer is arrange | positioned in the area | region located inside and outside of the said coil of the said coil formation area | region in the said board | substrate when it sees from the said normal line direction with respect to the said one surface of the said board | substrate. Semiconductor device.
3. The semiconductor device according to claim 2, wherein the magnetic layer includes a magnetic film (100a) and an insulating layer (100b) alternately stacked in the normal direction with respect to the one surface of the substrate.
4. The semiconductor device according to claim 2, wherein the magnetic layer is disposed on the opposite side of the coil from the substrate side via the insulating film.
A protective film (110) formed on the one surface of the substrate;
The said protective film is formed in the area | region located inside the said coil among the said coil formation area | regions in the said board | substrate when it sees from the said normal line direction with respect to the said one surface of the said board | substrate. The semiconductor device as described in any one.
The substrate includes a diaphragm (15) formed on the one surface side, and a sensing unit (16) that outputs a sensor signal corresponding to a pressure applied to the diaphragm,
The semiconductor device according to claim 1, wherein the coil and the insulating film are formed so as to surround the diaphragm when viewed from the normal direction with respect to the one surface of the substrate.
In the manufacturing method of the semiconductor device according to any one of claims 1 to 6,
Forming a wiring layer (40 to 90) constituting one layer when the coil is divided into a plurality along the direction parallel to the one surface of the substrate;
Forming an interlayer insulating film (31 to 37) constituting one layer when the insulating film is divided into a plurality of parts along a direction parallel to one surface of the substrate,
By alternately and repeatedly forming the wiring layer and forming the interlayer insulating film, the coil is constituted by a plurality of wiring layers, and the insulating film is constituted by a plurality of interlayer insulating films. And
The interlayer insulating film is formed by selectively forming the interlayer insulating film so as to surround only the coil when viewed from the normal direction to the one surface of the substrate when the coil is formed. A method of manufacturing a semiconductor device including:
Forming the interlayer insulating film includes pattern-printing an insulating paste using a mask having a predetermined area opened, and firing the insulating paste,
The method of manufacturing a semiconductor device according to claim 7, wherein forming the wiring layer includes pattern-printing a conductive paste using a mask having an opening in a predetermined region, and baking the conductive paste.