JP6500720B2 - Electronic device and method of manufacturing electronic device - Google Patents

Description

  The present invention relates to an electronic device and a method of manufacturing the electronic device.

  Heretofore, there has been proposed a capacitor having a laminated body in which dielectric layers and dummy electrodes are alternately laminated (see, for example, Patent Document 1).

  The laminate improves the toughness of the surface layer portion of the capacitor by exposing the surface layer portion of the capacitor. For this reason, even if external stress is applied to the surface layer portion of the capacitor, the occurrence of cracks in the surface layer portion of the capacitor can be prevented.

JP, 2008-283166, A

  The present inventor examined forming a coil structure by laminating a wiring layer and an insulating layer on a semiconductor substrate with reference to the capacitor described in Patent Document 1 above.

  In order to form the wiring layer (or insulating layer), a conductive paste (or insulating paste) is pattern printed on the semiconductor substrate by a screen printing method or the like.

  Firing to raise the temperature of the conductive paste (or insulating paste) to at least about 200 ° C. to 300 ° C. in order to remove the binder contained in the pattern-printed conductive paste (or insulating paste) Heat treatment such as is required.

  Here, in the case where a plurality of wiring layers (or insulating layers) are stacked on a semiconductor substrate, conductive paste (or insulating paste) is repeatedly pattern-printed, and the pattern-printed conductivity is printed every printing. Paste (or insulating paste) is fired.

  For example, when firing a pattern printed insulating paste to form a certain insulating layer among a plurality of wiring layers, a large amount of the wiring layer and the insulating layer formed before the firing may be produced by the firing. The temperature of the wiring layer and the insulating layer rises.

  Here, the thermal expansion coefficient of the wiring layer is smaller than the thermal expansion coefficient of the insulating layer, and the difference between the thermal expansion coefficient of the wiring layer and the thermal expansion coefficient of the insulating layer is large. Therefore, stress due to the difference between the thermal expansion coefficient of the wiring layer and the thermal expansion coefficient of the insulating layer may be applied to the wiring layer to cause a crack in the wiring layer.

  In particular, if four or more wiring layers are formed on the semiconductor substrate, the thickness dimension of the insulating layer formed around the wiring layer will approach the thickness dimension of the semiconductor substrate, and thus the wiring layer etc. is cracked. The probability of occurrence of

  As a specific example, in a transformer in which two first and second coils, each consisting of four wiring layers, are arranged on the semiconductor substrate in the thickness direction, a large current of several A may be supplied depending on the application, or In order to reduce circuit loss, the thickness of the wiring layer may be increased to 10 μm to 20 μm to increase the cross-sectional area of the wiring layer.

  Furthermore, in order to ensure the withstand voltage between the first and second coils, the distance between the first and second coils needs to be larger than the distance between the two layers of wires.

  Therefore, the thickness of the entire transformer is about 200 μm. In this case, when the thickness of the semiconductor substrate is 400 μm, the thickness of the transformer portion is half the thickness dimension of the semiconductor substrate. For this reason, when the temperature of the wiring layer or the insulating layer rises due to heat treatment such as baking, excessive stress from the insulating layer is applied to the wiring layer.

  In particular, in the lead-out wiring that connects the first coil (or the second coil) and the electrode pad, the wiring may be provided immediately above the resin-based insulating layer having a large thickness dimension.

  In this case, since the insulating layer expands due to firing, the lead-out wiring is pushed up by the insulating layer, so that stress is applied to the lead-out wiring and a crack is generated in the lead-out wiring.

  In view of the above-described points, the present invention has an object of providing an electronic device in which a crack is prevented from being generated in a lead-out wire and an electronic device manufacturing method in an electronic device formed by forming a coil on a substrate. .

In order to achieve the above object, in the invention according to claim 1, a substrate (10) having one surface (10a);
A coil (21, 22) formed on one side of the substrate and wound with the normal to the one side as a center line;
A first electrode pad and a second electrode pad (13 to 16) formed on one side of the substrate;
A first lead-out wire (25) formed on one side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
In an electronic device provided with a second lead-out wire (24, 26) formed on one surface side of a substrate and connecting between a second electrode (20b, 20d) and a second electrode pad (14, 16) of a coil ,
A plurality of lead wiring layers (24a to 24d, 25a, each of which is made of a conductive material and is stacked in the normal direction of one surface of the substrate) of the first lead wiring and the second lead wiring. To 25e, 26a to 26g),
Dummy wirings (30a to 30c, 31a to 31d, 32a to 32e) which are disposed between one lead wiring and the substrate and made of a conductive material;
A plurality of insulating layers (40a to 40h) which are disposed between one lead wire and the substrate, and which are each formed of a sintered body of an electrically insulating material and laminated in the normal direction of one surface of the substrate And an insulating film (40),
A material constituting the dummy wiring is characterized by being the same material as a material constituting one of the lead wirings.

  According to the first aspect of the present invention, the dummy wiring is disposed on the substrate side with respect to the one lead wiring. For this reason, the volume of the insulating film disposed on the substrate side with respect to one of the lead wires can be reduced. In addition to this, the material constituting the dummy wiring is the same material as the material constituting one lead wiring. Therefore, it is possible to reduce the stress given from the insulating film to one lead wiring due to the difference between the thermal expansion coefficient of the material constituting one lead wiring and the thermal expansion coefficient of the material constituting the insulating film. it can. This can suppress the occurrence of cracks in the lead-out wiring.

  However, in the present specification, the fired body of the conductive material is a fired product of the conductive material. The fired body of the electrically insulating material is obtained by firing the electrically insulating material.

In the invention according to claim 2, a substrate (10) having one surface (10a);
A coil (21, 22) formed on one side of the substrate and wound with the normal to the one side as a center line;
A first electrode pad and a second electrode pad (13 to 16) formed on one side of the substrate;
A first lead-out wire (25) formed on one side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
In an electronic device provided with a second lead-out wire (24, 26) formed on one surface side of a substrate and connecting between a second electrode (20b, 20d) and a second electrode pad (14, 16) of a coil ,
A plurality of lead wiring layers (24a to 24d, 25a, each of which is made of a conductive material and is stacked in the normal direction of one surface of the substrate) of the first lead wiring and the second lead wiring. To 25e, 26a to 26g),
Dummy wirings (30a to 30c, 31a to 31d, 32a to 32e) which are disposed between one lead wiring and the substrate and made of a conductive material;
A plurality of insulating layers (40a to 40h) which are disposed between one lead wire and the substrate, and which are each formed of a sintered body of an electrically insulating material and laminated in the normal direction of one surface of the substrate And an insulating film (40),
The material forming the dummy wiring is characterized in that the material is smaller than the thermal expansion coefficient of the insulating layer.

  According to the second aspect of the present invention, the dummy wiring is disposed on the substrate side with respect to the one lead wiring. For this reason, the volume of the insulating film disposed on the substrate side with respect to one of the lead wires can be reduced. In addition to this, the material forming the dummy wiring is a material smaller than the thermal expansion coefficient of the insulating layer. Therefore, it is possible to reduce the stress given from the insulating film to one lead wiring due to the difference between the thermal expansion coefficient of the material constituting one lead wiring and the thermal expansion coefficient of the material constituting the insulating film. it can. This can suppress the occurrence of cracks in the lead-out wiring.

In the invention according to claim 15, a substrate (10) having a surface (10a);
A coil (21, 22) formed on one side of the substrate and wound with the normal to the one side as a center line;
A first electrode pad and a second electrode pad (13 to 16) disposed on one side of the substrate;
A first lead-out wire (25) formed on one side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
A second lead-out wire (24, 26) formed on one side of the substrate and connecting the second electrode (20b, 20d) of the coil and the second electrode pad (14, 16);
A plurality of dummy wirings (30a to 30c, 31a to 31c) which are disposed between the substrate and any one of the first and second lead wirings and the substrate and are stacked in the normal direction of one surface of the substrate. 31d, 32a-32e),
An insulating film (40) which is disposed between one lead wire and the substrate and is formed of a plurality of insulating layers (40a to 40h) stacked in the normal direction of one surface of the substrate;
One lead wire is composed of a plurality of lead wire layers (24a to 24d, 25a to 25e, 26a to 26g) stacked in the normal direction of one surface of the substrate,
A method of manufacturing an electronic device, wherein the same material as the material forming one lead wiring is used as the material forming the dummy wiring,
A plurality of dummy wires are stacked by repeatedly forming dummy wires on one side of the substrate,
A plurality of lead-out wiring layers are stacked by forming a lead-out wiring layer on one side in the normal direction with respect to the dummy wiring every time when the dummy wiring is formed on one side of the substrate,
Every time a dummy wiring or drawing wiring layer is formed, an electrically insulating paste is applied to one side in the normal direction to the dummy wiring or drawing wiring layer formed on one side of the substrate, and this coating is applied every time this application is performed. The electrically insulating paste is fired to form a plurality of insulating films.

  As described above, it is possible to provide a method of manufacturing an electronic device suitable for suppressing the occurrence of a crack in the lead-out wiring.

In the invention according to claim 16, a substrate (10) having a surface (10a);
A coil (21, 22) formed on one side of the substrate and wound with the normal to the one side as a center line;
A first electrode pad and a second electrode pad (13 to 16) disposed on one side of the substrate;
A first lead-out wire (25) formed on one side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
A second lead-out wire (24, 26) formed on one side of the substrate and connecting the second electrode (20b, 20d) of the coil and the second electrode pad (14, 16);
A plurality of dummy wirings (30a to 30c, 31a to 31c) which are disposed between the substrate and any one of the first and second lead wirings and the substrate and are stacked in the normal direction of one surface of the substrate. 31d, 32a-32e),
An insulating film (40) which is disposed between one lead wire and the substrate and is formed of a plurality of insulating layers (40a to 40h) stacked in the normal direction of one surface of the substrate;
One lead wire is composed of a plurality of lead wire layers (24a to 24d, 25a to 25e, 26a to 26g) stacked in the normal direction of one surface of the substrate,
A method of manufacturing an electronic device, wherein a material smaller than a thermal expansion coefficient of an insulating film is used as a material forming the dummy wiring,
A plurality of dummy wires are stacked by repeatedly forming dummy wires on one side of the substrate,
A plurality of lead-out wiring layers are stacked by forming a lead-out wiring layer on one side in the normal direction with respect to the dummy wiring every time when the dummy wiring is formed on one side of the substrate,
Every time a dummy wiring or drawing wiring layer is formed, an electrically insulating paste is applied to one side in the normal direction to the dummy wiring or drawing wiring layer formed on one side of the substrate, and this coating is applied every time this application is performed. The electrically insulating paste is fired to form a plurality of insulating films.

  As described above, it is possible to provide a method of manufacturing an electronic device suitable for suppressing the occurrence of a crack in the lead-out wiring.

  However, in the present specification, the width direction of the wiring (or wiring layer) is a direction parallel to one surface of the substrate and orthogonal to the longitudinal direction in which the wiring (or wiring layer) extends. The thickness direction is a direction parallel to the normal direction of one surface of the substrate in the wiring (or wiring layer).

  In addition, the code | symbol in the parenthesis of each means described by this column and the claim shows correspondence with the specific means as described in embodiment mentioned later.

It is a top view of the semiconductor device in a 1st embodiment of the present invention. It is II sectional drawing in FIG. 1A. It is a schematic diagram which shows the transformer of the semiconductor device in 1st Embodiment. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is the III-III sectional view in FIG. 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is IV-IV sectional drawing in FIG. 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is a V-V sectional view in Drawing 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is the VI-VI sectional view in FIG. 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is a VII-VII sectional view in Drawing 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is a VIII-VIII sectional view in Drawing 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is IX-IX sectional drawing in FIG. 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is XX sectional drawing in FIG. 1A. FIG. 7 is a top view showing a manufacturing process of the semiconductor device in the first embodiment. It is XI-XI sectional drawing in FIG. 1A. It is a schematic diagram which shows the relationship between the lead-out wiring in 1st Embodiment, and the direction of the electric current which flows into a coil. It is a schematic diagram which shows the relationship between the extraction wiring in a comparative example, and the direction of the electric current which flows into a coil. It is a top view of the lead-out wiring in a 1st embodiment. It is a side view of the lead-out wiring in a 1st embodiment. It is a side view of dummy wiring in a 1st embodiment. It is a side view of dummy wiring in a 1st embodiment. It is a top view of the dummy wiring in 1st Embodiment. It is a top view of the dummy wiring in 1st Embodiment. It is a side view of the semiconductor device in a comparative example. It is a side view of the lead-out wiring in a comparative example. It is a side view of the lead-out wiring in a comparative example. It is a top view of the semiconductor device in a 2nd embodiment of the present invention. It is a top view of the semiconductor device in a 3rd embodiment of the present invention. It is FIG. 16 XVI-XVI sectional drawing. It is a side view of the semiconductor device in a 4th embodiment of the present invention.

  Hereinafter, an embodiment of the present invention will be described based on the drawings. In the following embodiments, parts identical or equivalent to each other are denoted by the same reference numerals in the drawings in order to simplify the description.

First Embodiment
FIG. 1 shows a first embodiment of a semiconductor device 1 to which an electronic device according to the present invention is applied.

  The semiconductor device 1 of the present embodiment is a semiconductor device formed so as to cover the transformer 20 and the like formed on the one surface 10 a side of the circuit board 10 with the insulating film 40.

  The circuit substrate 10 is composed of a semiconductor substrate 11 such as a silicon substrate and an insulating layer 12 formed in a thin film on one surface side of the semiconductor substrate 11. The insulating layer 12 electrically insulates between the coils 21 and 22 and the semiconductor substrate 11. As the insulating layer 12, for example, a material excellent in electrical insulation and heat resistance, such as a nitride film or an oxide film can be used. On the opposite side of the semiconductor substrate 11 in the insulating layer 12, a surface a extending in the direction orthogonal to the thickness direction of the semiconductor substrate 11 is formed.

  Hereinafter, for convenience of explanation, one side in the normal direction orthogonal to one surface 10 a of the circuit board 10 is referred to as the upper side in FIG. 1, and the other side in the normal direction is referred to as the lower side in FIG. The circuit board 10 of the present embodiment corresponds to the substrate of the present invention, and one surface 10 a of the insulating layer 12 corresponds to one surface of the present invention.

  The transformer 20 is formed on one side in the normal direction to the circuit board 10.

  The transformer 20 is comprised of coils 21 and 22 as shown in FIG. One of the coils 21 and 22 constitutes a primary coil, and the other coil constitutes a secondary coil.

  The coils 21, 22 are spaced apart and arranged in the normal direction. The coils 21 and 22 are spirally wound with the normal line of the surface 10 a of the circuit board 10 as a common center line S. The coil 22 is located on one side of the coil 21 in the normal direction.

  The semiconductor device 1 includes electrode pads 13, 14, 15, 16. The electrode pads 13, 14, 15, 16 are formed on one surface 10a side of the circuit board 10, as shown in FIGS. 3A and 3B. The electrode pads 13, 14, 15, 16 are arranged in four directions on one surface 10 a of the circuit board 10. The electrode pads 13, 14, 15, 16 constitute electrodes relaying between the electrodes 20a, 20b of the coil 21, 20c, 20d of the coil 22 and other electronic circuits.

  The electrode pads 13, 14, 15, 16 of the present embodiment are made of copper, gold, aluminum or the like.

  The electrode pad 13 includes pads 13a and 13b and a connection portion 13c connecting the pads 13a and 13b. The electrode 13a of the electrode pad 13 and the electrode 20a of the coil 21 are connected by the lead-out wiring 23 (that is, the lead-out wiring layer 23a). The electrode 13b is connected to another electronic circuit.

  The electrode pad 14 includes pads 14 a and 14 b and a connection portion 14 c connecting the pads 14 a and 14 b. The pad 14 a of the electrode 14 and the electrode 20 b of the coil 21 are connected by the lead wire 24. The electrode 14b is connected to another electronic circuit.

  The electrode pad 15 includes pads 15 a and 15 b and a connection portion 15 c connecting the pads 15 a and 15 b. The pad 15 a of the electrode pad 15 and the electrode 20 c of the coil 22 are connected by the lead wire 25. The pad 15b is connected to another electronic circuit.

  The electrode pad 16 includes pads 16a and 16b and a connection portion 16c connecting the pads 16a and 16b. The pad 16 a 16 b and the electrode 20 d of the coil 22 are connected by the lead wire 26. The pad 16b is connected to another electronic circuit.

  The lead wirings 24, 25, 26 of the present embodiment are formed in a step shape as described later.

  Dummy wirings 30 a, 30 b, and 30 c are disposed between the lead wirings 24 and the circuit board 10. The dummy wires 30a, 30b, and 30c are not connected to the lead wire 24 and the coil 21 (and the coil 22).

  Dummy wirings 31 a, 31 b, 31 c, and 31 d are disposed between the lead-out wiring 25 and the substrate 10. The dummy wires 31 a, 31 b, 31 c, 31 d are not connected to the lead wire 25 and the coil 22 (and the coil 21).

  Dummy wirings 32 a, 32 b, 32 c, 32 d, 32 e, 32 f, 32 g are disposed between the lead-out wiring 26 and the substrate 10. The dummy wires 32a, 32b, 32c, 32d, 32e, 32f, 32g are not connected to the lead wire 26 and the coil 22 (and the coil 21).

  The details of the structure of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g according to this embodiment will be described later.

  The insulating film 40 is made of a material such as polyimide, which is excellent in electrical insulation and heat resistance. The insulating film 40 is formed between the lead wires 23 to 26 and the substrate 10 so as to surround the dummy wires 30 a to 30 c, 31 a to 31 d, and 32 a to 32 g.

  The thickness dimensions of the lead wirings 23 to 26 and the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g in the present embodiment are, for example, 20 μm.

  The above is the configuration of the semiconductor device 1 in the present embodiment. Next, a method of manufacturing such a semiconductor device 1 will be described.

  First, as shown in FIGS. 3A and 3B, a circuit board 10 is prepared in which electrode pads 13, 14, 15, 16 electrically connected to various circuit elements are formed on one surface 10a in a dispersed manner. Do.

  Next, the interlayer insulating layer 40a is formed along the direction parallel to the surface 10a of the circuit board 10 on one side normal to the electrode pads 13, 14, 15, 16.

  Specifically, first, a screen printing method using a mask (not shown) in which a predetermined region is opened is used to pattern-print an insulating paste which is an electrically insulating material including polyimide having thixotropy, liquid glass, and the like. Do. The pattern printing is performed so as to cover the insulating paste from one side in the normal direction of the electrode pads 13, 14, 15, 16. In the pattern printing, the electrodes 13b and 14b protrude from the insulating paste to the lower side in FIG. 3A, and the electrodes 15b and 16b protrude from the insulating paste to the upper side in FIG. 3A, and the electrodes 13a, 14a, 15a, and 16a are also formed. It is performed so as to be exposed to one side in the linear direction.

  After the insulating paste is pattern-printed in this manner, the resin component is removed by baking or the like to form the interlayer insulating layer 40a. As a result, contact holes 13d, 14d, 15d and 16d for exposing the electrodes 13a, 14a, 15a and 16a are formed in the interlayer insulating layer 40a.

  Next, as shown in FIGS. 4A and 4B, the coil wiring layer 21a, the lead wiring layers 23a, 24a, 25a, 26a, and the dummy wirings 30a, 31a, 32a are formed on the interlayer insulating layer 40a.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste has the pattern of FIG. 4A and is also embedded in the contact holes 13d, 14d, 15d, and 16d.

  Then, after the conductive paste is pattern-printed, firing is performed in an oxygen atmosphere and a reducing atmosphere to remove the resin component and the oxide, thereby removing the coil wiring layer 21a, the lead wiring layers 23a, 24a, 25a, 26a, and the dummy. Wirings 30a, 31a, 32a are formed.

  In addition, what contained metal nanoparticles, such as copper, powder, or these mixtures in resin as a conductive paste is used.

  Here, the coil wiring layer 21a is formed in a spiral shape in the coil formation region A1.

  The lead-out wiring layer 23 a constitutes the lead-out wiring 23 and is connected between the electrode 20 a of the coil wiring layer 21 a and the pad 13 a of the electrode pad 13 through the contact hole 13 d. The lead-out wiring layer 24 a is connected to the pad 14 a of the electrode pad 14 through the contact hole 14 d. The lead interconnection layer 25 a is connected to the pad 15 a of the electrode pad 15 through the contact hole 15 d. The lead interconnection layer 26 a is connected to the pad 16 a of the electrode pad 16 through the contact hole 16 d.

  In the lead-out wiring layers 23a, 24a, 25a, 26a of the present embodiment, the narrow wiring portions 51 and the pads 50 are alternately arranged. The pad 50 is a portion whose dimension in the width direction is larger than that of the narrow wiring portion 51. The lead-out wiring layer 23 a is a strip narrow wiring portion 51 connecting the electrode 20 a of the coil wiring layer 21 a and the pad 13 a of the electrode pad 13, and one of the narrow wiring portions 51 arranged at one end side in the longitudinal direction. And a pad 50. The lead-out wiring layers 24 a, 25 a, 26 a each include two narrow wiring portions 51 and two pads 50.

  The dummy interconnection 30a is disposed between the coil interconnection layer 21a and the lead interconnection layer 24a. A space d1 (see FIG. 4B) is formed between the dummy wiring 30a and the coil wiring layer 21a. A space d2 (see FIG. 4B) is formed between the dummy wiring 30a and the lead-out wiring layer 24a. The intervals d1 and d2 are set to, for example, 200 μm or less.

  The dummy wiring 31a is disposed between the coil wiring layer 21a and the lead-out wiring layer 25a. A first interval is formed between the dummy interconnection 31a and the coil interconnection layer 21a. A second interval is formed between the dummy wiring 31a and the lead-out wiring layer 25a. The first and second intervals are set to, for example, 200 μm or less.

  In the dummy wirings 30a, 31a, 32a of this embodiment, the narrow wiring portions 51 and the pads 50 are alternately arranged. The dummy interconnection 30 a includes three narrow interconnections 51 and two pads 50. The dummy wiring 31 a includes four narrow wiring portions 51 and three pads 50. The dummy interconnection 32 a includes seven narrow interconnections 51 and six pads 50.

  The dummy interconnection 32a is disposed between the coil interconnection layer 21a and the lead interconnection layer 26a. A space is formed between the dummy wiring 32a and the coil wiring layer 21a. A space is formed between the dummy interconnection 32a and the lead interconnection layer 26a.

  The lead-out wiring layers 23a and 25a are formed in the lead-out wiring formation area A2. The lead-out wiring layers 24a, 26a are formed in the lead-out wiring formation area A3.

  Next, along a direction parallel to one surface 10 a of the circuit board 10 on one side normal to the coil wiring layer 21 a, the lead wiring layers 23 a, 24 a, 25 a, 26 a, and the dummy wirings 30 a, 31 a, 32 a An interlayer insulating layer 40b is formed (see FIGS. 5A and 5B).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. The pattern printing covers the coil wiring layer 21a, the lead wiring layers 23a, 24a, 25a, 26a and the dummy wirings 30a, 31a, 32a from one side in the normal direction, and also the coil wiring layer 21a and the lead wiring layers 24a, 25a, Each portion 26a is formed to be exposed to one side in the normal direction.

  After the insulating paste is pattern-printed in this manner, baking or the like is performed to remove the resin component, thereby forming the interlayer insulating layer 40b. As a result, in the interlayer insulating layer 40b, contact holes for exposing portions of the coil wiring layer 21a and the lead-out wiring layers 24a, 25a, 26a are formed for each wiring layer.

  Next, as shown in FIGS. 5A and 5B, a coil wiring layer 21b, lead wiring layers 24b, 25b and 26b, and dummy wirings 30b, 31b and 32b are formed on the interlayer insulating layer 40b.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste becomes the pattern of FIG. 5A and is also embedded in the contact holes of the coil wiring layer 21a and the lead-out wiring layers 24a, 25a, 26a.

  Then, after the conductive paste is pattern-printed, firing is performed in an oxygen atmosphere and a reducing atmosphere to remove the resin component and the oxide, whereby the coil wiring layer 21b, the lead wiring layers 24b, 25b, 26b, and the dummy wiring 30b. , 31b, 32b.

  Here, the coil wiring layer 21 b is formed in a spiral shape on one side in the normal direction with respect to the coil wiring layer 21 a. The coil wiring layer 21b is connected to the coil wiring layer 21a via the contact hole.

  The lead-out wiring layer 24b is disposed offset to the coil wiring layer 21b side on one side in the normal direction with respect to the lead-out wiring layer 24a. The lead-out wiring layer 24 b is connected to the lead-out wiring layer 24 a through the contact hole.

  The lead-out wiring layer 25b is disposed offset to the coil wiring layer 21b side on one side in the normal direction with respect to the lead-out wiring layer 25a. The lead-out wiring layer 25 b is connected to the lead-out wiring layer 25 a through the contact hole.

  The lead-out wiring layer 26b is disposed offset to the coil wiring layer 21b side on one side in the normal direction with respect to the lead-out wiring layer 26a. The lead-out wiring layer 26 b is connected to the lead-out wiring layer 26 a through the contact hole.

  In the lead-out wiring layers 24b, 25b, 26b of the present embodiment, narrow-width wiring portions 51 and pads 50 are alternately arranged in the same manner as the lead-out wiring layers 24a, 25a, 26a.

  The dummy wiring 30 b is disposed between the lead-out wiring layer 24 b and the coil wiring layer 21 b. A space is formed between the dummy wiring 30b and the coil wiring layer 21b. A space is formed between the dummy wiring 30b and the lead-out wiring layer 24b.

  The dummy wiring 31 b is disposed between the lead-out wiring layer 25 b and the coil wiring layer 21 b. A space is formed between the dummy wiring 31b and the coil wiring layer 21b. A space is formed between the dummy wiring 31 b and the lead-out wiring layer 25 b.

  The dummy wiring 32 b is disposed between the lead wiring layer 26 b and the coil wiring layer 21 b. A space is formed between the dummy wiring 32b and the coil wiring layer 21b. A space is formed between the dummy interconnection 32b and the lead interconnection layer 26b.

  The dummy interconnections 30b, 31b, and 32b of the present embodiment are alternately arranged with narrow interconnections 51 and pads 50, similarly to the dummy interconnections 30a, 31a, and 32a.

  Next, an interlayer insulating layer is formed along a direction parallel to one surface 10a of circuit board 10 on one side normal to coil wiring layer 21b, lead wiring layers 24b, 25b, 26b, and dummy wirings 30b, 31b, 32b. 40c are formed (see FIGS. 6A and 6B).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. The pattern printing covers the coil wiring layer 21b, the lead wiring layers 24b, 25b and 26b, and the dummy wirings 30b, 31b and 32b from one side in the normal direction, and also for the coil wiring layer 21b and the lead wiring layers 24b, 25b and 26b. Each part is formed to be exposed on one side in the normal direction.

  After the insulating paste is pattern-printed as described above, baking and the like are performed to remove the resin component, thereby forming the interlayer insulating layer 40c. As a result, in the interlayer insulating layer 40c, contact holes for exposing portions of the coil wiring layer 21b and the lead-out wiring layers 24b, 25b and 26b are formed for each wiring layer.

  Next, a coil wiring layer 21c, lead wiring layers 24c, 25c, and 26c, and dummy wirings 30c, 31c, and 32c are formed on the interlayer insulating layer 40c (see FIGS. 6A and 6B).

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste has the pattern of FIG. 6A and is also embedded in the contact holes of the coil wiring layer 21c and the lead wiring layers 24c, 25c, and 26c.

  Then, after conducting pattern printing of the conductive paste, firing is performed in an oxygen atmosphere and a reducing atmosphere to remove the resin component and the oxide, whereby the coil wiring layer 21c, the lead wiring layers 24c, 25c, 26c, and the dummy wiring 30c. , 31c, 32c.

  Here, the coil wiring layer 21c is formed in a spiral shape on one side in the normal direction with respect to the coil wiring layer 21a. The coil wiring layer 21c is connected to the coil wiring layer 21a via a contact hole.

  The lead-out wiring layer 24c is disposed offset to the coil wiring layer 21c side on one side in the normal direction with respect to the lead-out wiring layer 24b. The lead-out wiring layer 24 c is connected to the lead-out wiring layer 24 b through the contact hole.

  The lead-out wiring layer 25c is disposed offset to the coil wiring layer 21c side on one side in the normal direction with respect to the lead-out wiring layer 25b. The lead-out wiring layer 25c is connected to the lead-out wiring layer 25b through the contact hole.

  The lead-out wiring layer 26c is disposed offset to the coil wiring layer 21c side on one side in the normal direction with respect to the lead-out wiring layer 26b. The lead-out wiring layer 26c is connected to the lead-out wiring layer 26b through the contact hole.

  In the lead-out wiring layers 24c, 25c, 26c of the present embodiment, the narrow-width wiring portions 51 and the pads 50 are alternately arranged in the same manner as the lead-out wiring layers 24a, 25a, 26a.

  The dummy interconnection 30c is disposed between the lead interconnection layer 24c and the coil interconnection layer 21c. A space is formed between the dummy wiring 30c and the coil wiring layer 21c. A space is formed between the dummy wiring 30c and the lead-out wiring layer 24c.

  The dummy wiring 31 c is disposed between the lead-out wiring layer 25 c and the coil wiring layer 21 c. A space is formed between the dummy wiring 31c and the coil wiring layer 21c. A space is formed between the dummy wiring 31c and the lead-out wiring layer 25c.

  The dummy wiring 32c is disposed between the lead wiring layer 26c and the coil wiring layer 21c. A space is formed between the dummy wiring 32c and the coil wiring layer 21c. A space is formed between the dummy interconnection 32c and the lead interconnection layer 26c.

  The dummy interconnections 30c, 31c, and 32c of the present embodiment are alternately arranged with narrow interconnections 51 and pads 50, similarly to the dummy interconnections 30a, 31a, and 32a.

  Next, an interlayer insulating layer is formed along a direction parallel to one surface 10 a of circuit board 10 on one side normal to coil interconnection layer 21 c, lead interconnection layers 24 c, 25 c, 26 c, and dummy interconnections 30 c, 31 c, 32 c. Form 40d (see FIG. 7A, FIG. 7B).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. The pattern printing covers the coil wiring layer 21c, the lead wiring layers 24c, 25c and 26c, and the dummy wirings 30c, 31c and 32c from one side in the normal direction, and at the same time the coil wiring layer 21c and the lead wiring layers 24c, 25c and 26c. Each part is formed to be exposed on one side in the normal direction.

  After the insulating paste is pattern-printed as described above, baking and the like are performed to remove the resin component, thereby forming the interlayer insulating layer 40d. As a result, in the interlayer insulating layer 40d, contact holes for exposing portions of the coil wiring layer 21c and the lead-out wiring layers 24c, 25c, 26c are formed for each wiring layer.

  Next, as shown in FIGS. 7A and 7B, a coil wiring layer 21d, lead wiring layers 24d, 25d, 26d, and dummy wirings 31d, 32d are formed on the interlayer insulating layer 40d.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste becomes the pattern of FIG. 7A and is also embedded in the contact holes of the coil wiring layer 21d and the lead-out wiring layers 24d, 25d, 26d.

  Then, after conducting pattern printing of the conductive paste, firing is performed in an oxygen atmosphere and a reducing atmosphere to remove the resin component and the oxide, whereby the coil wiring layer 21d, the lead wiring layers 24d, 25d, 26d, and the dummy wiring 31d are obtained. , 32d.

  The coil wiring layer 21 d is formed in a spiral shape on one side in the normal direction with respect to the coil wiring layer 21 a. The coil wiring layer 21d is connected to the coil wiring layer 21c via the contact hole.

  The lead-out wiring layer 24 d is disposed offset to the coil wiring layer 21 d side on one side in the normal direction with respect to the lead-out wiring layer 24 c. The lead-out wiring layer 24 d is connected to the lead-out wiring layer 24 c via the contact hole, and is connected to the electrode 20 b of the coil wiring layer 21 d.

  The lead-out wiring layer 25d is disposed on one side in the normal direction with respect to the lead-out wiring layer 25c and offset to the coil wiring layer 21d side with respect to the lead-out wiring layer 25c. The lead-out wiring layer 25d is connected to the lead-out wiring layer 25c through the contact hole.

  The lead-out wiring layer 26 d is disposed on one side in the normal direction with respect to the lead-out wiring layer 26 c and offset to the coil wiring layer 21 d side with respect to the lead-out wiring layer 26 c. The lead-out wiring layer 26 d is connected to the lead-out wiring layer 26 c through the contact hole.

  In the lead-out wiring layers 24c, 25c, 26c of the present embodiment, the narrow-width wiring portions 51 and the pads 50 are alternately arranged in the same manner as the lead-out wiring layers 24a, 25a, 26a.

  The dummy wiring 31 d is disposed between the lead-out wiring layer 25 d and the coil wiring layer 21 d. A space is formed between the dummy wiring 31 d and the coil wiring layer 21 d. A space is formed between the dummy wiring 31 d and the lead-out wiring layer 25 d.

  The dummy wiring 32 d is disposed between the lead-out wiring layer 26 d and the coil wiring layer 21 d. A space is formed between the dummy wiring 32 d and the coil wiring layer 21 d. A space is formed between the dummy wiring 32 d and the lead-out wiring layer 26 d.

  In the dummy wirings 31 d and 32 d of the present embodiment, the narrow wiring portions 51 and the pads 50 are alternately arranged, similarly to the dummy wirings 30 a, 31 a and 32 a.

  Next, an interlayer insulating layer 40e is provided along the direction parallel to one surface 10a of the circuit board 10 on one side normal to the coil wiring layer 21d, the lead wiring layers 24d, 25d, 26d, and the dummy wirings 31d, 32d. (See FIGS. 8A and 8B).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. The pattern printing covers the coil wiring layer 21d, the lead wiring layers 24d, 25d and 26d, and the dummy wirings 31d and 32d from one side in the normal direction, and a part of each of the coil wiring layer 21d and the lead wiring layers 25d and 26d is It is formed to be exposed to one side in the normal direction.

  After the insulating paste is pattern-printed in this manner, baking or the like is performed to remove the resin component, thereby forming the interlayer insulating layer 40e. As a result, in the interlayer insulating layer 40e, contact holes for exposing portions of the coil wiring layer 21d and the lead-out wiring layers 25d and 26d are formed for each wiring layer.

  Next, as shown in FIGS. 8A and 8B, the coil wiring layer 22a, the lead wiring layers 25e and 26e, and the dummy wiring 32e are formed on the interlayer insulating layer 40e.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste has the pattern of FIG. 8A and is also embedded in the contact holes of the coil wiring layer 21d and the lead-out wiring layers 25d and 26d.

  Then, after the conductive paste is pattern printed, baking is performed in an oxygen atmosphere and a reducing atmosphere to remove the resin component and the oxide, thereby forming the coil wiring layer 22a, the lead wiring layers 25e and 26e, and the dummy wiring 32e. Do.

  Here, the coil wiring layer 22a is formed in a spiral shape on one side in the normal direction with respect to the coil wiring layer 21d. The coil wiring layer 22a is not connected to the coil wiring layer 21d.

  The lead-out wiring layer 25e is disposed on one side in the normal direction with respect to the lead-out wiring layer 25d and offset to the coil wiring layer 22a side with respect to the lead-out wiring layer 25d. The lead-out wiring layer 25e is connected to the lead-out wiring layer 25d through the contact hole, and is connected to the coil wiring layer 22a.

  The lead-out wiring layer 26e is disposed on one side in the direction normal to the lead-out wiring layer 26d and offset to the coil wiring layer 22a side with respect to the lead-out wiring layer 26d. The lead-out wiring layer 26e is connected to the lead-out wiring layer 26d through the contact hole.

  In the lead-out wiring layers 24e, 25e, and 26e of the present embodiment, narrow-width wiring portions 51 and pads 50 are alternately arranged in the same manner as the lead-out wiring layers 24a, 25a, and 26a.

  The dummy wiring 32e is disposed between the lead wiring layer 26e and the coil wiring layer 22a. A space is formed between the dummy interconnection 32e and the coil interconnection layer 22a. A space is formed between the dummy interconnection 32e and the lead interconnection layer 26e.

  In the dummy interconnections 32 e of the present embodiment, the narrow interconnections 51 and the pads 50 are alternately arranged, similarly to the dummy interconnections 30 a, 31 a, and 32 a.

  Next, an interlayer insulating layer 40f is formed along the direction parallel to one surface 10a of the circuit board 10 on one side normal to the coil wiring layer 22a, the lead-out wiring layers 25e and 26e, and the dummy wiring 32e (see FIG. 9A and 9B).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. In the pattern printing, the coil wiring layer 22a, the lead wiring layers 25e and 26e, and the dummy wiring 32e are covered from one side in the normal direction, and a part of each of the coil wiring layer 22a and the lead wiring layer 26f is on one side in the normal direction. It is formed to be exposed.

  After the insulating paste is pattern-printed in this manner, baking or the like is performed to remove the resin component, thereby forming the interlayer insulating layer 40f. As a result, in the interlayer insulating layer 40f, contact holes for exposing a part of the coil wiring layer 22a and the lead-out wiring layer 26e are formed for each wiring layer.

  Next, as shown in FIGS. 9A and 9B, the coil wiring layer 22b, the lead wiring layer 26f, and the dummy wiring 32f are formed on the interlayer insulating layer 40f.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste becomes the pattern of FIG. 8A and is also embedded in the contact holes of the coil wiring layer 22a and the lead-out wiring layer 26e.

  Here, the coil wiring layer 22 b is formed in a spiral shape on one side in the normal direction with respect to the coil wiring layer 22 a. The coil wiring layer 22b is connected to the coil wiring layer 22a through the contact hole.

  The lead-out wiring layer 25f is disposed on one side in the normal direction with respect to the lead-out wiring layer 25e and offset to the coil wiring layer 22b side with respect to the lead-out wiring layer 26e. The lead-out wiring layer 26f is connected to the lead-out wiring layer 26e through the contact hole.

  In the lead-out wiring layer 26f of the present embodiment, the narrow-width wiring portions 51 and the pads 50 are alternately arranged like the lead-out wiring layers 24a, 25a, 26a.

  The dummy interconnection 32f is disposed between the lead interconnection layer 26f and the coil interconnection layer 22b. An interval is formed between the dummy wiring 32f and the coil wiring layer 22f. A space is formed between the dummy wiring 32 f and the lead-out wiring layer 26 f.

  Similar to the dummy wirings 30a, 31a, and 32a, the narrow wirings 51 and the pads 50 are alternately arranged in the dummy wirings 32f of the present embodiment.

  Next, an interlayer insulating layer 40g is formed along the direction parallel to one surface 10a of the circuit board 10 on one side normal to the coil wiring layer 22b, the lead-out wiring layer 26f, and the dummy wiring 32f (FIG. 10A) , See FIG. 10B).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. The pattern printing covers the coil wiring layer 22b, the lead wiring layer 26f, and the dummy wiring 32f from one side in the normal direction, and a part of each of the coil wiring layer 22b and the lead wiring layer 26f is exposed to one side in the normal direction. Formed as.

  After the insulating paste is pattern-printed as described above, baking and the like are performed to remove the resin component, thereby forming the interlayer insulating layer 40 h. As a result, in the interlayer insulating layer 40g, a contact hole for exposing a part of the coil wiring layer 22b and the lead-out wiring layer 26f is formed for each wiring layer.

  Next, as shown in FIGS. 10A and 10B, the coil wiring layer 22c, the lead wiring layer 26g, and the dummy wiring 32g are formed on the interlayer insulating layer 40g.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste becomes the pattern of FIG. 11A and is also embedded in the contact holes of the coil wiring layer 22b and the lead-out wiring layer 26f.

  The coil wiring layer 22c is formed spirally on one side in the normal direction with respect to the coil wiring layer 22b. The coil wiring layer 22c is connected to the coil wiring layer 22b through the contact hole.

  The lead-out wiring layer 26 g is disposed on one side in the normal direction with respect to the lead-out wiring layer 26 f and offset to the coil wiring layer 22 c with respect to the lead-out wiring layer 26 f.

  Similar to the lead wiring layers 24a, 25a, 26a, the narrow wiring portions 51 and the pads 50 are alternately arranged in the lead wiring layer 26g of the present embodiment.

  The dummy interconnection 32g is disposed between the lead interconnection layer 26g and the coil interconnection layer 22c. A space is formed between the dummy wiring 32g and the coil wiring layer 22c. A space is formed between the dummy interconnection 32g and the lead interconnection layer 26g.

  Similar to the dummy wirings 30a, 31a, and 32a, the narrow wirings 51 and the pads 50 are alternately arranged in the dummy wirings 32g of the present embodiment.

  Next, an interlayer insulating layer 40h is formed along a direction parallel to one surface 10a of the circuit board 10 on one side normal to the coil wiring layer 22d, the lead-out wiring layer 26h, and the dummy wiring 32g (FIG. 11A) , 11 B)).

  Specifically, first, the above-described insulating paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. The pattern printing covers the coil wiring layer 22d, the lead-out wiring layer 26h, and the dummy wiring 32g from one side in the normal direction, and a part of each of the coil wiring layer 22c and the lead-out wiring layer 26g is exposed to one side in the normal direction. Formed as.

  After the insulating paste is pattern-printed as described above, baking and the like are performed to remove the resin component, thereby forming the interlayer insulating layer 40g. As a result, in the interlayer insulating layer 40g, contact holes for exposing portions of the coil wiring layer 22c and the lead-out wiring layer 26g are formed for each wiring layer.

  Next, as shown in FIGS. 11A and 11B, the coil wiring layer 22d and the lead wiring layer 26h are formed.

  Specifically, first, the conductive paste is pattern-printed by a screen printing method using a mask (not shown) in which a predetermined region is opened. At this time, pattern printing is performed so that the conductive paste becomes the pattern of FIG. 11A and is also embedded in the contact holes of the coil wiring layer 22c and the lead-out wiring layer 26g.

  The coil wiring layer 22 d is formed spirally on one side in the normal direction with respect to the coil wiring layer 22 c. The coil wiring layer 22d is connected to the coil wiring layer 22c through the contact hole.

  The lead-out wiring layer 26 h is disposed on one side in the normal direction with respect to the lead-out wiring layer 26 g and offset to the coil wiring layer 22 d side with respect to the lead-out wiring layer 26 g.

  In the lead-out wiring layer 26 h of the present embodiment, the narrow-width wiring portions 51 and the pads 50 are alternately arranged in the same manner as the lead-out wiring layers 24 a, 25 a, 26 a.

  As described above, the conductive paste is repeatedly pattern-printed on one surface side of the circuit board 10, and the conductive paste is fired every printing. As a result, dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g, which are fired products of the conductive material, are stacked.

  On the other hand, conductive paste is pattern-printed on one side of the normal direction to the dummy wiring every time the dummy wiring is formed on one surface side of the circuit board 10, and the conductive paste is fired every printing. As a result, the lead-out wiring layers 21a to 21d and 22a to 22d, which are fired bodies of the conductive material, are stacked.

  Then, every time a dummy wiring or drawing wiring layer is formed, insulating paste is pattern-printed on one side in the normal direction with respect to the dummy wiring or drawing wiring layer on one surface 10 a side of the circuit board 10. The pattern printed electrical insulating paste is fired. As a result, the interlayer insulating layers 40a to 40h, which are fired bodies of the electrical insulating material, are stacked to form the insulating film 40.

  In the present embodiment configured as described above, the coil wiring layers 21 a, 21 b, 21 c and 21 d are stacked in the normal direction on the surface 10 a of the circuit board 10 to form the coil 21. The coil wiring layers 22a, 22b, 22c, and 22d are stacked in the direction normal to the coil wiring layers 21a, 21b, 21c, and 21d to form the coil 22. The lead-out wiring layer 23 a is formed along the surface 10 a of the circuit board 10.

  The lead-out wiring layers 24 a, 24 b, 24 c, 24 d are stacked in the normal direction on the surface 10 a of the circuit board 10 to form a lead-out wiring 24. The lead-out wiring 24 is formed in a step-like shape that advances to the other side in the normal direction as it approaches the electrode pad 14 from the electrode 20 b of the coil 21.

  The lead-out wiring layers 25 a, 25 b, 25 c, 25 d, and 25 e are stacked in the normal direction on one surface 10 a of the circuit board 10 to form the lead-out wiring 25. The lead-out wiring 25 is formed in a step-like shape that advances to the other side in the normal direction as it approaches the electrode pad 15 from the electrode 20 c of the coil 22.

  The lead-out wiring layers 26 a, 26 b, 26 c, 26 d, 26 e, 26 f, 26 g and 26 h are stacked in the normal direction on the surface 10 a of the circuit board 10 to constitute the lead-out wiring 26. The lead-out wiring 26 is formed in a step-like shape that advances to the other side in the normal direction as it approaches the electrode pad 16 from the electrode 20 d of the coil 22 (see FIGS. 1A and 1B).

  Here, the dummy wirings 30 a to 30 c are stacked between the lead wiring layers 24 a to 24 d and the circuit board 10.

  Dummy interconnections 30a-30c and extraction interconnection layers 24a-24d are arranged such that pads 50 constituting dummy interconnections 30a-30c and pads 50 constituting extraction interconnection layers 24a-24d overlap as viewed in the normal direction. It is done.

  The dummy interconnections 30 a to 30 c and the extraction interconnection layer are formed so that the narrow interconnections 51 constituting the dummy interconnections 30 a to 30 c and the narrow interconnections 51 constituting the interconnection interconnection layers 24 a to 24 d overlap as viewed in the normal direction. 24a to 24d are arranged.

  The dummy wirings 31 a to 31 d are stacked between the lead wiring layers 25 a to 25 e and the circuit board 10.

  The dummy wirings 31a to 31d and the lead wiring layers 25a to 25e are arranged such that the pads 50 constituting the dummy wirings 31a to 31d and the pads 50 constituting the lead wiring layers 25a to 25e overlap as viewed in the normal direction. It is done.

  The narrow interconnections 51 constituting the dummy interconnections 31a to 31d and the narrow interconnections 51 constituting the interconnection interconnections 25a to 25e are overlapped with the dummy interconnections 31a to 31d in a view from the normal direction. 25a to 25e are arranged.

  The dummy wirings 32 a to 32 g are stacked between the lead wiring layers 26 a to 26 g and the circuit board 10.

  Dummy interconnections 32a to 32g and extraction interconnection layers 26a to 26g are arranged such that pads 50 constituting dummy interconnections 32a to 32g and pads 50 constituting extraction interconnection layers 26a to 26g overlap as viewed in the normal direction. ing.

  The dummy interconnections 32a to 32g and the extraction interconnection layer 26a are arranged such that the narrow interconnections 51 forming the dummy interconnections 32a to 32g and the narrow interconnections 51 forming the interconnection interconnections 26a to 26g overlap as viewed in the normal direction. -26 g are arranged.

  The widthwise dimensions of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g in the present embodiment are the same as the widthwise dimensions of the lead wiring layers 24a to 24d, 25a to 25e, and 26a to 26g. The dimensions in the thickness direction of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g are the same as the dimensions in the thickness direction of the lead wiring layers 24a to 24d, 25a to 25e, and 26a to 26g.

  In the wiring, the thickness direction is a direction parallel to the normal direction to the surface 10 a of the circuit board 10. In the wiring, the width direction is a direction orthogonal to the extending direction of the wiring and orthogonal to the normal direction.

  In the present embodiment, the lead wire 24 is connected to the electrode 20b of the coil 21 so as to be orthogonal to the direction in which the coil current flowing through the coil 21 flows (hereinafter referred to as the coil current direction of the coil 21) (FIG. 12A) reference).

  On the other hand, when the angle formed with respect to the coil current direction of the coil 21 is an obtuse angle or an acute angle, the lead-out wire 24 cancels the current that should normally flow in the coil 21 according to the magnetic flux generated in the coil 21 Occurs (see FIG. 12B).

  On the other hand, in the present embodiment, as described above, the lead-out wiring 24 is connected to the electrode 20 b of the coil 21 so as to be orthogonal to the coil current direction of the coil 21. For this reason, it is possible to prevent in advance the generation of a current that cancels the current that should originally flow in the coil 21.

  Here, the dummy wirings 30 a to 30 c arranged on the circuit board 10 side with respect to the lead wiring 24 are arranged in parallel to the lead wiring 24. Therefore, when viewed from the normal direction, the dummy wires 30 a to 30 c and the lead wire 24 are arranged to be orthogonal to the coil current direction of the coil 21.

  Similarly, the lead wires 25 26 connected to the coil 22 are connected to the electrodes 20 c 20 d of the coil 22 so as to be orthogonal to the coil current direction of the coil 22. Therefore, when viewed from the normal direction, the dummy wirings 31 a to 31 d and the lead wirings 25 are arranged to be orthogonal to the coil current direction of the coil 22. As viewed from the normal direction, the dummy wires 32 a to 32 g and the lead wire 26 are arranged to be orthogonal to the coil current direction of the coil 22.

  12A and 12B, reference numeral G1 indicates a state in which the magnetic flux flows toward the front side in the direction perpendicular to the sheet, and reference G2 indicates a state in which the magnetic flux flows toward the rear side in the direction perpendicular to the sheet.

  In the present embodiment, among the lead wiring layers 24 a to 24 d constituting the lead wiring 24, the upper lead wiring layer (for example, the lead wiring layer 24 d) and the lower lead wiring layer (for example, the lead wiring layer 24 c) The pads 50 are connected to each other via the connection portion 42 (see FIGS. 13A and 13B).

  Similarly, among the lead-out wiring layers 25 a to 25 e constituting the lead-out wiring 25, the upper lead-out wiring layer and the lower lead-out wiring layer are connected to each other via the connection portion 42. Similarly, among the lead wiring layers 26 a to 26 g constituting the lead wiring 26, the upper lead wiring layer and the lower lead wiring layer are connected to each other via the connection portion 42.

In the present embodiment, the dummy wirings 30a to 30c, 31a to 31d, 32a to 32e,
The pads 50 forming each of the lead-out interconnection layers 24a to 24d, 25a to 25e, and 26a to 26h are formed in the same shape. The narrow interconnections 51 constituting the dummy interconnections 30a to 30c, 31a to 31d, and 32a to 32e and the lead interconnection layers 24a to 24d, 25a to 25e, and 26a to 26h are respectively formed in the same shape.

  As described above, in the semiconductor device 1 of the present embodiment, conductive paste (or insulating paste) for forming the lead-out wiring layers 24a to 24d, 25a to 25e, 26a to 26g and the interlayer insulating layers 40a to 40h. The temperature of the lead-out wiring layer and the interlayer insulating layer formed before the firing increases when firing the. Therefore, stress applied to the lead-out wiring layer is generated according to the difference between the thermal expansion coefficient of the lead-out wiring layer and the thermal expansion coefficient of the interlayer insulating layer.

  Here, dummy wirings 30 a to 30 c, 31 a to 31 d, and 32 a to 32 g are disposed on the circuit board 10 side with respect to the lead wirings 24, 25, and 26. For this reason, the volume of the insulating film 40 disposed on the circuit board 10 side with respect to the lead wires 24, 25, 26 can be reduced. In addition to this, the lead wirings 24, 25, 26 and the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g are respectively made of the same conductive material.

  For this reason, the stress given from the insulating film 40 to the lead wirings 24, 25, 26 can be reduced. This can suppress the occurrence of cracks in the lead-out lines 24, 25, 26.

  In the present embodiment, the conductive materials constituting the lead wires 24, 25, 26 and the dummy wirings 30a to 30c, 31a to 31d, 32a to 32g have a thermal expansion coefficient smaller than that of the electrical insulating material constituting the insulating film 40. ing. For this reason, the stress applied from the insulating film 40 to the lead wirings 24, 25, 26 can be further reduced.

  Further, as shown in FIGS. 14A and 14B, a Via wiring 27B formed by stacking a plurality of wiring layers in the thickness direction of the semiconductor substrate 11 and a wiring 27A connecting the Via wiring 27B and the transformer 20 are drawn out. In the case of forming as 27, there is a possibility that a crack may occur in the lead-out wire 27 as follows.

  That is, after forming the lead-out wiring 27 and the interlayer insulating layers 40a, 40b,... 40f, 40g, when firing the insulating paste patterned and printed to form the interlayer insulating layer 40h, the lead-out wiring 27 and the interlayer insulating layer Large heat is applied to 40a, 40b, 40f and 40g.

  As shown in FIG. 14B, a tensile stress from the insulating film 40 is generated in the Via wiring 27B to cause a crack in the Via wiring 27B, or as shown in FIG. 14C, stress is generated in the wiring 27A due to expansion of the insulating film 40. In addition, the wiring 27A is cracked.

  On the other hand, in the present embodiment, the lead-out wiring layers 24 a to 24 d are formed in a step shape. Therefore, the thickness dimension of the insulating film 40 between the lead wiring layers 24 a to 24 d and the circuit board 10 becomes smaller as it approaches the electrode 14. For this reason, it is possible to reduce the stress due to the tensile stress and the expansion on the lead interconnection layers 24 a to 24 d. Similarly, the lead wiring layers 25a to 25e and 26a to 26h are also formed in a step-like shape. Therefore, similar effects can be obtained.

  In the present embodiment, the narrow interconnections 51 and the pads 50 are the same as the lead interconnections 24a to 24d, 25a to 25e, and 26a to 26h and the dummy interconnections 30a to 30c, 31a to 31d, and 32a to 32g, respectively. And are alternately arranged.

  Here, when the width dimensions of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g are increased, the magnetic fields generated by the coil 21 (or 22) become complex with the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g. It becomes easy to cross, and eddy current is generated in the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g to deteriorate the characteristics of the coil 21 (or 22).

  On the other hand, in the present embodiment, as described above, the lead-out interconnection layers 24a to 24d, 25a to 25e, and 26a to 26h, and the dummy interconnections 30a to 30c, 31a to 31d, and 32a to 32g respectively are the same. The narrow wiring portions 51 and the pads 50 are alternately arranged.

  As a result, the magnetic field generated by the coil 21 (or 22) is less likely to cross over the dummy wires 30a-30c, 31a-31d, 32a-32g, and the dummy wires 30a-30c, 31a-31d, 32a-32g swirl. It becomes difficult to generate current. Therefore, the deterioration of the characteristics of the coil 21 (or 22) is suppressed.

  In the present embodiment, any one of the dummy interconnections 30a to 30c, 31a to 31d, and 32a to 32e, and any one of the extraction interconnection layers 24a to 24d, 25a to 25e, and 26a to 26h. The coil wiring layer of any of the coil wiring layers 21a to 21d and 22a to 22d is formed in the same layer.

  The lead wiring layers 24a to 24d, 25a to 25e, 26a to 26h, the dummy wirings 30a to 30c, 31a to 31d, 32a to 32e, and the coil wiring layers 21a to 21d, 22a to 22d have the same thickness dimensions, respectively. It has become.

Here, the process of pattern printing the conductive paste for forming the coil wiring layer, the dummy wiring, and the lead wiring layer formed in the same layer is performed in the same process. In addition to this, the step of firing the conductive paste for forming the coil wiring layer, the dummy wiring, and the lead wiring layer formed in the same layer is performed in the same step. Thereby, the number of processes and the process cost can be reduced. In addition to this, in the present embodiment, it is possible to suppress the variation in the width dimensions of the extraction wiring layers 24a to 24d, 25a to 25e, 26a to 26h and the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e. The material forming the insulating film 40 is polyimide, and the material forming the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e is, for example, Cu or Ag. Cu and Ag have high thermal conductivity. For this reason, although the insulating film 40 has poor heat dissipation,
Since the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e enter into the insulating film 40, it is possible to improve the performance of cooling the heat generated in the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e.

  In the present embodiment, the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e are respectively sandwiched by the insulating material forming the insulating film 40 from one side and the other side in the normal direction. Therefore, the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e themselves may be cracked by suppressing the thickness dimensions of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e from becoming too large. It can be suppressed.

  In the present embodiment, the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e are not connected to the lead wiring layers 24a to 24d, 25a to 25e, and 26a to 26h. Therefore, the end portions of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e can be used as free ends.

  Here, when the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e are connected to the lead wiring layers 24a to 24d, 25a to 25e, and 26a to 26h, the dummy wirings 30a to 30c, 31a to 31d are formed. The end portions of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e become fixed ends due to the thermal expansion of the lead wirings 32a to 32e and the lead wiring layers 24a to 24d, 25a to 25e, and 26a to 26h. Occur. For this reason, there is a possibility that the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e may be cracked.

  On the other hand, in the present embodiment, the end portions of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e can be used as free ends. Therefore, no stress is generated at the end of each of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e, and the generation of cracks in the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e is suppressed in advance. be able to.

  In the present embodiment, the pads 50 of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e have the same shape and are configured to overlap when viewed from the normal direction. The narrow wiring portions 51 of the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e have the same shape and are configured to overlap when viewed from the normal direction.

  For example, when the dimension in the width direction of the pad 50 of the dummy interconnection 30b is large in the width direction of the pad 50 of the dummy interconnection 30a, the interlayer insulating layer 40a on the circuit substrate 10 side with respect to the dummy interconnection 30a Stress generated by thermal expansion passes through the side of the pad 50 of the dummy wiring 30a and is applied to the pad 50 of the dummy wiring 30b. For this reason, there is a possibility that a crack may occur in the pad 50 of the dummy wiring 30b due to the stress. That is, a stress caused by thermal expansion of a portion of the insulating film 40 on the circuit board 10 side may act on the dummy wiring on one side in the normal direction of the dummy wirings 30 a to 30 c to generate a crack.

On the other hand, in the present embodiment, the pads 50 constituting the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e have the same shape, and are configured to overlap when viewed from the normal direction. The narrow wiring portions 51 forming the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e have the same shape, and are configured to overlap when viewed from the normal direction. Therefore, it is possible to suppress that the stress from the circuit board 10 side in the insulating film 40 acts on the dummy wiring on one side in the normal direction among the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e.
Second Embodiment
In the first embodiment, an example in which the narrow wiring portions 51 and the pads 50 are alternately arranged in the lead-out wiring layers 24 a to 24 d, 25 a to 25 e, and 26 a to 26 h has been described. In the second embodiment, an example will be described in which the lead-out wiring layers 24 a to 24 d, 25 a to 25 e, and 26 a to 26 h are formed in a band shape extending in the longitudinal direction with the same width.

  FIG. 15 shows a top view of the semiconductor device 1 of the second embodiment. In FIG. 15, the same reference numerals as in FIG. 1A indicate the same components.

  The present embodiment is different from the first embodiment only in the shapes of the lead-out wiring layers 24a to 24d, 25a to 25e, and 26a to 26h and the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e.

  The lead-out wiring layers 24 a to 24 d, 25 a to 25 e, and 26 a to 26 h of the present embodiment are each formed in a strip shape extending in the longitudinal direction with the same width. Similarly, the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e are each formed in a strip shape extending in the longitudinal direction with the same width.

Third Embodiment
In the third embodiment, an example in which the lead wires 24, 26 of the semiconductor device 1 according to the first embodiment are formed in a spiral step will be described.

  FIG. 16A shows a top view of the semiconductor device 1 of this embodiment. 16B is a cross-sectional view taken along line XVI-XVI in FIG. 16A.

  As shown in FIG. 16B, dummy wires 300, 301, 302, 303, 304, 305, and 306 are stacked on the other side in the normal direction with respect to the lead-out wiring layer 26h. Dummy wirings 400, 401, and 402 are stacked on the other side in the normal direction with respect to the lead-out wiring layer 26d.

  Here, the lead-out wiring layer 26 d and the dummy wiring 303 are formed in the same layer. The lead-out wiring layer 26 d and the dummy wiring 303 are arranged in parallel.

  The dimension in the width direction of the lead-out wiring layer 26d is L1, the dimension in the width direction of the dummy wiring 303 is L2, the dimension between the lead-out wiring layer 26d and the dummy wiring 303 is S, and L1 = L2 = S. Wiring layers 26a to 26h and dummy wirings 300 to 306 and 400 to 402 are formed. As a result, by making L1, L2, and S uniform, the process of screen printing is stabilized, the variation in the width dimension is reduced, and the occurrence probability of the overstress due to the variation is reduced.

Fourth Embodiment
In the fourth embodiment, an example will be described in which a coil core 61 made of a magnetic material is disposed on the side of the center line S of the coils 21 and 22 in the semiconductor device 1 of the first embodiment.

  FIG. 17 shows a top view of the semiconductor device 1 of the present embodiment. In FIG. 17, the same reference numerals as in FIG. 1A indicate the same components.

  In the present embodiment, the magnetic layer 60 is formed to cover the lead-out wiring layers 24 a to 24 d, 25 a to 25 e, and 26 a to 26 h and the dummy wirings 30 a to 30 c, 31 a to 31 d, and 32 a to 32 e. The coil core 61 is connected to the magnetic layer 60.

  In the embodiment configured as described above, the dummy wirings 30 a to 30 c, 31 a to 31 d, and 32 a to 32 e are formed of the same magnetic material as the coil core 61. In this case, the dummy wirings 30a to 30c, 31a to 31d, 32a to 32e, the coil core 61, and the magnetic layer 60 are formed in the same step for each layer. Specifically, after pattern printing of a magnetic paste containing a magnetic material is performed for each layer, baking is performed in an oxygen atmosphere and a reducing atmosphere to remove resin components and oxides, whereby the dummy wirings 30a to 30c and 31a are formed. To 31 d, 32 a to 32 e, a coil core 61 and a magnetic layer 60 are formed.

  In the present embodiment, the dummy wirings 30 a to 30 c, 31 a to 31 d, and 32 a to 32 e are made of the same magnetic material as the coil core 61. For this reason, the magnetic flux generated in the coils 21 and 22 also passes through the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32e. Therefore, the inductance of the transformer 20 is improved, and the characteristics of the coils 21 and 22 and the transformer 20 can be improved.

  In this embodiment, metal (Fe, Ni, etc.) or metal oxide (eg, ferrite, etc.) is used as the magnetic material forming the dummy wirings 30a-30c, 31a-31d, 32a-32e and the coil core 61. Be The material forming the dummy wirings 30 a to 30 c, 31 a to 31 d, and 32 a to 32 e is a material smaller than the thermal expansion coefficient of the insulating film 40.

  Here, since the dummy wirings 30a to 30c, 31a to 31d, 32a to 32e and the coil core 61 have higher thermal conductivity than the polyimide constituting the insulating film 40, the lead wiring layers 24a to 24d, 25a to 25e, 26a to The heat generated in 26 h can be dissipated efficiently.

(Other embodiments)
(1) In the first to fourth embodiments, the example in which the two coils 21 and 22 are configured in the semiconductor device 1 is described, but instead of this, one coil 21 (22) is configured in the semiconductor device 1 You may

  (2) In the first to fourth embodiments, although the example in which the insulating film 40 is formed of a resin material has been described, the present invention is not limited thereto. The material constituting the insulating film 40 is formed of an electrical insulating material Then, various materials such as nitrides and oxides may be used.

  (3) In the first to fourth embodiments, the conductive paste (or insulating paste) is applied onto the circuit board 10 using printing, but instead, the conductive paste is applied using a method other than printing. The paste (or insulating paste) may be applied onto the circuit board 10.

  (4) In the first to fourth embodiments, an example in which a plurality of dummy wirings are stacked between the circuit board 10 and the lead-out wiring layers 24a to 24d, 25a to 25e, and 26a to 26g has been described. Instead of the above, a single-layer dummy wiring may be disposed between the circuit board 10 and the lead-out wiring layers 24a to 24d, 25a to 25e, and 26a to 26g.

  (5) In addition, this invention is not limited to above-described embodiment, In the range described in the claim, it can change suitably.

  For example, although the method of forming the lead-out wiring layers 24a to 24d, 25a to 25e, 26a to 26g, and the dummy wirings 30a to 30c, 31a to 31d, and 32a to 32g is a printing method using conductive printing paste, Alternatively, the following may be performed.

  That is, the lead-out interconnection layers 24a to 24d, 25a to 25e, and 26a to 26g and the dummy interconnections 30a to 30c, 31a to 31d, and 32a to 32g may be formed using a plating method.

  In this case, when forming an interlayer insulating layer among the interlayer insulating layers 40a to 40h by firing the electrically insulating paste, the lead-out interconnection layer and the interlayer insulating layer formed before forming the interlayer insulating layer. A large amount of heat is applied to the and, and the temperature of each of the lead-out wiring layer and the interlayer insulating layer is increased. Therefore, stress is generated due to the difference between the thermal expansion coefficient of the lead-out wiring layer and the thermal expansion coefficient of the interlayer insulating layer.

  Therefore, as in the first embodiment, the stress applied from the interlayer insulating layer to the lead-out wiring layer can be reduced by using the dummy wiring. This can suppress the occurrence of cracks in the lead-out wiring layer.

  Alternatively, the coil wiring layers 21a to 21d and 22a to 22d may be formed using a plating method.

  (6) Moreover, said each embodiment is not mutually irrelevant and can be combined suitably, unless the combination is obviously impossible. Further, in each of the above-described embodiments, it is needless to say that the elements constituting the embodiment are not necessarily essential except when clearly indicated as being essential and when it is considered to be obviously essential in principle. Yes. Further, in the above embodiments, when numerical values such as the number, numerical value, amount, range, etc. of constituent elements of the embodiment are mentioned, it is clearly indicated that they are particularly essential and clearly limited to a specific number in principle. It is not limited to the specific number except when it is done. Further, in the above embodiments, when referring to the shape, positional relationship, etc. of the component etc., unless otherwise specified or in principle when limited to a specific shape, positional relationship, etc. It is not limited to the positional relationship and the like.

1 Semiconductor device (electronic device)
10 Circuit board (board)
13, 14, 15, 16 electrode pads 20 transformers 21, 22 coils 21a to 21d, 22a to 22d coil wiring layers 23, 24, 25, 26 lead wiring 24a to 24d, 25a to 25e, 26a to 26g lead wiring layer 30a to 30c, 31a to 31d, 32a to 32g dummy wiring 40 insulating film 40a to 40h interlayer insulating layer

Claims (18)

A substrate (10) having one surface (10a),
A coil (21, 22) formed on one surface side of the substrate and wound with the normal line of the one surface as a center line;
A first electrode pad and a second electrode pad (13 to 16) formed on one side of the substrate;
A first lead-out wiring (25) formed on one surface side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
And a second lead-out wire (24, 26) formed on one side of the substrate to connect the second electrode (20b, 20d) of the coil and the second electrode pad (14, 16). In electronic devices,
Any one of the first and second lead-out lines is made of a conductive material, and a plurality of lead-out line layers (24a to 24a) are stacked in the normal direction of one surface of the substrate. 24d, 25a to 25e, 26a to 26g),
Dummy wirings (30a to 30c, 31a to 31d, 32a to 32e) which are disposed between the one lead wiring and the substrate and are made of a conductive material;
A plurality of insulating layers (40a to 40h) which are disposed between the one lead wire and the substrate, and which are respectively formed of a sintered body of an electrically insulating material and stacked in the normal direction of one surface of the substrate And an insulating film (40) made of
The electronic device, wherein the material constituting the dummy wiring is the same material as the material constituting the one lead wiring. A substrate (10) having one surface (10a),
A coil (21, 22) formed on one surface side of the substrate and wound with the normal line of the one surface as a center line;
A first electrode pad and a second electrode pad (13 to 16) formed on one side of the substrate;
A first lead-out wiring (25) formed on one surface side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
And a second lead-out wire (24, 26) formed on one side of the substrate to connect the second electrode (20b, 20d) of the coil and the second electrode pad (14, 16). In electronic devices,
Any one of the first and second lead-out lines is made of a conductive material, and a plurality of lead-out line layers (24a to 24a) are stacked in the normal direction of one surface of the substrate. 24d, 25a to 25e, 26a to 26g),
Dummy wirings (30a to 30c, 31a to 31d, 32a to 32e) which are disposed between the one lead wiring and the substrate and are made of a conductive material;
A plurality of insulating layers (40a to 40h) which are disposed between the one lead wire and the substrate, and which are respectively formed of a sintered body of an electrically insulating material and stacked in the normal direction of one surface of the substrate And an insulating film (40) made of
The electronic device whose material which comprises the said dummy wiring is a material smaller than the thermal expansion coefficient of the said insulating layer. Each of the plurality of lead-out wiring layers is composed of a sintered body of the conductive material,
The electronic device according to claim 1, wherein the dummy wiring is formed of a sintered body of the conductive material.   The electronic device according to any one of claims 1 to 3, wherein the dimension in the width direction of the dummy wiring is the same as the dimension in the width direction of the one lead wiring.   The electronic device according to any one of claims 1 to 4, wherein the dimension in the thickness direction of the dummy wiring is the same as the dimension in the thickness direction of the one lead-out wiring. The electrical insulating material constituting the insulating film is polyimide,
The electronic device according to any one of claims 1 to 5, wherein a material forming the dummy wiring is Cu or Ag. It has a coil core (61) which is disposed on the center line side with respect to the coil and made of a magnetic material,
The electronic device according to claim 2, wherein a material forming the dummy wiring is the same material as the coil core. The one lead wire is
An upper wiring (24d) comprising a first wiring portion (51) and a first pad (50) connected to the first wiring portion and having a dimension in the width direction larger than that of the first wiring portion;
A second pad disposed on the substrate side with respect to the upper wiring and connected to a second wiring portion (51) and the second wiring portion and having a dimension in the width direction larger than that of the second wiring portion ( Lower wiring (24c) comprising
The dummy wiring includes a third wiring portion (51) and a third pad (50) connected to the third wiring portion and having a dimension in the width direction larger than that of the third wiring portion.
The first wiring portion, the second wiring portion, and the third wiring portion are respectively formed in the same shape.
The first pad, the second pad, and the third pad are respectively formed in the same shape,
The first pad and the second pad are connected,
The first pad, the second pad, and the third pad are arranged to overlap when viewed from the normal direction,
The electronic device according to any one of claims 1 to 7, wherein the first wiring portion, the second wiring portion, and the third wiring portion are disposed so as to overlap as viewed in the normal direction.   The electronic device according to any one of claims 1 to 8, wherein the insulating layer is formed so as to surround the periphery of the dummy wiring.   10. The one lead wiring and the dummy wiring according to any one of claims 1 to 9, wherein the one lead wiring and the dummy wiring are formed to be orthogonal to the direction of the current flowing in the coil as viewed from the normal direction of one surface of the substrate. Electronic device. The plurality of dummy wirings (30a to 30c, 31a to 31d, and 32a to 32g) are respectively stacked in the normal direction of one surface of the substrate. Electronic device according to one.   12. The electronic device according to claim 11, wherein the one lead-out wiring is formed in a step-like shape by arranging the one lead-out wiring layer to be offset in a direction orthogonal to the normal direction. The first lead-out wiring layer among the plurality of lead-out wiring layers is disposed parallel to the first dummy wiring among the plurality of dummy wirings, and the first lead-out wiring layer and the first dummy wiring are the same. It is formed in one layer,
Let L1 be the widthwise dimension of the first lead-out wiring layer,
Let L2 be the widthwise dimension of the first dummy wiring,
Let S be a dimension between the first lead-out wiring layer and the first dummy wiring,
The electronic device according to claim 12, wherein the plurality of lead-out wiring layers and the plurality of dummy wirings are formed so as to satisfy L1 = L2 = S.   The electronic device according to any one of claims 1 to 13, wherein the dummy wiring is not connected to the one lead wiring. A substrate (10) having one surface (10a),
A coil (21, 22) formed on one surface side of the substrate and wound with the normal line of the one surface as a center line;
A first electrode pad and a second electrode pad (13 to 16) disposed on one side of the substrate;
A first lead-out wiring (25) formed on one surface side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
A second lead-out wire (24, 26) formed on one surface side of the substrate and connecting the second electrode (20b, 20d) of the coil and the second electrode pad (14, 16);
A plurality of dummy wirings (30a to 30m) disposed between the substrate and any one of the first and second lead wirings and the substrate and stacked in the normal direction of one surface of the substrate 30c, 31a-31d, 32a-32e),
An insulating film (40) composed of a plurality of insulating layers (40a to 40h) disposed between the one lead-out wiring and the substrate and stacked in the normal direction of one surface of the substrate; Equipped with
The one lead-out wiring is composed of a plurality of lead-out wiring layers (24a to 24d, 25a to 25e, 26a to 26g) stacked in the normal direction of one surface of the substrate,
A method of manufacturing an electronic device, wherein the same material as the material forming the one lead wiring is used as the material forming the dummy wiring,
A plurality of dummy wirings are stacked by repeatedly forming the dummy wirings on one surface side of the substrate,
A plurality of the lead-out wiring layers are stacked by forming the lead-out wiring layer on one side in the normal direction with respect to the dummy wiring every time the dummy wiring is formed on one surface side of the substrate.
Every time the dummy wiring or the lead-out wiring layer is formed, an electrically insulating paste is applied to one side in the normal direction with respect to the dummy wiring or the lead-out wiring layer formed on one side of the substrate. The manufacturing method of the electronic device which bakes the applied electrically insulating paste for every application | coating, and forms said several insulating film. A substrate (10) having one surface (10a),
A coil (21, 22) formed on one surface side of the substrate and wound with the normal line of the one surface as a center line;
A first electrode pad and a second electrode pad (13 to 16) disposed on one side of the substrate;
A first lead-out wiring (25) formed on one surface side of the substrate and connecting the first electrode (20c) of the coil and the first electrode pad (15);
A second lead-out wire (24, 26) formed on one surface side of the substrate and connecting the second electrode (20b, 20d) of the coil and the second electrode pad (14, 16);
A plurality of dummy wirings (30a to 30m) disposed between the substrate and any one of the first and second lead wirings and the substrate and stacked in the normal direction of one surface of the substrate 30c, 31a-31d, 32a-32e),
An insulating film (40) composed of a plurality of insulating layers (40a to 40h) disposed between the one lead-out wiring and the substrate and stacked in the normal direction of one surface of the substrate; Equipped with
The one lead-out wiring is composed of a plurality of lead-out wiring layers (24a to 24d, 25a to 25e, 26a to 26g) stacked in the normal direction of one surface of the substrate,
A method of manufacturing an electronic device, wherein a material smaller than a thermal expansion coefficient of the insulating film is used as a material forming the dummy wiring.
A plurality of dummy wirings are stacked by repeatedly forming the dummy wirings on one surface side of the substrate,
A plurality of the lead-out wiring layers are stacked by forming the lead-out wiring layer on one side in the normal direction with respect to the dummy wiring every time the dummy wiring is formed on one surface side of the substrate.
Every time the dummy wiring or the lead-out wiring layer is formed, an electrically insulating paste is applied to one side in the normal direction with respect to the dummy wiring or the lead-out wiring layer formed on one side of the substrate. The manufacturing method of the electronic device which bakes the applied electrically insulating paste for every application | coating, and forms said several insulating film. A conductive paste is repeatedly applied to one side of the substrate, and the applied conductive paste is fired for each application, thereby laminating the plurality of dummy wirings.
A conductive paste is applied to one side in the normal direction with respect to the dummy wiring every time the dummy wiring is formed on one surface side of the substrate, and the applied conductive paste is fired for each application. The method of manufacturing an electronic device according to claim 15, wherein a plurality of lead wiring layers are stacked. The coil is composed of a plurality of coil wiring layers (21a to 21d, 22a to 22d) stacked on one side in the normal direction on one side of the substrate,
Any one coil wiring layer among the plurality of coil wiring layers, any one dummy wiring among the plurality of dummy wirings, and any one lead wiring layer among the plurality of lead wiring layers; Are located in the same layer,
A conductive paste is repeatedly applied on one side of the substrate, and the applied conductive paste is fired every application to form the plurality of coil wiring layers.
An application step of applying the conductive paste to form the one coil wiring layer, the one dummy wiring, and the one lead wiring layer formed in the same layer is performed in the same step.
In the same step, a firing step of firing the conductive paste when forming the one coil wiring layer, the one dummy wiring, and the one lead wiring layer formed in the same layer is performed in the same step. 17. The manufacturing method of the electronic device according to 17.

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