WO2015074280A1 - Dispositif de traitement, procédé de traitement et système de communication de flux binaire - Google Patents

Dispositif de traitement, procédé de traitement et système de communication de flux binaire Download PDF

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Publication number
WO2015074280A1
WO2015074280A1 PCT/CN2013/087792 CN2013087792W WO2015074280A1 WO 2015074280 A1 WO2015074280 A1 WO 2015074280A1 CN 2013087792 W CN2013087792 W CN 2013087792W WO 2015074280 A1 WO2015074280 A1 WO 2015074280A1
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Prior art keywords
bitstreams
group
module
carriers
bitstream
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PCT/CN2013/087792
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English (en)
Chinese (zh)
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孙方林
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华为技术有限公司
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Priority to PCT/CN2013/087792 priority Critical patent/WO2015074280A1/fr
Priority to CN201380002682.3A priority patent/CN103843275B/zh
Publication of WO2015074280A1 publication Critical patent/WO2015074280A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/04—Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end

Definitions

  • the present invention relates to the field of information transmission technologies, and in particular, to a bit stream processing device, and to a bit stream processing method and a communication system.
  • Multi-carrier Modulation refers to dividing a data stream into a plurality of parallel sub-streams such that the sub-streams have a much lower transmission bit rate and then modulating the sub-streams onto multiple carriers.
  • Multi-carrier modulation technology including OFDM (Orthogonal Frequency Division) Multiplex, Orthogonal Frequency Division Multiplexing), Wavelet OFDM (Wavelet Orthogonal Frequency Division Multiplexing) or Filter Bank Multi-Carrier (Filter Bank) Multicarrier), etc.
  • OFDM technology is the most widely used multi-carrier modulation technique.
  • a carrier is divided into a number of orthogonal subcarriers, a data stream is converted into a plurality of parallel substreams, and a substream is modulated onto each subcarrier for transmission.
  • ICI can be reduced between subchannels due to the orthogonality between subcarriers (Inter Carrier Interference, inter-carrier interference).
  • Sub-data stream modulation usually includes QAM (Quadrature Amplitude) Modulation, Quadrature Amplitude Modulation), PSK (Phase Shift) Keying, phase shift keying, etc.
  • QAM Quadrature Amplitude Modulation
  • PSK Phase Shift
  • time-frequency domain conversion is generally implemented by fast Fourier transform or inverse transform (FFT/IFFT).
  • FEC Forward Error
  • the data transmission rate is continuously increased, and the bit error rate in the transmission process is put forward higher, and the bit error rate directly affects the effective coding gain of the FEC coding, thereby reducing the data transmission.
  • the bit error rate has become an urgent problem to be solved.
  • the embodiment of the invention provides a bit stream processing device, a processing method and a communication system, which can reduce the bit error rate and improve the effective coding gain.
  • a first aspect of the embodiments of the present invention provides a bitstream processing device, where the processing device includes: an encoding module, configured to perform FEC encoding on a bitstream to obtain an encoded bitstream; and a mapping module, configured to The first set of bitstreams in the bitstream of the encoding module are sequentially mapped onto the first one of the plurality of carriers, Mapping a second set of bitstreams in the bitstream from the encoding module adjacent to the first set of bitstreams to a second one of the plurality of carriers in reverse order, wherein the plurality of carriers Each of the subcarriers corresponds to a set of bitstreams in the bitstream from the encoding module.
  • the encoding module performs, when performing the FEC encoding, encoding, by using a first quantity of bits as a coding unit, where the first quantity is greater than 2.
  • the FEC encoding type used by the encoding module to perform the FEC encoding is a Reed Solomon RS code or BCH code.
  • the mapping module includes: a sorting unit, configured to: The second group of bitstreams are sorted in reverse order; a mapping unit, configured to map the first group of bitstreams and the second group of bitstreams that are sorted in reverse order to the first subcarrier and the second On the subcarrier.
  • the mapping module is specifically configured to alternate between sequential and reverse order A plurality of consecutive sets of bitstreams in the bitstream from the encoding module are mapped into respective sets of subcarriers.
  • the processing device further includes: a constellation module, configured to perform constellation mapping on the mapped subcarriers Obtaining a constellation symbol; a transmitting module for modulating and transmitting a constellation symbol from the constellation module.
  • the bit stream from the encoding module is the encoding a subsequent bit stream; or the bit stream from the encoding module is a bit stream obtained by interleaving the encoded bit stream, wherein the interleaving is performed with a second number of bits as a granularity.
  • a second aspect of the embodiments of the present invention provides a processing device for a bitstream, where the processing device includes: a demapping module, configured to sequentially demap the first of the bitstreams from the first subcarriers of the plurality of carriers. a group bit stream, in which a second group of bitstreams adjacent to the first group of bitstreams in the bitstream are demapped in reverse order from a second one of the plurality of carriers, wherein the first The group bit stream is sequentially mapped on the first subcarrier, and the second group bit stream is mapped on the second subcarrier in reverse order, and each of the plurality of carriers corresponds to the bit stream a set of bitstreams; a decoding module, configured to perform FEC decoding on the bitstream from the demapping module to obtain a decoded bitstream.
  • a demapping module configured to sequentially demap the first of the bitstreams from the first subcarriers of the plurality of carriers.
  • the decoding module performs the FEC decoding, where the first number of bits are used as a decoding unit, where the first quantity is greater than 2.
  • the FEC decoding type used by the decoding module to perform the FEC decoding is a Reed Solomon RS code or BCH code.
  • the demapping module includes: a demapping unit, configured to De-mapping a first set of bitstreams in the bitstream on a first one of the plurality of carriers, and de-mapping the first set of bitstreams in the bitstream from a second one of the plurality of carriers a second set of bitstreams adjacent to each other; a sorting unit for ordering the second set of bitstreams from the demapping unit in order.
  • the demapping module is specifically used from multiple carriers A plurality of sets of subcarriers are alternately used in a sequential and reverse order manner to demap successive sets of bitstreams in the bitstream.
  • the processing device further includes: a receiving module, configured to receive and demodulate a constellation symbol; Performing constellation demapping on the constellation symbols from the receiving module to obtain a plurality of carriers, and outputting the plurality of carriers to the demapping module.
  • the bit stream from the demapping module is a demapped bitstream; or the bitstream from the demapping module is a bitstream obtained after the demapped bitstream is deinterleaved, wherein the deinterleaving is a second number of bits For particle size.
  • a third aspect of the embodiments of the present invention provides a method for processing a bitstream, where the processing method includes: performing FEC encoding on a bitstream to obtain an encoded bitstream; and using a first group of bits in the encoded bitstream.
  • the stream is sequentially mapped to the first one of the plurality of carriers, and the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream are mapped to the plurality of carriers in reverse order And on a second subcarrier, wherein each of the plurality of carriers corresponds to a group of bitstreams from the encoded bitstream.
  • performing the FEC encoding is performed by using a first quantity of bits as a coding unit, where the first quantity is greater than 2.
  • the first group of bit streams in the encoded bit stream are sequentially mapped to a first one of the plurality of carriers And mapping, in reverse order, the second group of bitstreams in the encoded bitstream adjacent to the first group of bitstreams to the second one of the plurality of carriers, including: encoding The second group of bitstreams adjacent to the first group of bitstreams are sorted in reverse order; the first set of bitstreams and the second set of bitstreams sorted by reverse order are respectively mapped to multiple On the first subcarrier and the second subcarrier in the carrier.
  • the first one of the encoded bit streams is The group bit stream is sequentially mapped to the first one of the plurality of carriers, and the second group of bit streams adjacent to the first group of bit streams in the encoded bit stream are mapped to the plurality in reverse order
  • the step of the second subcarrier in the carrier is specifically: alternately using sequential and reverse sequential manners to map consecutive groups of bitstreams in the encoded bitstream to corresponding ones of the plurality of carriers .
  • a fourth aspect of the embodiments of the present invention provides a method for processing a bitstream, where the processing method includes: de-mapping a first group of bitstreams in a bitstream from a first subcarrier of a plurality of carriers, Decoding a second set of bitstreams adjacent to the first set of bitstreams in the bitstream in reverse order on a second one of the plurality of carriers, wherein the first set of bitstreams are sequentially mapped And on the first subcarrier, the second group of bitstreams are mapped on the second subcarrier in reverse order, and each of the plurality of carriers corresponds to a group of bitstreams in the bitstream; FEC decoding is performed on the demapped bit stream to obtain a decoded bit stream.
  • performing the FEC decoding is performed by using a first quantity of bits as a decoding unit, where the first quantity is greater than 2.
  • the first group of bit streams in the bit stream are demapped sequentially from the first one of the plurality of carriers,
  • Decomposing, in a reverse order, a second set of bitstreams in the bitstream adjacent to the first set of bitstreams on a second subcarrier of the plurality of carriers comprises: from a first one of the plurality of carriers Demaping a first set of bitstreams in the bitstream, and de-mapping a second set of bitstreams in the bitstream adjacent to the first set of bitstreams from a second one of the plurality of carriers;
  • the demapped second set of bitstreams are sorted in reverse order.
  • the pressing from the first one of the multiple carriers Demap out a first set of bitstreams in the bitstream, and demap out a second of the bitstreams adjacent to the first set of bitstreams in reverse order from a second one of the plurality of carriers
  • the step of grouping the bit stream is specifically: de-mapping successive sets of bit streams in the bit stream by alternately using sequential and reverse order on multiple sets of subcarriers of the plurality of carriers.
  • a fifth aspect of the embodiments of the present invention provides a communication system, where the communication system includes a sending device and a receiving device, where the sending device includes: an encoding module, configured to perform forward error correction FEC encoding on the bit stream, and obtain the encoding.
  • a mapping module configured to sequentially map the first group of bitstreams in the bitstream from the encoding module to the first one of the plurality of carriers, Mapping a second set of bitstreams in the bitstream from the encoding module adjacent to the first set of bitstreams to a second one of the plurality of carriers in reverse order, wherein the plurality of carriers Each of the subcarriers corresponds to a set of bitstreams in the bitstream from the encoding module; a transmitting module configured to modulate and transmit subcarriers from the mapping module; the receiving device includes: a receiving module, configured to receive And demodulating a set of subcarriers from the plurality of carriers of the transmitting module; a demapping module, configured to sequentially demap the bitstream from the first subcarriers of the plurality of carriers from the receiving module a first set of bitstreams, in reverse order from a second subcarrier of the plurality of carriers from the receiving module, a second set of bitstreams adjacent to the first set
  • the encoding module performs the FEC encoding, where the first number of bits are used as a coding unit, and the decoding module performs the FEC decoding.
  • the encoding is performed with the first number of bits as a decoding unit, wherein the first number is greater than two.
  • the mapping module is specifically configured to use a bit from the encoding module in an alternate order and a reverse order manner. Continuous sets of bitstreams in the stream are mapped into corresponding groups of subcarriers; the demapping module is specifically configured to alternately use sequential and reverse order from multiple sets of subcarriers of the plurality of carriers from the receiving module The manner demaps successive sets of bitstreams in the bitstream.
  • the processing device, the processing method, and the communication system of the bitstream when the FEC-encoded bit stream is mapped to subcarriers in multiple carriers, the first group of bitstreams in the bitstream are sequentially mapped. Going to the first subcarrier, mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarriers in reverse order, since the order and the reverse order are opposite to each other, the high bit error rate in the first group of bitstreams The bits of the bit error and the high bit error rate in the second set of bitstreams will be adjacent to each other.
  • the bits of the high bit error rate in the adjacent two sets of bitstreams will be concentrated in one coding unit, such that Fewer coding units are erroneous, and fewer decoding units are required to correct errors, thereby reducing the bit error rate and increasing the effective coding gain.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a processing apparatus for a bitstream according to the present invention
  • FIG. 2A is a schematic diagram showing a correspondence relationship between a mapping module and a byte after mapping a bit stream in FIG. 1;
  • 2B is a schematic diagram showing a correspondence relationship between a bit stream and a byte after being mapped in the prior art
  • FIG. 3 is a schematic diagram of information mapping of a plurality of sets of bitstreams by the mapping module of FIG. 1;
  • FIG. 4 is a schematic structural diagram of an embodiment of a mapping module of FIG. 1;
  • FIG. 5 is a schematic diagram of an application scenario of the mapping module in FIG. 4; FIG.
  • FIG. 6 is a schematic diagram of another application scenario of the mapping module in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a second embodiment of a processing apparatus for a bitstream according to the present invention.
  • FIG. 8 is a schematic structural diagram of an embodiment of the demapping module of FIG. 7;
  • FIG. 9 is a schematic flow chart of a first embodiment of a method for processing a bitstream according to the present invention.
  • FIG. 10 is a schematic diagram of a specific process of mapping a bit stream according to the present invention.
  • FIG. 11 is a schematic flowchart diagram of a second embodiment of a method for processing a bitstream according to the present invention.
  • FIG. 12 is a schematic diagram of a specific process of demapping a bit stream according to the present invention.
  • FIG. 13 is a schematic structural diagram of a third embodiment of a processing apparatus for a bitstream according to the present invention.
  • FIG. 14 is a schematic structural diagram of a fourth embodiment of a processing apparatus for a bitstream according to the present invention.
  • Figure 15 is a block diagram showing an embodiment of a communication system of the present invention.
  • the techniques described herein can be used in various communication systems, such as current 2G (2nd-generation, third generation mobile communication technology), 3G (3rd-generation, third generation mobile communication technology) communication systems, and next generation communication systems, such as Global System for Mobile Communications (GSM, Global System for Mobile communications), Code Division Multiple Access (CDMA, Code Division Multiple) Access) system, Time Division Multiple Access (TDMA) system, Wideband Code Division Multiple Access (WCDMA, Wideband Code) Division Multiple Access Wireless), Frequency Division Multiple Access (FDMA, Frequency Division Multiple) Addressing) system, orthogonal frequency division multiple access (OFDMA, Orthogonal Frequency-Division Multiple Access) system, single carrier FDMA (SC-FDMA) system, general packet radio service (GPRS, General Packet Radio Service) systems, Long Term Evolution (LTE) systems, and other such communication systems.
  • GSM Global System for Mobile Communications
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • FDMA Wideband Code
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a processing apparatus for a bitstream according to the present invention.
  • the processing device of this embodiment includes an encoding module 11 and a mapping module 13.
  • the processing module may further include an interleaving module 12, a constellation module 14, and a sending module 15, and may further include other modules.
  • the encoding module 11 is configured to perform FEC encoding on the bit stream to obtain an encoded bit stream. Wherein, after performing FEC encoding, redundant bits (also called parity bits) are added to the original bit stream, and there is a specific correspondence between the redundant bits and the original bit stream. When the encoded bit stream needs to be decoded, the error can be detected and corrected by a specific correspondence.
  • the encoding module 11 performs FEC encoding, the encoding is performed by using the first number of bits as the coding unit, where the first quantity is greater than 2.
  • the FEC encoding type used by the encoding module 11 for FEC encoding may be an RS (need-solomon) code or a BCH code.
  • the RS code has a finite field of 2 m , and each coding unit contains information of m bits, and m is greater than 2.
  • the RS code can well correct burst errors in the communication system. Because the error correction capability of the RS code is related to the number of error symbols of the RS code, it has little to do with the number of error bits in a single symbol. Therefore, no matter how many bits of a symbol in the RS code are erroneous, as long as the error correction capability of the RS code is within the range, the implementation of the error correction has little effect.
  • the number of error bits that may be generated is relatively fixed.
  • the error bits are grouped, the number of error bits in some symbols is increased, and the error bits in other symbols are added. The number is reduced, some symbols change from the presence of the error bit to the absence of the error bit, so in general, the centralized error bit can reduce the total number of error symbols, thereby reducing the total number of symbols that need to be corrected, and reducing the correction of the communication system. Wrong request. In the case where the error correction capability of the communication system is determined, concentrating the error bits can reduce the bit error rate to some extent.
  • the FEC encoding type used by the encoding module 11 to perform FEC encoding may also be a block code such as a Hamming code (Block). Codes), can also be TPC (Turbo Product Code, Turbo Product Code), LDPC (Low Density Parity Check) Code, low density parity check code) and other convolutional codes (Convolutional Codes) are not limited here. These coding types are not for the erroneous bits in the coding unit, but only for the coding unit, that is, regardless of how many bits in the coding unit are erroneous, only the coding unit is considered to be in error.
  • the interleaving module 12 is configured to interleave the bitstream from the encoding module 11. Among them, the interleaving is performed with a certain number of bits as the granularity. After the interleaving, the FEC-encoded bit stream will be reordered, so that a burst error that may occur in the communication system becomes a random error.
  • the mapping module 13 is configured to sequentially map the first group of bit streams in the bit stream obtained after the interleaving to the first subcarriers of the plurality of carriers, And mapping a second group of bitstreams adjacent to the first group of bitstreams in the bitstream obtained after the interleaving into a second subcarrier of the plurality of carriers, wherein each of the plurality of carriers corresponds to A set of bitstreams from the bitstream of encoding module 11.
  • the inventors of the present invention found in the long-term research and development that in the OFDM technology, the sub-data streams are mapped onto the sub-carriers in a fixed order. Since the sub-data stream is actually a bit stream, the bit stream is divided into multiple groups, and each group is mapped to a corresponding sub-carrier according to a fixed order from a low bit to a high bit or from a high bit to a low bit.
  • the bit error rate of the bit stream on the subcarrier from the low bit to the high bit is monotonously distributed, that is, the data of the low bit has a higher error than the data of the high bit.
  • the code rate or high bit data has a higher bit error rate than the lower bit data.
  • the receiving end When the receiving end performs FEC decoding, it usually decodes with 1 byte (8 bits) as the decoding unit.
  • the bit with high bit error rate When the subcarrier is in error during transmission, the bit with high bit error rate will be dispersed in different bytes. The receiving end needs to correct each error byte. When the number of bytes in error is large, the bit error rate will increase, and the effective coding gain of the receiving end will also decrease.
  • DSL Digital Subscriber Line, Digital Subscriber Line
  • AWGN Additional White Gaussian Under Noise, additive white Gaussian noise
  • the constellation points on the constellation diagram corresponding to QAM are tested and simulated, and the bit error rate is statistically calculated for each of the 14 bits.
  • the bit error rate carried by each subcarrier exhibits a monotonous characteristic (increment or decrement), and the result is as shown in the table. 1 shows:
  • the error probability of the lowest two bits (0, 1) accounts for 51.6% of all errors. More than half of all errors.
  • the error probability of the highest two bits (12, 13) only accounts for 0.4% of all errors, and its coding gain is much higher than other bits.
  • the first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent, for example, before mapping
  • the first set of bitstreams is the bits of the first bit to the seventh bit of the interleaved bitstream
  • the second set of bitstreams is the bits of the eighth bit to the sixteenth bit of the interleaved bitstream
  • the bits of the seventh bit and the bits of the eighth bit are adjacent.
  • the first set of bitstreams and the second set of bitstreams may contain different numbers of bits, as previously described, the first set of bitstreams includes seven bits and the second set of bitstreams comprises nineteen bits.
  • FIG. 2A is a schematic diagram of the mapping relationship between the mapping module and the byte after the mapping module in FIG. 1
  • FIG. 2B is a schematic diagram of the corresponding relationship between the bit stream and the byte in the prior art.
  • the FEC encoding takes one byte (eight bits) as a coding unit, and the bits of the first group of bit streams and the high bits of the second group of bit streams have a high error rate.
  • the bits of the seventh bit of the first group of bitstream high bit error rate and the bits of the thirteenth bit of the bit error rate of the second group of bitstreams are just in one byte, so that only one Byte error
  • the prior art maps in a fixed ascending order
  • the bits of the seventh bit of the first set of bitstreams are in the first byte
  • the sixteenth of the second set of bitstreams The bits of the bit are in the second byte, so both bytes contain bits with a high bit error rate, so both bytes will fail. It can be seen that the number of bytes of error in the prior art is increased, and the bit error rate is increased.
  • first subcarrier and the second subcarrier of the multiple carriers should be subcarriers with logical locations adjacent to each other, and on this basis, the physical locations may be adjacent. That is, the first subcarrier and the second subcarrier should be adjacent in coding order such that the bits of the seventh bit of the first group of bitstreams and the sixteenth bit of the second set of bitstreams The bits are logically adjacent.
  • the mapping module 11 is specifically configured to map consecutive groups of bit streams in the bit stream obtained after the interleaving into the corresponding groups of subcarriers in an alternate order and a reverse order manner.
  • the interleaved bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are easily understood by those skilled in the art.
  • the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier.
  • the first group of bitstreams are sequentially mapped to the first subcarrier
  • the second group of bitstreams are mapped to the second subcarriers in reverse order
  • the third group of bitstreams are sequentially mapped to the first subcarriers
  • the fourth group The bit stream is mapped to the fourth subcarrier in reverse order
  • the other groups of bit streams are alternately mapped to the corresponding subcarriers in this manner.
  • the bit stream after the mapping is completed is as shown in FIG. 3, wherein the abscissa indicates the grouping order of the bit stream, the ordinate indicates the number of bits of a group of bit streams, and the bar indicates a group of bit streams, and the arrows in the figure indicate a group The ordering direction of the bit stream. As can be seen from the figure, the order of the adjacent two bit streams is reversed.
  • the order may be an ascending order of a low bit to a high bit in a set of bit streams, or may be a descending order opposite to the ascending order.
  • the constellation module 14 is configured to perform constellation mapping on the mapped subcarriers to obtain constellation symbols.
  • Each subcarrier corresponds to a constellation point on the constellation after the constellation mapping, and a constellation point is represented by a constellation symbol. Constellation mapping can improve the anti-interference ability of the communication system.
  • the transmitting module 15 is for modulating and transmitting constellation symbols from the constellation module 14.
  • the processing device may only include an encoding module 11 and a mapping module 13 for performing FEC encoding on the bit stream to obtain an encoded bit stream.
  • the mapping module 13 sequentially maps the first group of bit streams in the bit stream from the encoding module 11 onto the first one of the plurality of carriers, And mapping, in reverse order, a second group of bitstreams in the bitstream from the encoding module 11 that are adjacent to the first group of bitstreams to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to A set of bitstreams in the bitstream of encoding module 11.
  • the bit stream from the encoding module 11 is an encoded bit stream, and the encoded bit stream does not need to be interleaved.
  • the bit stream from the mapping module 11 can be transmitted to other devices by other separate transmitting devices.
  • the first group of bit streams in the bit stream are sequentially mapped to the first sub-carrier.
  • bits of the high bit error rate and the second group in the first group of bitstreams will be adjacent to each other and concentrated in one byte of the FEC encoding, so that fewer bytes are erroneous compared to the prior art, and the number of bytes that need to be corrected during decoding is thus reduced. Therefore, the bit error rate can be reduced and the effective coding gain can be improved.
  • FIG. 4 is a schematic structural diagram of an embodiment of the mapping module in FIG. 1 .
  • the mapping module 13 of the present embodiment includes a sorting unit 131 and a mapping unit 132.
  • the sorting unit 131 is configured to sort the second group of bitstreams in reverse order. After the bit stream is acquired, the sorting unit 131 may divide the bit stream into multiple groups according to the number of bits that each subcarrier can carry, and each group of bit streams corresponds to one subcarrier. The sorting unit 131 takes the initial ordering of the first group of bitstreams as an order, and then the initial ordering of the first group of bitstreams remains unchanged, and the initial ordering of the second group of bitstreams is reversed, for example, The order of a set of bitstreams is from a high bit to a low bit, while the ordering of the second set of bitstreams is from a low bit to a high bit.
  • the mapping unit 132 is configured to map the first group of bitstreams and the second group of bitstreams sorted in reverse order onto the first subcarrier and the second subcarrier, respectively.
  • the bits in the first group of bitstreams sorted by the mapping unit 132 are sequentially mapped onto the first subcarrier, and then the bits in the second group of bitstreams are sequentially mapped onto the second subcarrier.
  • mapping module 13 The specific application scenarios of the mapping module 13 are described in detail below:
  • FIG. 5 is a schematic diagram of an application scenario of the mapping module in FIG. 4 .
  • the sorting unit 131 confirms the number of bits that can be carried by a group of subcarriers among the plurality of carriers according to the bit table (b1, b2, b3, ..., bn), where bn indicates that the nth subcarrier can be carried. The number of bits. Then the number of bits of the nth group of bitstreams is also bn.
  • the sorting unit 131 obtains a first set of bitstreams (u 1 , u 2 , . . . , u b1 ) from the bitstream, where u 1 represents the bits of the first bit and u b1 represents the bits of the b1th bit.
  • the sorting unit 131 sequentially sorts the first group of bit streams (u 1 , u 2 , . . . , u b1 ), and the sorted first group of bit streams (u 1 , u 2 , . . .
  • u b1 becomes (u b1 , u b1-1 ,...,u 1 ); and then obtaining a second set of bit streams (u b1+1 , u b1+2 ,..., u b1+b2 ) from the bit stream, where u b1+1 represents the first
  • the bit of the bit, u b1 + b2 represents the bit of the b2 bit
  • the sorting unit 131 maintains the order of the second set of bit streams (u b1+1 , u b1+2 , ..., u b1 + b2 ) unchanged.
  • the mapping unit 132 maps the sorted first group of bit streams (u b1 , u b1-1 , . . . , u 1 ) onto the first subcarrier, and the mapped first group of bit streams becomes (v b1-1 , v b1 ,...,v 0 ), where v b1-1 corresponds to u 1 and v 0 corresponds to u b1 .
  • a second set of bitstreams (u b1+1 , u b1+2 , . . . , u b1+b2 ) is mapped onto the second subcarrier.
  • the mapped second set of bitstreams becomes (w 0 , w 1 , . . .
  • the sorting unit 131 and the mapping unit 132 sort and map the third group of bit streams and the fourth group of bit streams and the other groups of bit streams in the same manner.
  • FIG. 6 is a schematic diagram of another application scenario of the mapping module in FIG. 5 .
  • the sorting unit 131 still confirms the number of bits that can be carried by a group of subcarriers among the plurality of carriers according to the bit table (b1, b2, b3, ..., bn), where bn indicates that the nth subcarrier can carry The number of bits. Then the number of bits of the nth group of bitstreams is also bn.
  • TCM Troellis
  • the sorting unit 131 obtains a set of bit streams (u 1 , u 2 , . . . , u b1-2 , u b1-1 , u b1 , u b1+1 , u b1+2 , . . . , u b1+b2 from the bit stream. -2 , u b1+b2-1 ), the 3 bits (u b1-1 , u b1 , u b1+1 ) are TCM encoded.
  • u b1-1 is represented by k 3
  • u B1 and u b1+1 are processed by convolutional coding to obtain 3 bits (k 0 , k 1 , k 2 ), and bits (w 0 are obtained according to 4 bits (k 0 , k 1 , k 2 , k 3 ).
  • the original bit stream (u 1 , u 2 ,..., u b1-2 , u b1-1 , u b1 , u b1+1 , u b1+2 ,..., u b1+b2-2 , u b1+b2 -1 ) will become (v 0 , v 1 , ..., v b1-1 , w 0 , w 1 , ..., w b2-1 ) from which the first set of bit streams (v 0 , v 1 ,... , v b1-1 ) and obtaining a second set of bit streams (w 0 , w 1 , . . .
  • the mapping unit 132 maps the sorted first set of bit streams (v b1-1 , v b1-2 , . . . , v 2 , v 1 , v 0 ) onto the first subcarrier.
  • a second set of bitstreams (w 0 , w 1 , w 2 , . . . , w b2-2 , w b2-1 ) is mapped onto the second subcarrier.
  • the bit v 0 on the first subcarrier is adjacent to the bit w 0 on the second subcarrier, and both the bit v 0 and the bit w 0 are bits of a high bit or a low bit.
  • the sorting unit 131 and the mapping unit 132 sort and map the third group of bit streams and the fourth group of bit streams and the other groups of bit streams in the same manner.
  • the sorting unit 131 may keep the ordering of the first group of bitstreams unchanged and reorder the second group of bitstreams.
  • the mapping module 13 does not include the sorting unit 131. That is, the mapping module 13 does not alternate the ordering and the reverse ordering of the first group of bitstreams and the second group of bitstreams, but by the mapping unit 132.
  • the first group of bit streams and the second group of bit streams that are not sorted are respectively mapped to the first subcarrier and the second subcarrier by using the reverse mapping order, and the same effect as the foregoing embodiment can be achieved.
  • FIG. 7 is a schematic structural diagram of a second embodiment of a processing apparatus for a bitstream according to the present invention.
  • the processing device of this embodiment includes a demapping module 23 and a decoding module 25.
  • the receiving module 21, the constellation module 22, and the de-interleaving module 24 may be further included, and of course, other modules may be further included.
  • the receiving module 21 is configured to receive and demodulate constellation symbols.
  • the constellation module 22 is configured to perform constellation demapping on the constellation symbols from the receiving module 21 to obtain a plurality of carriers, and output the plurality of carriers to the demapping module 23.
  • one constellation symbol corresponds to one constellation point on the constellation diagram
  • one constellation point corresponds to one subcarrier.
  • constellation demapping a set of subcarriers of a plurality of carriers can be obtained from constellation symbols.
  • the demapping module 23 is configured to sequentially demap the first group of bitstreams in the bitstream from the first subcarriers of the plurality of carriers, and demap the bitstreams from the second subcarriers of the plurality of carriers in reverse order a second group of bitstreams adjacent to the first set of bitstreams, wherein the first set of bitstreams are sequentially mapped on the first subcarrier, and the second set of bitstreams are mapped in reverse order on the second subcarrier, the plurality of Each subcarrier in the carrier corresponds to a set of bitstreams in the bitstream.
  • the first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent.
  • the first group of bitstreams is the first bit to the seventh bit of the bitstream to be demapped
  • the second set of bitstreams is the eighth bit to the sixteenth of the bitstream to be demapped.
  • the bit of the bit, before performing demapping, the order of the first group of bit streams on the first subcarrier is ascending order of the first bit to the seventh bit
  • the order of the second group of bit streams on the second subcarrier is The descending order of the sixteenth bit to the eighth bit, the bit of the seventh bit and the bit of the sixteenth bit are adjacent.
  • the order of the first group of bitstreams on the first subcarrier is in descending order of the first bit to the seventh bit, and the ordering of the second group of bitstreams on the second subcarrier is the eighth bit to The ascending order of the sixteenth bit, so that the order of the two sets of demapped bitstreams is the original order, that is, from the low bit to the high bit.
  • first subcarrier and the second subcarrier of the multiple carriers should be subcarriers with logical locations adjacent to each other, and on this basis, the physical locations may be adjacent. That is, the first subcarrier and the second subcarrier should be adjacent in the coding order such that the bits of the seventh bit of the first group of bitstreams and the bits of the second group of bitstreams before the demapping The bits of the sixteen bits are logically adjacent.
  • the demapping module 23 is specifically configured to de-map the consecutive groups of bit streams in the bit stream by using sequential and reverse ordering on multiple sets of subcarriers of the multiple carriers.
  • the bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are within the scope of those skilled in the art, Not to elaborate.
  • the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier.
  • the first group of bitstreams are demapped in order
  • the second group of bitstreams are demapped in reverse order
  • the third group of bitstreams are demapped in order
  • the fourth group of bitstreams are demapped in reverse order
  • the other groups of bitstreams are used. This approach alternates between sequential and reverse order demapping.
  • the order may be an ascending order of a low bit to a high bit in a set of bit streams, or may be a descending order opposite to the ascending order.
  • the deinterleaving module 24 is used for deinterleaving the bitstream from the demapping module 23. After deinterleaving, the demapped bitstreams may be sorted in an initial order.
  • the decoding module 25 is configured to perform FEC decoding on the bit stream from the demapping module 24 to obtain a decoded bit stream. Wherein, after performing FEC encoding, errors in the demapped bitstream can be corrected and redundant bits are removed to obtain useful bit information.
  • the decoding module 25 performs decoding during FEC decoding with a certain number of bits as decoding units, wherein the first number is greater than two.
  • the FEC decoding type used by the decoding module 25 to perform FEC decoding may be an RS code or a BCH code.
  • the FEC decoding type used by the decoding module 25 to perform FEC decoding may also be a block code such as a Hamming code, or a convolutional code such as a turbo product code or an LDPC. limited. These decoding types are not for the erroneous bits in the decoding unit, but only for the decoding unit, that is, regardless of how many bits in the decoding unit are erroneous, only the decoding unit is considered to be in error.
  • the bit rate is low.
  • the bits of the adjacent bits, the bits of the first set of bitstreams and the second set of bitstreams are erroneously concentrated in one byte, thereby reducing the number of erroneous bytes.
  • the processing device may only include a demapping module 23 and a decoding module 25, and the demapping module 23 is configured to sequentially demap the first group of the bitstreams from the first one of the plurality of carriers.
  • a bitstream that demaps a second set of bitstreams in the bitstream adjacent to the first set of bitstreams in reverse order from a second one of the plurality of carriers, wherein the first set of bitstreams are sequentially mapped in the first On the subcarrier, the second group of bitstreams are mapped in reverse order on the second subcarrier, and each of the plurality of carriers corresponds to a group of bitstreams in the bitstream.
  • the decoding module 25 is configured to perform FEC decoding on the bit stream from the demapping module 23 to obtain a decoded bit stream. That is to say, the bit stream from the demapping module 23 is the demapped bit stream, that is, the demapped bit stream is directly decoded by the decoding module 25 without deinterleaving. Before the mapping by the demapping module 23, the subcarriers may be received by other separate receiving devices and sent to the demapping module 23.
  • the first group of bitstreams in the bitstream are sequentially mapped on the first subcarrier, and the second group of bitstreams adjacent to the first group of bitstreams are mapped in reverse order.
  • the first group of bitstreams and the bits of the second group of bitstreams are adjacent to each other, and when the first group of bitstreams and the second group of bitstreams are demapped, the first group of bitstreams are sequentially demapped The second group of bitstreams are demapped in reverse order.
  • the bits of the high bit error rate on the adjacent two sets of bitstreams are still adjacent, so that in the FEC decoding, the erroneous bits are concentrated in the FEC decoding.
  • the number of bytes that need to be corrected is reduced, the bit error rate can be reduced, and the effective decoding gain can be improved.
  • FIG. 8 is a schematic structural diagram of an embodiment of the demapping module in FIG. 7 .
  • the demapping module 23 of the present embodiment includes a demapping unit 231 and a sorting unit 232.
  • the demapping unit 231 is configured to demap the first group of bit streams in the bit stream from the first subcarriers of the plurality of carriers, and demap the bit stream from the second subcarrier of the plurality of carriers to be the first A second set of bitstreams adjacent to the group bitstream.
  • Each of the set of subcarriers acquired by the demapping unit 231 carries a set of bitstreams on each subcarrier.
  • the first group of bitstreams are sorted sequentially
  • the second set of bitstreams is sorted in reverse order.
  • the first set of bitstreams is still ordered sequentially.
  • the second set of bitstreams is still sorted in reverse order.
  • the sorting unit 232 is configured to sort the second group of bit streams from the demapping unit 231 in reverse order. Wherein, after sorting, the first group of bit streams and the second group of bit streams are sequentially ordered.
  • the demapping module 23 does not include the sorting unit 232, that is, the demapping module 23 does not alternate the ordering and the reverse ordering of the first set of bitstreams and the second set of bitstreams, but by solving The mapping unit 231 alternately demaps the first group of subcarriers and the second group of subcarriers from the first subcarrier and the second subcarrier by using the reverse demapping sequence, and can achieve the same effect as the foregoing embodiment. Detailed.
  • FIG. 9 is a schematic flowchart of a first embodiment of a method for processing a bitstream according to the present invention.
  • the processing method of the bit stream includes the following steps:
  • the FEC encoding is performed with the first number of bits as the coding unit, wherein the first number is greater than two.
  • the FEC coding type used when performing FEC coding may be an RS code or a BCH code.
  • the FEC encoding type used in the FEC encoding may be a block code such as a Hamming code, or a convolutional code such as a turbo product code or an LDPC, which is not limited herein.
  • coding types are not for the erroneous bits in the coding unit, but only for the coding unit, that is, regardless of how many bits in the coding unit are erroneous, only the coding unit is considered to be in error.
  • S32 Map the first group of bitstreams in the encoded bitstream to the first subcarriers of the plurality of carriers in sequence, and select the second group of bits in the encoded bitstream adjacent to the first group of bitstreams.
  • the stream is mapped in reverse order to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to a set of bitstreams from the encoded bitstream.
  • first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent, for example, before mapping, the first group of bits The stream is the bit from the first bit to the seventh bit in the interleaved bit stream, and the second group bit stream is the bit from the eighth bit to the sixteenth bit in the interleaved bit stream, then the seventh bit The bits and the bits of the eighth bit are adjacent.
  • the first set of bitstreams and the second set of bitstreams may contain different numbers of bits, as previously described, the first set of bitstreams includes seven bits and the second set of bitstreams comprises nineteen bits.
  • the first group of bitstreams on the first subcarrier are sorted in ascending order of the first bit to the seventh bit, and the second set of bitstreams on the second subcarrier are sorted into the sixteenth bit to In the descending order of the eighth bit, the bit of the seventh bit and the bit of the sixteenth bit are adjacent.
  • first subcarrier and the second subcarrier of the multiple carriers should be subcarriers with logical locations adjacent to each other, and on this basis, the physical locations may be adjacent. That is, the first subcarrier and the second subcarrier should be adjacent in coding order such that the bits of the seventh bit of the first group of bitstreams and the sixteenth bit of the second set of bitstreams The bits are logically adjacent.
  • step S32 is specifically: alternately using sequential and reverse order to map consecutive groups of bit streams in the encoded bit stream to corresponding groups of subcarriers of multiple carriers.
  • the interleaved bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are easily understood by those skilled in the art.
  • the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier.
  • the first group of bitstreams are sequentially mapped to the first subcarrier
  • the second group of bitstreams are mapped to the second subcarriers in reverse order
  • the third group of bitstreams are sequentially mapped to the first subcarriers
  • the fourth group The bit stream is mapped to the fourth subcarrier in reverse order
  • the other groups of bit streams are alternately mapped to the corresponding subcarriers in this manner.
  • the order may be an ascending order of a low bit to a high bit in a set of bit streams, or may be a descending order opposite to the ascending order.
  • the processing method further includes: performing constellation mapping on the mapped subcarriers to obtain constellation symbols; and modulating and transmitting the constellation symbols.
  • Each subcarrier corresponds to a constellation point on the constellation after the constellation mapping, and a constellation point is represented by a constellation symbol. Constellation mapping can improve the anti-interference ability of the communication system.
  • the first group of bitstreams in the bitstream are sequentially mapped onto the first subcarrier.
  • mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarriers in reverse order since the order and the reverse order are opposite to each other, the bits of the high bit error rate and the second group in the first group of bitstreams.
  • the bits of high bit error rate in the bitstream will be adjacent to each other and concentrated in one coding unit of FEC coding, so that fewer bytes are erroneous compared to the prior art, and the number of bytes that need to be corrected during decoding is thus reduced. Therefore, the bit error rate can be reduced and the effective coding gain can be improved.
  • Step S32 includes:
  • S321 Sort the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream in reverse order.
  • the bit stream may be divided into multiple groups according to the number of bits that each subcarrier can carry, and each group of bit streams corresponds to one subcarrier.
  • the initial ordering of the first set of bitstreams is taken as an order, then the initial ordering of the first set of bitstreams remains unchanged, no sorting is required, and the initial ordering of the second set of bitstreams is reverse ordered. For example, the ordering of the first set of bitstreams is from a high bit to a low bit, and the ordering of the second set of bitstreams is from a low bit to a high bit.
  • S322 Map the first group of bitstreams and the second group of bitstreams sorted in reverse order to the first subcarriers and the second subcarriers of the plurality of carriers, respectively.
  • bits in the sorted first group of bitstreams are sequentially mapped onto the first subcarrier, and then the bits in the second group of bitstreams are sequentially mapped onto the second subcarrier.
  • FIG. 11 is a schematic flowchart of a second embodiment of a method for processing a bitstream according to the present invention.
  • the processing method of the bit stream includes the following steps:
  • S41 Demap the first group of bitstreams in the bitstream in sequence from the first subcarriers of the plurality of carriers, and demap the bitstreams from the second subcarriers of the plurality of carriers in the reverse order. a second group of bitstreams adjacent to the group bitstream, wherein the first group of bitstreams are sequentially mapped on the first subcarrier, and the second group of bitstreams are mapped in reverse order on the second subcarrier, each of the plurality of carriers Each subcarrier corresponds to a set of bitstreams in the bitstream.
  • the first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent.
  • the first group of bitstreams is the first bit to the seventh bit of the bitstream to be demapped
  • the second set of bitstreams is the eighth bit to the sixteenth of the bitstream to be demapped.
  • the bit of the bit, before performing demapping, the order of the first group of bit streams on the first subcarrier is ascending order of the first bit to the seventh bit
  • the order of the second group of bit streams on the second subcarrier is The descending order of the sixteenth bit to the eighth bit, the bit of the seventh bit and the bit of the sixteenth bit are adjacent.
  • the order of the first group of bitstreams on the first subcarrier is in descending order of the first bit to the seventh bit, and the ordering of the second group of bitstreams on the second subcarrier is the eighth bit to The ascending order of the sixteenth bit, so that the order of the two sets of demapped bitstreams is the original order, that is, from the low bit to the high bit.
  • first subcarrier and the second subcarrier of the multiple carriers should be subcarriers with logical locations adjacent to each other, and on this basis, the physical locations may be adjacent. That is, the first subcarrier and the second subcarrier should be adjacent in the coding order such that the bits of the seventh bit of the first group of bitstreams and the bits of the second group of bitstreams before the demapping The bits of the sixteen bits are logically adjacent.
  • step S41 is specifically: de-mapping successive sets of bitstreams in the bitstream by alternately using sequential and reverse order on multiple sets of subcarriers of the plurality of carriers.
  • the bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are within the scope of those skilled in the art, Not to elaborate.
  • the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier.
  • the first group of bitstreams are demapped in order
  • the second group of bitstreams are demapped in reverse order
  • the third group of bitstreams are demapped in order
  • the fourth group of bitstreams are demapped in reverse order
  • the other groups of bitstreams are used. This approach alternates between sequential and reverse order demapping.
  • the order may be an ascending order of a low bit to a high bit in a set of bit streams, or may be a descending order opposite to the ascending order.
  • S42 Perform FEC decoding on the demapped bitstream to obtain a decoded bitstream.
  • FEC decoding is performed with a certain number of bits as decoding units, wherein the first number is greater than two.
  • the FEC decoding type used when performing FEC decoding may be an RS code or a BCH code.
  • the FEC decoding type used in the FEC decoding may be a block code such as a Hamming code, or a convolutional code such as a turbo product code or an LDPC, which is not limited herein.
  • decoding types are not for the erroneous bits in the decoding unit, but only for the decoding unit, that is, regardless of how many bits in the decoding unit are erroneous, only the decoding unit is considered to be in error.
  • the bit rate is low.
  • the bits of the adjacent bits, the bits of the first set of bitstreams and the second set of bitstreams are erroneously concentrated in one byte, thereby reducing the number of erroneous bytes.
  • the first group of bitstreams in the bitstream are sequentially mapped on the first subcarrier, and the second group of bitstreams adjacent to the first group of bitstreams are mapped in reverse order.
  • the first group of bitstreams and the bits of the second group of bitstreams are adjacent to each other, and when the first group of bitstreams and the second group of bitstreams are demapped, the first group of bitstreams are sequentially demapped The second group of bitstreams are demapped in reverse order.
  • the bits of the high bit error rate on the adjacent two sets of bitstreams are still adjacent, so that in the FEC decoding, the erroneous bits are concentrated in the FEC decoding.
  • the number of bytes that need to be corrected is reduced, the bit error rate can be reduced, and the effective decoding gain can be improved.
  • Step S41 includes:
  • S411 De-mapping a first group of bitstreams in a bitstream from a first one of the plurality of carriers, and de-mapping the second group of the plurality of carriers from the first group of bitstreams The second set of bitstreams of the neighbors.
  • the obtained one of the set of subcarriers carries a set of bitstreams on each of the subcarriers.
  • the first group of bitstreams are sorted sequentially
  • the second set of bitstreams is sorted in reverse order.
  • the first set of bitstreams is still ordered sequentially.
  • the second set of bitstreams is still sorted in reverse order.
  • S412 Sort the demapped second group of bitstreams in reverse order.
  • the first group of bit streams and the second group of bit streams are sequentially ordered.
  • FIG. 13 is a schematic structural diagram of a third embodiment of a processing apparatus for a bitstream according to the present invention.
  • the processing device includes a processor (processer) 51, a memory (memory) 52, and a bus 53. And communication interface (communication Interface)54.
  • the processor 51, the memory 52 and the communication interface 54 are connected to one another via a bus 53.
  • the communication interface 54 is for connection with a subsequent device (not shown).
  • Bus 53 can be a peripheral component interconnection standard (English: Peripheral Component Interconnect, abbreviation: PCI) bus or extended industry standard structure (English: Extended Industry Standard Architecture, abbreviation: EISA) bus, etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in FIG. 13, but it does not mean that there is only one bus or one type of bus.
  • the memory 52 is used to store programs.
  • the program can include program code, the program code including computer operating instructions.
  • Memory 52 may contain high speed random access memory (English: random-access Memory, abbreviation: RAM) memory, may also include non-volatile memory (English: non-volatile memory, abbreviated: NVM), such as at least one disk storage.
  • RAM random-access Memory
  • NVM non-volatile memory
  • the processor 51 may be a central processing unit (English: central processing) Unit, abbreviation: CPU).
  • the processor 51 executes the program stored in the memory 52, and is used to implement the processing method of the bit stream provided by the embodiment of the present invention, including:
  • the reverse order is mapped to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to a set of bitstreams from the encoded bitstream.
  • the first number of bits are used as the coding unit, where the first number is greater than 2.
  • the mapping process specifically includes: sorting the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream in reverse order; and dividing the first group of bitstreams and the second group in reverse order
  • the group bit stream is mapped to the first subcarrier and the second subcarrier of the plurality of carriers, respectively.
  • mapping process is specifically: alternately using sequential and reverse-ordered manners to map consecutive sets of bitstreams in the encoded bitstream to corresponding ones of the plurality of carriers.
  • the communication interface 54 can be integrated or solidified in hardware, which can be a chip, such as an FPGA (Field-Programmable Gate) Array, Field Programmable Gate Array), AISC (Application Specific Integrated) Circuit, ASIC, DSP (Digital Signal Process), ARM (Advanced RISC) Machines, advanced simplification command system set computers) and other chips.
  • FPGA Field-Programmable Gate
  • AISC Application Specific Integrated Circuit
  • ASIC Application Specific Integrated
  • DSP Digital Signal Process
  • ARM Advanced RISC Machines
  • advanced simplification command system set computers advanced simplification command system set computers
  • FIG. 14 is a schematic structural diagram of a fourth embodiment of a processing apparatus for a bitstream according to the present invention.
  • the processing device includes a processor 61, a memory 62, and a bus 63. And communication interface (communication Interface) 64.
  • the processor 61, the memory 62 and the communication interface 64 are connected to one another via a bus 63.
  • the communication interface 64 is used to connect with subsequent devices (not shown).
  • Bus 63 can be a peripheral component interconnect standard (English: Peripheral Component Interconnect, abbreviation: PCI) bus or extended industry standard structure (English: Extended Industry Standard Architecture, abbreviation: EISA) bus, etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 14, but it does not mean that there is only one bus or one type of bus.
  • the memory 62 is used to store programs.
  • the program can include program code, the program code including computer operating instructions.
  • Memory 62 may contain high speed random access memory (English: random-access Memory, abbreviation: RAM) memory, may also include non-volatile memory (English: non-volatile memory, abbreviated: NVM), such as at least one disk storage.
  • RAM random-access Memory
  • NVM non-volatile memory
  • the processor 61 may be a central processing unit (English: central processing) Unit, abbreviation: CPU).
  • the processor 61 executes the program stored in the memory 62, and is used to implement the processing method of the bit stream provided by the embodiment of the present invention, including:
  • FEC decoding is performed on the demapped bit stream to obtain a decoded bit stream.
  • the decoding is performed with the first number of bits as the decoding unit, wherein the first number is greater than 2.
  • the process of demapping specifically includes: de-mapping a first group of bitstreams in the bitstream from a first one of the plurality of carriers, and de-mapping the bits from the second of the plurality of carriers a second set of bitstreams in the stream adjacent to the first set of bitstreams; sorting the demapped second set of bitstreams in reverse order.
  • the demapping process is specifically: de-mapping successive sets of bit streams in the bit stream by using sequential and reverse ordering on multiple sets of subcarriers of the multiple carriers.
  • the communication interface 64 can be integrated or solidified in hardware, which can be a chip, such as an FPGA (Field-Programmable Gate) Array, Field Programmable Gate Array), AISC (Application Specific Integrated) Circuit, ASIC, DSP (Digital Signal Process), ARM (Advanced RISC) Machines, advanced simplification command system set computers) and other chips.
  • FPGA Field-Programmable Gate
  • AISC Application Specific Integrated
  • ASIC Application Specific Integrated
  • DSP Digital Signal Process
  • ARM Advanced RISC
  • the communication system includes a transmitting device including an encoding module 71, a mapping module 72, and a transmitting module 73.
  • the receiving device includes a receiving module 81, a demapping module 82, and a decoding module 83.
  • the encoding module 71 is configured to perform FEC encoding on the bit stream to obtain an encoded bit stream.
  • the mapping module 72 is configured to sequentially map the first group of bit streams in the bit stream from the encoding module 71 onto the first one of the plurality of carriers, And mapping a second group of bitstreams in the bitstream from the encoding module 71 adjacent to the first group of bitstreams to a second one of the plurality of carriers in reverse order, wherein each of the plurality of carriers corresponds to A set of bitstreams in the bitstream of encoding module 71.
  • the transmitting module 73 is configured to modulate and transmit subcarriers from the mapping module 72.
  • the receiving module 81 is configured to receive and demodulate a group of subcarriers from the plurality of carriers of the transmitting module 73.
  • the demapping module 82 is configured to sequentially demap the first group of bitstreams in the bitstream from the first one of the plurality of carriers from the receiving module 81, from the second of the plurality of carriers from the receiving module 81. A second set of bitstreams in the bitstream adjacent to the first set of bitstreams are demapped in reverse order on the subcarriers.
  • the decoding module 83 is configured to perform FEC decoding on the bit stream from the demapping module 82 to obtain a decoded bit stream.
  • the encoding module 71, the mapping module 72, the demapping module 82, and the decoding module 83 of the present embodiment refer to the processing device and the processing method of the bit stream according to any of the preceding embodiments, which are easily understood by those skilled in the art. I will not repeat them here.
  • the processing device, the processing method, and the communication system of the bit stream of the present invention when the FEC-encoded bit stream is mapped to the sub-carriers of the plurality of carriers, sequentially processes the first group of bit streams in the bit stream.
  • mapping to the first subcarrier, mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarrier in reverse order, and demaping the subcarriers before performing FEC decoding, from the first subcarrier Demap the first set of bitstreams in reverse order, and sequentially demap the second set of bitstreams in the bitstream adjacent to the first set of bitstreams from the second subcarriers, since the order and the reverse order are mutually
  • the bits of the high bit error rate in the first set of bitstreams and the bits of the high bit error rate in the second set of bitstreams will be adjacent to each other after encoding and before decoding, if the subcarriers are transmitting errors, high errors.
  • the bit of the rate will be concentrated in one of the encoding/decoding units of the FEC encoding/decoding, so that the number of decoding units that need to be error-corrected at the time of decoding is reduced as compared with the encoding/decoding unit that is erroneous in the prior art, thereby enabling Reduced transmission
  • the bit error rate and improve the effective encoding and decoding gain.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the coupling or direct coupling or communication connection to each other may be an indirect coupling or communication connection through some interface, device or unit, and may be in electrical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • all or part of the technical solution of the present invention may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a computer device (which may be a personal computer, The management server, or network device, etc. or processor, performs all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, and a read only memory (English: read-only Memory, abbreviation: ROM), RAM, disk or optical disc, etc.
  • ROM read only memory
  • RAM disk or optical disc, etc.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un dispositif de traitement, un procédé de traitement et un système de communication d'un flux binaire. Le dispositif de traitement comporte: un module de codage servant à effectuer un codage à FEC sur des flux binaires et à acquérir les flux binaires codés; et un module de transcription servant à transcrire un premier groupe de flux binaires parmi les flux binaires provenant du module de codage sur une première sous-porteuse parmi une pluralité de porteuses dans l'ordre, et à transcrire un deuxième groupe de flux binaires adjacent au premier groupe de flux binaires parmi les flux binaires provenant du module de codage sur une deuxième sous-porteuse parmi la pluralité de porteuses dans l'ordre inverse, chaque sous-porteuse de la pluralité de porteuses correspondant à un groupe de flux binaires parmi les flux binaires provenant du module de codage. La mise en œuvre de la présente invention peut réduire le taux d'erreur sur les bits et améliorer le gain effectif de codage.
PCT/CN2013/087792 2013-11-25 2013-11-25 Dispositif de traitement, procédé de traitement et système de communication de flux binaire WO2015074280A1 (fr)

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CN201380002682.3A CN103843275B (zh) 2013-11-25 2013-11-25 比特流的处理设备、处理方法和通信系统

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CN107465485A (zh) * 2014-09-02 2017-12-12 上海数字电视国家工程研究中心有限公司 编码调制方法以及信息处理方法
CN109075900B (zh) 2016-04-12 2020-10-23 华为技术有限公司 用于信号扩频和复用的方法和设备
US10735143B2 (en) * 2017-11-07 2020-08-04 Huawei Technologies Co., Ltd. System and method for bit mapping in multiple access
CN114553365A (zh) * 2020-11-26 2022-05-27 华为技术有限公司 一种编码方法、解码方法、网络设备、系统以及存储介质
CN112953681B (zh) * 2021-02-20 2022-03-29 Tcl华星光电技术有限公司 解码方法、解码设备及计算机可读存储介质

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