WO2015074280A1

WO2015074280A1 - Processing device, processing method and communication system of bit stream

Info

Publication number: WO2015074280A1
Application number: PCT/CN2013/087792
Authority: WO
Inventors: 孙方林
Original assignee: 华为技术有限公司
Priority date: 2013-11-25
Filing date: 2013-11-25
Publication date: 2015-05-28
Also published as: CN103843275A; CN103843275B

Abstract

Provided are a processing device, processing method and communication system of a bit stream. The processing device comprises: an encoding module for performing FEC encoding on bit streams and acquiring the encoded bit streams; and a mapping module for mapping a first group of bit streams in the bit streams from the encoding module onto a first sub-carrier in a plurality of carriers in sequence, and mapping a second group of bit streams adjacent to the first group of bit streams in the bit streams from the encoding module onto a second sub-carrier in the plurality of carriers in an inverse order, wherein each sub-carrier in the plurality of carriers corresponds to a group of bit streams in the bit streams from the encoding module. The implementation of the present invention can reduce the bit error rate and improve effective encoding gain.

Description

Bit stream processing device, processing method and communication system

【技术领域】[Technical Field]

The present invention relates to the field of information transmission technologies, and in particular, to a bit stream processing device, and to a bit stream processing method and a communication system.

【背景技术】【Background technique】

Multi-carrier modulation of communication systems (Multi-carrier Modulation) refers to dividing a data stream into a plurality of parallel sub-streams such that the sub-streams have a much lower transmission bit rate and then modulating the sub-streams onto multiple carriers.

Multi-carrier modulation technology including OFDM (Orthogonal Frequency Division) Multiplex, Orthogonal Frequency Division Multiplexing), Wavelet OFDM (Wavelet Orthogonal Frequency Division Multiplexing) or Filter Bank Multi-Carrier (Filter Bank) Multicarrier), etc., and OFDM technology is the most widely used multi-carrier modulation technique. In OFDM technology, a carrier is divided into a number of orthogonal subcarriers, a data stream is converted into a plurality of parallel substreams, and a substream is modulated onto each subcarrier for transmission. ICI can be reduced between subchannels due to the orthogonality between subcarriers (Inter Carrier Interference, inter-carrier interference). Sub-data stream modulation usually includes QAM (Quadrature Amplitude) Modulation, Quadrature Amplitude Modulation), PSK (Phase Shift) Keying, phase shift keying, etc., time-frequency domain conversion is generally implemented by fast Fourier transform or inverse transform (FFT/IFFT).

In OFDM technology, FEC (Forward Error) is usually performed before subcarrier transmission. Correction, forward error correction coding, so that when an error occurs in the transmission, the receiver can find the error or even correct the error.

In the prior art communication system, the data transmission rate is continuously increased, and the bit error rate in the transmission process is put forward higher, and the bit error rate directly affects the effective coding gain of the FEC coding, thereby reducing the data transmission. The bit error rate has become an urgent problem to be solved.

【发明内容】 [Summary of the Invention]

The embodiment of the invention provides a bit stream processing device, a processing method and a communication system, which can reduce the bit error rate and improve the effective coding gain.

A first aspect of the embodiments of the present invention provides a bitstream processing device, where the processing device includes: an encoding module, configured to perform FEC encoding on a bitstream to obtain an encoded bitstream; and a mapping module, configured to The first set of bitstreams in the bitstream of the encoding module are sequentially mapped onto the first one of the plurality of carriers, Mapping a second set of bitstreams in the bitstream from the encoding module adjacent to the first set of bitstreams to a second one of the plurality of carriers in reverse order, wherein the plurality of carriers Each of the subcarriers corresponds to a set of bitstreams in the bitstream from the encoding module.

In conjunction with the first aspect, in a first possible implementation manner of the first aspect, the encoding module performs, when performing the FEC encoding, encoding, by using a first quantity of bits as a coding unit, where the first quantity is greater than 2.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the FEC encoding type used by the encoding module to perform the FEC encoding is a Reed Solomon RS code or BCH code.

In conjunction with the first aspect, or any one of the first to the second possible implementations, in a third possible implementation of the first aspect, the mapping module includes: a sorting unit, configured to: The second group of bitstreams are sorted in reverse order; a mapping unit, configured to map the first group of bitstreams and the second group of bitstreams that are sorted in reverse order to the first subcarrier and the second On the subcarrier.

In conjunction with the first aspect, or any one of the first to the third possible implementation manners, in a fourth possible implementation manner of the first aspect, the mapping module is specifically configured to alternate between sequential and reverse order A plurality of consecutive sets of bitstreams in the bitstream from the encoding module are mapped into respective sets of subcarriers.

With reference to the fourth possible implementation of the first aspect, in a fifth possible implementation manner of the first aspect, the processing device further includes: a constellation module, configured to perform constellation mapping on the mapped subcarriers Obtaining a constellation symbol; a transmitting module for modulating and transmitting a constellation symbol from the constellation module.

With reference to the first aspect, or any one of the first to fifth possible implementation manners, in a sixth possible implementation manner of the first aspect, the bit stream from the encoding module is the encoding a subsequent bit stream; or the bit stream from the encoding module is a bit stream obtained by interleaving the encoded bit stream, wherein the interleaving is performed with a second number of bits as a granularity.

A second aspect of the embodiments of the present invention provides a processing device for a bitstream, where the processing device includes: a demapping module, configured to sequentially demap the first of the bitstreams from the first subcarriers of the plurality of carriers. a group bit stream, in which a second group of bitstreams adjacent to the first group of bitstreams in the bitstream are demapped in reverse order from a second one of the plurality of carriers, wherein the first The group bit stream is sequentially mapped on the first subcarrier, and the second group bit stream is mapped on the second subcarrier in reverse order, and each of the plurality of carriers corresponds to the bit stream a set of bitstreams; a decoding module, configured to perform FEC decoding on the bitstream from the demapping module to obtain a decoded bitstream.

With reference to the second aspect, in a first possible implementation manner of the second aspect, the decoding module performs the FEC decoding, where the first number of bits are used as a decoding unit, where the first quantity is greater than 2.

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the FEC decoding type used by the decoding module to perform the FEC decoding is a Reed Solomon RS code or BCH code.

With reference to the second aspect, or any one of the first to the second possible implementation manners, in a third possible implementation manner of the second aspect, the demapping module includes: a demapping unit, configured to De-mapping a first set of bitstreams in the bitstream on a first one of the plurality of carriers, and de-mapping the first set of bitstreams in the bitstream from a second one of the plurality of carriers a second set of bitstreams adjacent to each other; a sorting unit for ordering the second set of bitstreams from the demapping unit in order.

With reference to the second aspect, or any one of the first to the third possible implementation manners, in a fourth possible implementation manner of the second aspect, the demapping module is specifically used from multiple carriers A plurality of sets of subcarriers are alternately used in a sequential and reverse order manner to demap successive sets of bitstreams in the bitstream.

With reference to the fourth possible implementation of the second aspect, in a fifth possible implementation manner of the second aspect, the processing device further includes: a receiving module, configured to receive and demodulate a constellation symbol; Performing constellation demapping on the constellation symbols from the receiving module to obtain a plurality of carriers, and outputting the plurality of carriers to the demapping module.

With reference to the second aspect, or any one of the first to fifth possible implementation manners, in a sixth possible implementation manner of the second aspect, the bit stream from the demapping module is a demapped bitstream; or the bitstream from the demapping module is a bitstream obtained after the demapped bitstream is deinterleaved, wherein the deinterleaving is a second number of bits For particle size.

A third aspect of the embodiments of the present invention provides a method for processing a bitstream, where the processing method includes: performing FEC encoding on a bitstream to obtain an encoded bitstream; and using a first group of bits in the encoded bitstream. The stream is sequentially mapped to the first one of the plurality of carriers, and the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream are mapped to the plurality of carriers in reverse order And on a second subcarrier, wherein each of the plurality of carriers corresponds to a group of bitstreams from the encoded bitstream.

In conjunction with the third aspect, in a first possible implementation manner of the third aspect, performing the FEC encoding is performed by using a first quantity of bits as a coding unit, where the first quantity is greater than 2.

With reference to the third aspect, in a second possible implementation manner of the third aspect, the first group of bit streams in the encoded bit stream are sequentially mapped to a first one of the plurality of carriers And mapping, in reverse order, the second group of bitstreams in the encoded bitstream adjacent to the first group of bitstreams to the second one of the plurality of carriers, including: encoding The second group of bitstreams adjacent to the first group of bitstreams are sorted in reverse order; the first set of bitstreams and the second set of bitstreams sorted by reverse order are respectively mapped to multiple On the first subcarrier and the second subcarrier in the carrier.

With reference to the third aspect, or any one of the first to the second possible implementation manners, in a third possible implementation manner of the third aspect, the first one of the encoded bit streams is The group bit stream is sequentially mapped to the first one of the plurality of carriers, and the second group of bit streams adjacent to the first group of bit streams in the encoded bit stream are mapped to the plurality in reverse order The step of the second subcarrier in the carrier is specifically: alternately using sequential and reverse sequential manners to map consecutive groups of bitstreams in the encoded bitstream to corresponding ones of the plurality of carriers .

A fourth aspect of the embodiments of the present invention provides a method for processing a bitstream, where the processing method includes: de-mapping a first group of bitstreams in a bitstream from a first subcarrier of a plurality of carriers, Decoding a second set of bitstreams adjacent to the first set of bitstreams in the bitstream in reverse order on a second one of the plurality of carriers, wherein the first set of bitstreams are sequentially mapped And on the first subcarrier, the second group of bitstreams are mapped on the second subcarrier in reverse order, and each of the plurality of carriers corresponds to a group of bitstreams in the bitstream; FEC decoding is performed on the demapped bit stream to obtain a decoded bit stream.

With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect, performing the FEC decoding is performed by using a first quantity of bits as a decoding unit, where the first quantity is greater than 2.

With reference to the fourth aspect, in a second possible implementation manner of the fourth aspect, the first group of bit streams in the bit stream are demapped sequentially from the first one of the plurality of carriers, Decomposing, in a reverse order, a second set of bitstreams in the bitstream adjacent to the first set of bitstreams on a second subcarrier of the plurality of carriers comprises: from a first one of the plurality of carriers Demaping a first set of bitstreams in the bitstream, and de-mapping a second set of bitstreams in the bitstream adjacent to the first set of bitstreams from a second one of the plurality of carriers; The demapped second set of bitstreams are sorted in reverse order.

With reference to the fourth aspect, or any one of the first to the second possible implementation manners, in a third possible implementation manner of the fourth aspect, the pressing from the first one of the multiple carriers Demap out a first set of bitstreams in the bitstream, and demap out a second of the bitstreams adjacent to the first set of bitstreams in reverse order from a second one of the plurality of carriers The step of grouping the bit stream is specifically: de-mapping successive sets of bit streams in the bit stream by alternately using sequential and reverse order on multiple sets of subcarriers of the plurality of carriers.

A fifth aspect of the embodiments of the present invention provides a communication system, where the communication system includes a sending device and a receiving device, where the sending device includes: an encoding module, configured to perform forward error correction FEC encoding on the bit stream, and obtain the encoding. a bit stream; a mapping module, configured to sequentially map the first group of bitstreams in the bitstream from the encoding module to the first one of the plurality of carriers, Mapping a second set of bitstreams in the bitstream from the encoding module adjacent to the first set of bitstreams to a second one of the plurality of carriers in reverse order, wherein the plurality of carriers Each of the subcarriers corresponds to a set of bitstreams in the bitstream from the encoding module; a transmitting module configured to modulate and transmit subcarriers from the mapping module; the receiving device includes: a receiving module, configured to receive And demodulating a set of subcarriers from the plurality of carriers of the transmitting module; a demapping module, configured to sequentially demap the bitstream from the first subcarriers of the plurality of carriers from the receiving module a first set of bitstreams, in reverse order from a second subcarrier of the plurality of carriers from the receiving module, a second set of bitstreams adjacent to the first set of bitstreams in the bitstream a decoding module, configured to perform FEC decoding on the bit stream from the demapping module to obtain a decoded bit stream.

With reference to the fifth aspect, in a first possible implementation manner of the fifth aspect, the encoding module performs the FEC encoding, where the first number of bits are used as a coding unit, and the decoding module performs the FEC decoding. The encoding is performed with the first number of bits as a decoding unit, wherein the first number is greater than two.

With reference to the fifth aspect, or the first possible implementation manner thereof, in a second possible implementation manner of the fifth aspect, the mapping module is specifically configured to use a bit from the encoding module in an alternate order and a reverse order manner. Continuous sets of bitstreams in the stream are mapped into corresponding groups of subcarriers; the demapping module is specifically configured to alternately use sequential and reverse order from multiple sets of subcarriers of the plurality of carriers from the receiving module The manner demaps successive sets of bitstreams in the bitstream.

In the processing device, the processing method, and the communication system of the bitstream according to the embodiment of the present invention, when the FEC-encoded bit stream is mapped to subcarriers in multiple carriers, the first group of bitstreams in the bitstream are sequentially mapped. Going to the first subcarrier, mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarriers in reverse order, since the order and the reverse order are opposite to each other, the high bit error rate in the first group of bitstreams The bits of the bit error and the high bit error rate in the second set of bitstreams will be adjacent to each other. If the subcarriers are erroneously transmitted, the bits of the high bit error rate in the adjacent two sets of bitstreams will be concentrated in one coding unit, such that Fewer coding units are erroneous, and fewer decoding units are required to correct errors, thereby reducing the bit error rate and increasing the effective coding gain.

【附图说明】 [Description of the Drawings]

1 is a schematic structural diagram of a first embodiment of a processing apparatus for a bitstream according to the present invention;

2A is a schematic diagram showing a correspondence relationship between a mapping module and a byte after mapping a bit stream in FIG. 1;

2B is a schematic diagram showing a correspondence relationship between a bit stream and a byte after being mapped in the prior art;

3 is a schematic diagram of information mapping of a plurality of sets of bitstreams by the mapping module of FIG. 1;

4 is a schematic structural diagram of an embodiment of a mapping module of FIG. 1;

FIG. 5 is a schematic diagram of an application scenario of the mapping module in FIG. 4; FIG.

6 is a schematic diagram of another application scenario of the mapping module in FIG. 5;

7 is a schematic structural diagram of a second embodiment of a processing apparatus for a bitstream according to the present invention;

8 is a schematic structural diagram of an embodiment of the demapping module of FIG. 7;

9 is a schematic flow chart of a first embodiment of a method for processing a bitstream according to the present invention;

10 is a schematic diagram of a specific process of mapping a bit stream according to the present invention;

11 is a schematic flowchart diagram of a second embodiment of a method for processing a bitstream according to the present invention;

12 is a schematic diagram of a specific process of demapping a bit stream according to the present invention;

13 is a schematic structural diagram of a third embodiment of a processing apparatus for a bitstream according to the present invention;

14 is a schematic structural diagram of a fourth embodiment of a processing apparatus for a bitstream according to the present invention;

Figure 15 is a block diagram showing an embodiment of a communication system of the present invention.

【具体实施方式】【detailed description】

In the following description, for purposes of illustration and description, reference However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the invention.

The techniques described herein can be used in various communication systems, such as current 2G (2nd-generation, third generation mobile communication technology), 3G (3rd-generation, third generation mobile communication technology) communication systems, and next generation communication systems, such as Global System for Mobile Communications (GSM, Global System for Mobile communications), Code Division Multiple Access (CDMA, Code Division Multiple) Access) system, Time Division Multiple Access (TDMA) system, Wideband Code Division Multiple Access (WCDMA, Wideband Code) Division Multiple Access Wireless), Frequency Division Multiple Access (FDMA, Frequency Division Multiple) Addressing) system, orthogonal frequency division multiple access (OFDMA, Orthogonal Frequency-Division Multiple Access) system, single carrier FDMA (SC-FDMA) system, general packet radio service (GPRS, General Packet Radio Service) systems, Long Term Evolution (LTE) systems, and other such communication systems.

Additionally, the terms "system" and "network" are used interchangeably herein. The term "and/or" in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.

Please refer to FIG. 1, which is a schematic structural diagram of a first embodiment of a processing apparatus for a bitstream according to the present invention. The processing device of this embodiment includes an encoding module 11 and a mapping module 13. Optionally, the processing module may further include an interleaving module 12, a constellation module 14, and a sending module 15, and may further include other modules.

The encoding module 11 is configured to perform FEC encoding on the bit stream to obtain an encoded bit stream. Wherein, after performing FEC encoding, redundant bits (also called parity bits) are added to the original bit stream, and there is a specific correspondence between the redundant bits and the original bit stream. When the encoded bit stream needs to be decoded, the error can be detected and corrected by a specific correspondence. Optionally, when the encoding module 11 performs FEC encoding, the encoding is performed by using the first number of bits as the coding unit, where the first quantity is greater than 2. The FEC encoding type used by the encoding module 11 for FEC encoding may be an RS (need-solomon) code or a BCH code.

In practical applications, the RS code has a finite field of 2 ^m , and each coding unit contains information of m bits, and m is greater than 2. The RS code can well correct burst errors in the communication system. Because the error correction capability of the RS code is related to the number of error symbols of the RS code, it has little to do with the number of error bits in a single symbol. Therefore, no matter how many bits of a symbol in the RS code are erroneous, as long as the error correction capability of the RS code is within the range, the implementation of the error correction has little effect. When carrying data with the same multi-carrier, in general, the number of error bits that may be generated is relatively fixed. If the error bits are grouped, the number of error bits in some symbols is increased, and the error bits in other symbols are added. The number is reduced, some symbols change from the presence of the error bit to the absence of the error bit, so in general, the centralized error bit can reduce the total number of error symbols, thereby reducing the total number of symbols that need to be corrected, and reducing the correction of the communication system. Wrong request. In the case where the error correction capability of the communication system is determined, concentrating the error bits can reduce the bit error rate to some extent.

It should be noted that, in other embodiments, the FEC encoding type used by the encoding module 11 to perform FEC encoding may also be a block code such as a Hamming code (Block). Codes), can also be TPC (Turbo Product Code, Turbo Product Code), LDPC (Low Density Parity Check) Code, low density parity check code) and other convolutional codes (Convolutional Codes) are not limited here. These coding types are not for the erroneous bits in the coding unit, but only for the coding unit, that is, regardless of how many bits in the coding unit are erroneous, only the coding unit is considered to be in error.

The interleaving module 12 is configured to interleave the bitstream from the encoding module 11. Among them, the interleaving is performed with a certain number of bits as the granularity. After the interleaving, the FEC-encoded bit stream will be reordered, so that a burst error that may occur in the communication system becomes a random error.

The mapping module 13 is configured to sequentially map the first group of bit streams in the bit stream obtained after the interleaving to the first subcarriers of the plurality of carriers, And mapping a second group of bitstreams adjacent to the first group of bitstreams in the bitstream obtained after the interleaving into a second subcarrier of the plurality of carriers, wherein each of the plurality of carriers corresponds to A set of bitstreams from the bitstream of encoding module 11.

Among them, the inventors of the present invention found in the long-term research and development that in the OFDM technology, the sub-data streams are mapped onto the sub-carriers in a fixed order. Since the sub-data stream is actually a bit stream, the bit stream is divided into multiple groups, and each group is mapped to a corresponding sub-carrier according to a fixed order from a low bit to a high bit or from a high bit to a low bit. When an error occurs in the transmission of the subcarrier, the bit error rate of the bit stream on the subcarrier from the low bit to the high bit is monotonously distributed, that is, the data of the low bit has a higher error than the data of the high bit. The code rate or high bit data has a higher bit error rate than the lower bit data. When the receiving end performs FEC decoding, it usually decodes with 1 byte (8 bits) as the decoding unit. When the subcarrier is in error during transmission, the bit with high bit error rate will be dispersed in different bytes. The receiving end needs to correct each error byte. When the number of bytes in error is large, the bit error rate will increase, and the effective coding gain of the receiving end will also decrease. With DSL (Digital Subscriber Line, Digital Subscriber Line) Communication system as an example, in AWGN (Additive White Gaussian Under Noise, additive white Gaussian noise, the bits in each subcarrier exhibit a regular error rate distribution, for b=14 (16384) The constellation points on the constellation diagram corresponding to QAM are tested and simulated, and the bit error rate is statistically calculated for each of the 14 bits. The bit error rate carried by each subcarrier exhibits a monotonous characteristic (increment or decrement), and the result is as shown in the table. 1 shows:

Table 1 Simulation results of constellation points

Bit	Number of errors	Specific gravity (bit error rate)
0	210798	0.2586
1	210322	0.2580
2	104143	0.1278
3	104458	0.1282
4	50877	0.0624
5	51161	0.0628
6	24316	0.0298
7	24565	0.0301
8	11146	0.0137
9	11260	0.0138
10	4569	0.0056
11	4573	0.0056
12	1425	0.0017
13	1495	0.0018

As can be seen from Table 1, the error probability of the lowest two bits (0, 1) accounts for 51.6% of all errors. More than half of all errors. The error probability of the highest two bits (12, 13) only accounts for 0.4% of all errors, and its coding gain is much higher than other bits.

In this embodiment, the first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent, for example, before mapping, The first set of bitstreams is the bits of the first bit to the seventh bit of the interleaved bitstream, and the second set of bitstreams is the bits of the eighth bit to the sixteenth bit of the interleaved bitstream, The bits of the seventh bit and the bits of the eighth bit are adjacent. Also, the first set of bitstreams and the second set of bitstreams may contain different numbers of bits, as previously described, the first set of bitstreams includes seven bits and the second set of bitstreams comprises nineteen bits. After mapping, the first group of bitstreams on the first subcarrier are sorted in ascending order of the first bit to the seventh bit, and the second set of bitstreams on the second subcarrier are sorted into the sixteenth bit to In the descending order of the eighth bit, the bit of the seventh bit and the bit of the sixteenth bit are adjacent. Referring to FIG. 2A and FIG. 2B, FIG. 2A is a schematic diagram of the mapping relationship between the mapping module and the byte after the mapping module in FIG. 1, and FIG. 2B is a schematic diagram of the corresponding relationship between the bit stream and the byte in the prior art. Wherein, the FEC encoding takes one byte (eight bits) as a coding unit, and the bits of the first group of bit streams and the high bits of the second group of bit streams have a high error rate. As shown in FIG. 2A, the bits of the seventh bit of the first group of bitstream high bit error rate and the bits of the thirteenth bit of the bit error rate of the second group of bitstreams are just in one byte, so that only one Byte error, as shown in Figure 2B, the prior art maps in a fixed ascending order, the bits of the seventh bit of the first set of bitstreams are in the first byte, and the sixteenth of the second set of bitstreams The bits of the bit are in the second byte, so both bytes contain bits with a high bit error rate, so both bytes will fail. It can be seen that the number of bytes of error in the prior art is increased, and the bit error rate is increased.

Further, the first subcarrier and the second subcarrier of the multiple carriers should be subcarriers with logical locations adjacent to each other, and on this basis, the physical locations may be adjacent. That is, the first subcarrier and the second subcarrier should be adjacent in coding order such that the bits of the seventh bit of the first group of bitstreams and the sixteenth bit of the second set of bitstreams The bits are logically adjacent.

In this embodiment, the mapping module 11 is specifically configured to map consecutive groups of bit streams in the bit stream obtained after the interleaving into the corresponding groups of subcarriers in an alternate order and a reverse order manner. Accordingly, the interleaved bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are easily understood by those skilled in the art. In the scope, not to elaborate. Meanwhile, the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier. Then, the first group of bitstreams are sequentially mapped to the first subcarrier, the second group of bitstreams are mapped to the second subcarriers in reverse order, and the third group of bitstreams are sequentially mapped to the first subcarriers, the fourth group The bit stream is mapped to the fourth subcarrier in reverse order, and the other groups of bit streams are alternately mapped to the corresponding subcarriers in this manner. The bit stream after the mapping is completed is as shown in FIG. 3, wherein the abscissa indicates the grouping order of the bit stream, the ordinate indicates the number of bits of a group of bit streams, and the bar indicates a group of bit streams, and the arrows in the figure indicate a group The ordering direction of the bit stream. As can be seen from the figure, the order of the adjacent two bit streams is reversed.

It should be noted that in this embodiment, not only the order and the reverse order are opposite to each other, but the order may be an ascending order of a low bit to a high bit in a set of bit streams, or may be a descending order opposite to the ascending order.

The constellation module 14 is configured to perform constellation mapping on the mapped subcarriers to obtain constellation symbols. Each subcarrier corresponds to a constellation point on the constellation after the constellation mapping, and a constellation point is represented by a constellation symbol. Constellation mapping can improve the anti-interference ability of the communication system.

The transmitting module 15 is for modulating and transmitting constellation symbols from the constellation module 14.

In a further embodiment, the processing device may only include an encoding module 11 and a mapping module 13 for performing FEC encoding on the bit stream to obtain an encoded bit stream. The mapping module 13 sequentially maps the first group of bit streams in the bit stream from the encoding module 11 onto the first one of the plurality of carriers, And mapping, in reverse order, a second group of bitstreams in the bitstream from the encoding module 11 that are adjacent to the first group of bitstreams to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to A set of bitstreams in the bitstream of encoding module 11. That is to say, the bit stream from the encoding module 11 is an encoded bit stream, and the encoded bit stream does not need to be interleaved. After the mapping module 11 is mapped, the bit stream from the mapping module 11 can be transmitted to other devices by other separate transmitting devices.

In the processing device of the bit stream according to the embodiment of the present invention, when the FEC-encoded bit stream is mapped to the sub-carriers of the plurality of carriers, the first group of bit streams in the bit stream are sequentially mapped to the first sub-carrier. And mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarriers in reverse order, since the order and the reverse order are opposite to each other, the bits of the high bit error rate and the second group in the first group of bitstreams The bits of high bit error rate in the bitstream will be adjacent to each other and concentrated in one byte of the FEC encoding, so that fewer bytes are erroneous compared to the prior art, and the number of bytes that need to be corrected during decoding is thus reduced. Therefore, the bit error rate can be reduced and the effective coding gain can be improved.

Please refer to FIG. 4 , which is a schematic structural diagram of an embodiment of the mapping module in FIG. 1 . The mapping module 13 of the present embodiment includes a sorting unit 131 and a mapping unit 132.

The sorting unit 131 is configured to sort the second group of bitstreams in reverse order. After the bit stream is acquired, the sorting unit 131 may divide the bit stream into multiple groups according to the number of bits that each subcarrier can carry, and each group of bit streams corresponds to one subcarrier. The sorting unit 131 takes the initial ordering of the first group of bitstreams as an order, and then the initial ordering of the first group of bitstreams remains unchanged, and the initial ordering of the second group of bitstreams is reversed, for example, The order of a set of bitstreams is from a high bit to a low bit, while the ordering of the second set of bitstreams is from a low bit to a high bit.

The mapping unit 132 is configured to map the first group of bitstreams and the second group of bitstreams sorted in reverse order onto the first subcarrier and the second subcarrier, respectively. The bits in the first group of bitstreams sorted by the mapping unit 132 are sequentially mapped onto the first subcarrier, and then the bits in the second group of bitstreams are sequentially mapped onto the second subcarrier.

The specific application scenarios of the mapping module 13 are described in detail below:

Please refer to FIG. 5 , which is a schematic diagram of an application scenario of the mapping module in FIG. 4 . In this application scenario, the sorting unit 131 confirms the number of bits that can be carried by a group of subcarriers among the plurality of carriers according to the bit table (b1, b2, b3, ..., bn), where bn indicates that the nth subcarrier can be carried. The number of bits. Then the number of bits of the nth group of bitstreams is also bn.

The sorting unit 131 obtains a first set of bitstreams (u ₁ , u ₂ , . . . , u _b1 ) from the bitstream, where u ₁ represents the bits of the first bit and u _b1 represents the bits of the b1th bit. The sorting unit 131 sequentially sorts the first group of bit streams (u ₁ , u ₂ , . . . , u _b1 ), and the sorted first group of bit streams (u ₁ , u ₂ , . . . , u _b1 ) becomes (u _b1 , u _b1-1 ,...,u ₁ ); and then obtaining a second set of bit streams (u _b1+1 , u _b1+2 ,..., u _b1+b2 ) from the bit stream, where u _b1+1 represents the first The bit of the bit, u _{b1 + b2} represents the bit of the b2 bit, and the sorting unit 131 maintains the order of the second set of bit streams (u _b1+1 , u _b1+2 , ..., u _{b1 + b2} ) unchanged.

The mapping unit 132 maps the sorted first group of bit streams (u _b1 , u _b1-1 , . . . , u ₁ ) onto the first subcarrier, and the mapped first group of bit streams becomes (v _b1-1 , v _b1 ,...,v ₀ ), where v _b1-1 corresponds to u ₁ and v ₀ corresponds to u _b1 . A second set of bitstreams (u _b1+1 , u _b1+2 , . . . , u _b1+b2 ) is mapped onto the second subcarrier. The mapped second set of bitstreams becomes (w ₀ , w ₁ , . . . , w _b2-1 ), where w ₀ corresponds to u _b1+1 and w _b2-1 corresponds to u _b1+b2 . The bit v ₀ on the first subcarrier is adjacent to the bit w ₀ on the second subcarrier, and both the bit v ₀ and the bit w ₀ are bits of a high bit or a low bit. The sorting unit 131 and the mapping unit 132 sort and map the third group of bit streams and the fourth group of bit streams and the other groups of bit streams in the same manner.

Please refer to FIG. 6 , which is a schematic diagram of another application scenario of the mapping module in FIG. 5 . In this application scenario, the sorting unit 131 still confirms the number of bits that can be carried by a group of subcarriers among the plurality of carriers according to the bit table (b1, b2, b3, ..., bn), where bn indicates that the nth subcarrier can carry The number of bits. Then the number of bits of the nth group of bitstreams is also bn. The difference from the previous application scenario is that the sorting unit 131 performs TCM (Trellis) in the process of sorting each group of bitstreams. Coded Modulation, Coding.

The sorting unit 131 obtains a set of bit streams (u ₁ , u ₂ , . . . , u _b1-2 , u _b1-1 , u _b1 , u _b1+1 , u _b1+2 , . . . , u _b1+b2 from the bit stream. _-2 , u _b1+b2-1 ), the 3 bits (u _b1-1 , u _b1 , u _b1+1 ) are TCM encoded. The specific process is that u _{b1-1 is} represented by k ₃ , u _B1 and u _b1+1 are processed by convolutional coding to obtain 3 bits (k ₀ , k ₁ , k ₂ ), and bits (w _{0 are} obtained according to 4 bits (k ₀ , k ₁ , k ₂ , k ₃ ). w ₁ , v ₀ , v ₁ ), where v ₀ =k ₃ , v ₁ = k ₁ ⊕k ₃ , w ₀ = k ₂ ⊕k ₃ , w ₁ = k ₀ ⊕k ₁ ⊕k ₂ ⊕k ₃ .

Then the original bit stream (u ₁ , u ₂ ,..., u _b1-2 , u _b1-1 , u _b1 , u _b1+1 , u _b1+2 ,..., u _b1+b2-2 , u _{b1+b2 -1} ) will become (v ₀ , v ₁ , ..., v _b1-1 , w ₀ , w ₁ , ..., w _b2-1 ) from which the first set of bit streams (v ₀ , v ₁ ,... , v _b1-1 ) and obtaining a second set of bit streams (w ₀ , w ₁ , . . . , w _b2-1 ) _therefrom , the first set of bit streams (v ₀ , v ₁ , . . . , v _b1-1 ) After sorting sequentially, it becomes (v _b1-1 , v _b1-2 , . . . , v ₂ , v ₁ , v ₀ ), and the order of the second group of bit streams (w ₀ , w ₁ , . . . , w _b2-1 ) constant.

The mapping unit 132 maps the sorted first set of bit streams (v _b1-1 , v _b1-2 , . . . , v ₂ , v ₁ , v ₀ ) onto the first subcarrier. A second set of bitstreams (w ₀ , w ₁ , w ₂ , . . . , w _b2-2 , w _b2-1 ) is mapped onto the second subcarrier. The bit v ₀ on the first subcarrier is adjacent to the bit w ₀ on the second subcarrier, and both the bit v ₀ and the bit w ₀ are bits of a high bit or a low bit. The sorting unit 131 and the mapping unit 132 sort and map the third group of bit streams and the fourth group of bit streams and the other groups of bit streams in the same manner.

In the above two application scenarios, the sorting unit 131 may keep the ordering of the first group of bitstreams unchanged and reorder the second group of bitstreams.

In further embodiments, the mapping module 13 does not include the sorting unit 131. That is, the mapping module 13 does not alternate the ordering and the reverse ordering of the first group of bitstreams and the second group of bitstreams, but by the mapping unit 132. The first group of bit streams and the second group of bit streams that are not sorted are respectively mapped to the first subcarrier and the second subcarrier by using the reverse mapping order, and the same effect as the foregoing embodiment can be achieved. Detailed.

Please refer to FIG. 7, which is a schematic structural diagram of a second embodiment of a processing apparatus for a bitstream according to the present invention. The processing device of this embodiment includes a demapping module 23 and a decoding module 25. Optionally, the receiving module 21, the constellation module 22, and the de-interleaving module 24 may be further included, and of course, other modules may be further included.

The receiving module 21 is configured to receive and demodulate constellation symbols.

The constellation module 22 is configured to perform constellation demapping on the constellation symbols from the receiving module 21 to obtain a plurality of carriers, and output the plurality of carriers to the demapping module 23. Wherein, one constellation symbol corresponds to one constellation point on the constellation diagram, and one constellation point corresponds to one subcarrier. By constellation demapping, a set of subcarriers of a plurality of carriers can be obtained from constellation symbols.

The demapping module 23 is configured to sequentially demap the first group of bitstreams in the bitstream from the first subcarriers of the plurality of carriers, and demap the bitstreams from the second subcarriers of the plurality of carriers in reverse order a second group of bitstreams adjacent to the first set of bitstreams, wherein the first set of bitstreams are sequentially mapped on the first subcarrier, and the second set of bitstreams are mapped in reverse order on the second subcarrier, the plurality of Each subcarrier in the carrier corresponds to a set of bitstreams in the bitstream.

Wherein, the first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent. For example, the first group of bitstreams is the first bit to the seventh bit of the bitstream to be demapped, and the second set of bitstreams is the eighth bit to the sixteenth of the bitstream to be demapped. The bit of the bit, before performing demapping, the order of the first group of bit streams on the first subcarrier is ascending order of the first bit to the seventh bit, and the order of the second group of bit streams on the second subcarrier is The descending order of the sixteenth bit to the eighth bit, the bit of the seventh bit and the bit of the sixteenth bit are adjacent. After performing demapping, the order of the first group of bitstreams on the first subcarrier is in descending order of the first bit to the seventh bit, and the ordering of the second group of bitstreams on the second subcarrier is the eighth bit to The ascending order of the sixteenth bit, so that the order of the two sets of demapped bitstreams is the original order, that is, from the low bit to the high bit.

Further, the first subcarrier and the second subcarrier of the multiple carriers should be subcarriers with logical locations adjacent to each other, and on this basis, the physical locations may be adjacent. That is, the first subcarrier and the second subcarrier should be adjacent in the coding order such that the bits of the seventh bit of the first group of bitstreams and the bits of the second group of bitstreams before the demapping The bits of the sixteen bits are logically adjacent.

In this embodiment, optionally, the demapping module 23 is specifically configured to de-map the consecutive groups of bit streams in the bit stream by using sequential and reverse ordering on multiple sets of subcarriers of the multiple carriers. Wherein, the bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are within the scope of those skilled in the art, Not to elaborate. Meanwhile, the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier. Then, the first group of bitstreams are demapped in order, the second group of bitstreams are demapped in reverse order, the third group of bitstreams are demapped in order, the fourth group of bitstreams are demapped in reverse order, and the other groups of bitstreams are used. This approach alternates between sequential and reverse order demapping.

The deinterleaving module 24 is used for deinterleaving the bitstream from the demapping module 23. After deinterleaving, the demapped bitstreams may be sorted in an initial order.

The decoding module 25 is configured to perform FEC decoding on the bit stream from the demapping module 24 to obtain a decoded bit stream. Wherein, after performing FEC encoding, errors in the demapped bitstream can be corrected and redundant bits are removed to obtain useful bit information. Preferably, the decoding module 25 performs decoding during FEC decoding with a certain number of bits as decoding units, wherein the first number is greater than two. The FEC decoding type used by the decoding module 25 to perform FEC decoding may be an RS code or a BCH code.

It should be noted that, in other embodiments, the FEC decoding type used by the decoding module 25 to perform FEC decoding may also be a block code such as a Hamming code, or a convolutional code such as a turbo product code or an LDPC. limited. These decoding types are not for the erroneous bits in the decoding unit, but only for the decoding unit, that is, regardless of how many bits in the decoding unit are erroneous, only the decoding unit is considered to be in error.

After demapping, if the FEC decoding takes one byte as the decoding unit, since the bits in the first group of bitstreams and the bits of the second group of bitstreams with high bit error rate are adjacent, the bit rate is low. The bits of the adjacent bits, the bits of the first set of bitstreams and the second set of bitstreams are erroneously concentrated in one byte, thereby reducing the number of erroneous bytes.

In further embodiments, the processing device may only include a demapping module 23 and a decoding module 25, and the demapping module 23 is configured to sequentially demap the first group of the bitstreams from the first one of the plurality of carriers. a bitstream that demaps a second set of bitstreams in the bitstream adjacent to the first set of bitstreams in reverse order from a second one of the plurality of carriers, wherein the first set of bitstreams are sequentially mapped in the first On the subcarrier, the second group of bitstreams are mapped in reverse order on the second subcarrier, and each of the plurality of carriers corresponds to a group of bitstreams in the bitstream. The decoding module 25 is configured to perform FEC decoding on the bit stream from the demapping module 23 to obtain a decoded bit stream. That is to say, the bit stream from the demapping module 23 is the demapped bit stream, that is, the demapped bit stream is directly decoded by the decoding module 25 without deinterleaving. Before the mapping by the demapping module 23, the subcarriers may be received by other separate receiving devices and sent to the demapping module 23.

In the processing device of the bitstream according to the embodiment of the present invention, the first group of bitstreams in the bitstream are sequentially mapped on the first subcarrier, and the second group of bitstreams adjacent to the first group of bitstreams are mapped in reverse order. On the two subcarriers, the first group of bitstreams and the bits of the second group of bitstreams are adjacent to each other, and when the first group of bitstreams and the second group of bitstreams are demapped, the first group of bitstreams are sequentially demapped The second group of bitstreams are demapped in reverse order. Since the order and the reverse order are opposite to each other, the bits of the high bit error rate on the adjacent two sets of bitstreams are still adjacent, so that in the FEC decoding, the erroneous bits are concentrated in the FEC decoding. In one decoding unit, the number of bytes that need to be corrected is reduced, the bit error rate can be reduced, and the effective decoding gain can be improved.

Please refer to FIG. 8 , which is a schematic structural diagram of an embodiment of the demapping module in FIG. 7 . The demapping module 23 of the present embodiment includes a demapping unit 231 and a sorting unit 232.

The demapping unit 231 is configured to demap the first group of bit streams in the bit stream from the first subcarriers of the plurality of carriers, and demap the bit stream from the second subcarrier of the plurality of carriers to be the first A second set of bitstreams adjacent to the group bitstream. Each of the set of subcarriers acquired by the demapping unit 231 carries a set of bitstreams on each subcarrier. Before demapping, the first group of bitstreams are sorted sequentially The second set of bitstreams is sorted in reverse order. After demapping, the first set of bitstreams is still ordered sequentially. The second set of bitstreams is still sorted in reverse order.

The sorting unit 232 is configured to sort the second group of bit streams from the demapping unit 231 in reverse order. Wherein, after sorting, the first group of bit streams and the second group of bit streams are sequentially ordered.

In further embodiments, the demapping module 23 does not include the sorting unit 232, that is, the demapping module 23 does not alternate the ordering and the reverse ordering of the first set of bitstreams and the second set of bitstreams, but by solving The mapping unit 231 alternately demaps the first group of subcarriers and the second group of subcarriers from the first subcarrier and the second subcarrier by using the reverse demapping sequence, and can achieve the same effect as the foregoing embodiment. Detailed.

Please refer to FIG. 9, which is a schematic flowchart of a first embodiment of a method for processing a bitstream according to the present invention. The processing method of the bit stream includes the following steps:

S31: FEC encoding the bit stream to obtain an encoded bit stream.

Wherein, after performing FEC encoding, redundant bits are added to the original bit stream, and there is a specific correspondence between the redundant bits and the original bit stream. When the encoded bit stream needs to be decoded, the error can be detected and corrected by a specific correspondence. Preferably, the FEC encoding is performed with the first number of bits as the coding unit, wherein the first number is greater than two. The FEC coding type used when performing FEC coding may be an RS code or a BCH code.

It is to be noted that, in other embodiments, the FEC encoding type used in the FEC encoding may be a block code such as a Hamming code, or a convolutional code such as a turbo product code or an LDPC, which is not limited herein. These coding types are not for the erroneous bits in the coding unit, but only for the coding unit, that is, regardless of how many bits in the coding unit are erroneous, only the coding unit is considered to be in error.

S32: Map the first group of bitstreams in the encoded bitstream to the first subcarriers of the plurality of carriers in sequence, and select the second group of bits in the encoded bitstream adjacent to the first group of bitstreams. The stream is mapped in reverse order to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to a set of bitstreams from the encoded bitstream.

Wherein the first group of bitstreams and the second group of bitstreams are adjacent, meaning that the physical and logical positions of the first group of bitstreams and the second group of bitstreams are adjacent, for example, before mapping, the first group of bits The stream is the bit from the first bit to the seventh bit in the interleaved bit stream, and the second group bit stream is the bit from the eighth bit to the sixteenth bit in the interleaved bit stream, then the seventh bit The bits and the bits of the eighth bit are adjacent. Also, the first set of bitstreams and the second set of bitstreams may contain different numbers of bits, as previously described, the first set of bitstreams includes seven bits and the second set of bitstreams comprises nineteen bits. After mapping, the first group of bitstreams on the first subcarrier are sorted in ascending order of the first bit to the seventh bit, and the second set of bitstreams on the second subcarrier are sorted into the sixteenth bit to In the descending order of the eighth bit, the bit of the seventh bit and the bit of the sixteenth bit are adjacent.

In this embodiment, optionally, step S32 is specifically: alternately using sequential and reverse order to map consecutive groups of bit streams in the encoded bit stream to corresponding groups of subcarriers of multiple carriers. in. Accordingly, the interleaved bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are easily understood by those skilled in the art. In the scope, not to elaborate. Meanwhile, the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier. Then, the first group of bitstreams are sequentially mapped to the first subcarrier, the second group of bitstreams are mapped to the second subcarriers in reverse order, and the third group of bitstreams are sequentially mapped to the first subcarriers, the fourth group The bit stream is mapped to the fourth subcarrier in reverse order, and the other groups of bit streams are alternately mapped to the corresponding subcarriers in this manner.

In other embodiments, after step S32, the processing method further includes: performing constellation mapping on the mapped subcarriers to obtain constellation symbols; and modulating and transmitting the constellation symbols. Each subcarrier corresponds to a constellation point on the constellation after the constellation mapping, and a constellation point is represented by a constellation symbol. Constellation mapping can improve the anti-interference ability of the communication system.

In the method for processing a bitstream according to the embodiment of the present invention, when the FEC-encoded bitstream is mapped to subcarriers in multiple carriers, the first group of bitstreams in the bitstream are sequentially mapped onto the first subcarrier. And mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarriers in reverse order, since the order and the reverse order are opposite to each other, the bits of the high bit error rate and the second group in the first group of bitstreams The bits of high bit error rate in the bitstream will be adjacent to each other and concentrated in one coding unit of FEC coding, so that fewer bytes are erroneous compared to the prior art, and the number of bytes that need to be corrected during decoding is thus reduced. Therefore, the bit error rate can be reduced and the effective coding gain can be improved.

Please refer to FIG. 10, which is a schematic flowchart of a specific process of mapping a bit stream according to the present invention. Step S32 includes:

S321: Sort the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream in reverse order.

After obtaining the encoded bit stream, the bit stream may be divided into multiple groups according to the number of bits that each subcarrier can carry, and each group of bit streams corresponds to one subcarrier. The initial ordering of the first set of bitstreams is taken as an order, then the initial ordering of the first set of bitstreams remains unchanged, no sorting is required, and the initial ordering of the second set of bitstreams is reverse ordered. For example, the ordering of the first set of bitstreams is from a high bit to a low bit, and the ordering of the second set of bitstreams is from a low bit to a high bit.

S322: Map the first group of bitstreams and the second group of bitstreams sorted in reverse order to the first subcarriers and the second subcarriers of the plurality of carriers, respectively.

The bits in the sorted first group of bitstreams are sequentially mapped onto the first subcarrier, and then the bits in the second group of bitstreams are sequentially mapped onto the second subcarrier.

Please refer to FIG. 11, which is a schematic flowchart of a second embodiment of a method for processing a bitstream according to the present invention. The processing method of the bit stream includes the following steps:

S41: Demap the first group of bitstreams in the bitstream in sequence from the first subcarriers of the plurality of carriers, and demap the bitstreams from the second subcarriers of the plurality of carriers in the reverse order. a second group of bitstreams adjacent to the group bitstream, wherein the first group of bitstreams are sequentially mapped on the first subcarrier, and the second group of bitstreams are mapped in reverse order on the second subcarrier, each of the plurality of carriers Each subcarrier corresponds to a set of bitstreams in the bitstream.

In this embodiment, optionally, step S41 is specifically: de-mapping successive sets of bitstreams in the bitstream by alternately using sequential and reverse order on multiple sets of subcarriers of the plurality of carriers. Wherein, the bit stream may include a third group of bit streams, a fourth group of bit streams, etc., in addition to the first group of bit streams and the second group of bit streams, which are within the scope of those skilled in the art, Not to elaborate. Meanwhile, the plurality of subcarriers may include a third subcarrier, a fourth subcarrier, and the like in addition to the first subcarrier and the second subcarrier. Then, the first group of bitstreams are demapped in order, the second group of bitstreams are demapped in reverse order, the third group of bitstreams are demapped in order, the fourth group of bitstreams are demapped in reverse order, and the other groups of bitstreams are used. This approach alternates between sequential and reverse order demapping.

S42: Perform FEC decoding on the demapped bitstream to obtain a decoded bitstream.

Wherein, after performing FEC encoding, errors in the demapped bitstream can be corrected and redundant bits are removed to obtain useful bit information. Preferably, FEC decoding is performed with a certain number of bits as decoding units, wherein the first number is greater than two. The FEC decoding type used when performing FEC decoding may be an RS code or a BCH code.

It is to be noted that, in other embodiments, the FEC decoding type used in the FEC decoding may be a block code such as a Hamming code, or a convolutional code such as a turbo product code or an LDPC, which is not limited herein. These decoding types are not for the erroneous bits in the decoding unit, but only for the decoding unit, that is, regardless of how many bits in the decoding unit are erroneous, only the decoding unit is considered to be in error.

In the method for processing a bitstream according to the embodiment of the present invention, the first group of bitstreams in the bitstream are sequentially mapped on the first subcarrier, and the second group of bitstreams adjacent to the first group of bitstreams are mapped in reverse order. On the two subcarriers, the first group of bitstreams and the bits of the second group of bitstreams are adjacent to each other, and when the first group of bitstreams and the second group of bitstreams are demapped, the first group of bitstreams are sequentially demapped The second group of bitstreams are demapped in reverse order. Since the order and the reverse order are opposite to each other, the bits of the high bit error rate on the adjacent two sets of bitstreams are still adjacent, so that in the FEC decoding, the erroneous bits are concentrated in the FEC decoding. In one decoding unit, the number of bytes that need to be corrected is reduced, the bit error rate can be reduced, and the effective decoding gain can be improved.

Please refer to FIG. 12, which is a schematic flowchart of a specific process for de-mapping a bit stream according to the present invention. Step S41 includes:

S411: De-mapping a first group of bitstreams in a bitstream from a first one of the plurality of carriers, and de-mapping the second group of the plurality of carriers from the first group of bitstreams The second set of bitstreams of the neighbors.

The obtained one of the set of subcarriers carries a set of bitstreams on each of the subcarriers. Before demapping, the first group of bitstreams are sorted sequentially The second set of bitstreams is sorted in reverse order. After demapping, the first set of bitstreams is still ordered sequentially. The second set of bitstreams is still sorted in reverse order.

S412: Sort the demapped second group of bitstreams in reverse order.

Wherein, after sorting, the first group of bit streams and the second group of bit streams are sequentially ordered.

Please refer to FIG. 13, which is a schematic structural diagram of a third embodiment of a processing apparatus for a bitstream according to the present invention. The processing device includes a processor (processer) 51, a memory (memory) 52, and a bus 53. And communication interface (communication Interface)54. The processor 51, the memory 52 and the communication interface 54 are connected to one another via a bus 53. The communication interface 54 is for connection with a subsequent device (not shown).

Bus 53 can be a peripheral component interconnection standard (English: Peripheral Component Interconnect, abbreviation: PCI) bus or extended industry standard structure (English: Extended Industry Standard Architecture, abbreviation: EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in FIG. 13, but it does not mean that there is only one bus or one type of bus.

The memory 52 is used to store programs. In particular, the program can include program code, the program code including computer operating instructions. Memory 52 may contain high speed random access memory (English: random-access Memory, abbreviation: RAM) memory, may also include non-volatile memory (English: non-volatile memory, abbreviated: NVM), such as at least one disk storage.

The processor 51 may be a central processing unit (English: central processing) Unit, abbreviation: CPU).

The processor 51 executes the program stored in the memory 52, and is used to implement the processing method of the bit stream provided by the embodiment of the present invention, including:

Performing FEC encoding on the bit stream to obtain an encoded bit stream;

Mapping the first set of bitstreams in the encoded bitstream to the first one of the plurality of carriers in sequence, and pressing the second set of bitstreams in the encoded bitstream adjacent to the first set of bitstreams The reverse order is mapped to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to a set of bitstreams from the encoded bitstream.

Optionally, when the FEC encoding is performed, the first number of bits are used as the coding unit, where the first number is greater than 2.

Optionally, the mapping process specifically includes: sorting the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream in reverse order; and dividing the first group of bitstreams and the second group in reverse order The group bit stream is mapped to the first subcarrier and the second subcarrier of the plurality of carriers, respectively.

Optionally, the mapping process is specifically: alternately using sequential and reverse-ordered manners to map consecutive sets of bitstreams in the encoded bitstream to corresponding ones of the plurality of carriers.

For the specific implementation process of the processor 51, refer to the processing device and the processing method of the bit stream in the foregoing embodiment, and details are not described herein again.

The processor 51, the memory 52, and the bus 53 of this embodiment And the communication interface 54 can be integrated or solidified in hardware, which can be a chip, such as an FPGA (Field-Programmable Gate) Array, Field Programmable Gate Array), AISC (Application Specific Integrated) Circuit, ASIC, DSP (Digital Signal Process), ARM (Advanced RISC) Machines, advanced simplification command system set computers) and other chips.

Referring to FIG. 14, which is a schematic structural diagram of a fourth embodiment of a processing apparatus for a bitstream according to the present invention. The processing device includes a processor 61, a memory 62, and a bus 63. And communication interface (communication Interface) 64. The processor 61, the memory 62 and the communication interface 64 are connected to one another via a bus 63. The communication interface 64 is used to connect with subsequent devices (not shown).

Bus 63 can be a peripheral component interconnect standard (English: Peripheral Component Interconnect, abbreviation: PCI) bus or extended industry standard structure (English: Extended Industry Standard Architecture, abbreviation: EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 14, but it does not mean that there is only one bus or one type of bus.

The memory 62 is used to store programs. In particular, the program can include program code, the program code including computer operating instructions. Memory 62 may contain high speed random access memory (English: random-access Memory, abbreviation: RAM) memory, may also include non-volatile memory (English: non-volatile memory, abbreviated: NVM), such as at least one disk storage.

The processor 61 may be a central processing unit (English: central processing) Unit, abbreviation: CPU).

The processor 61 executes the program stored in the memory 62, and is used to implement the processing method of the bit stream provided by the embodiment of the present invention, including:

Demap the first group of bitstreams in the bitstream sequentially from the first subcarriers of the plurality of carriers, and demap the bitstreams from the first group of bits in a reverse order from the second of the plurality of carriers Flowing a second set of bitstreams adjacent to each other, wherein the first set of bitstreams are sequentially mapped on the first subcarrier, and the second set of bitstreams are mapped in reverse order on the second subcarrier, each of the plurality of carriers Corresponding to a set of bitstreams in the bitstream;

FEC decoding is performed on the demapped bit stream to obtain a decoded bit stream.

Optionally, when the FEC decoding is performed, the decoding is performed with the first number of bits as the decoding unit, wherein the first number is greater than 2.

Optionally, the process of demapping specifically includes: de-mapping a first group of bitstreams in the bitstream from a first one of the plurality of carriers, and de-mapping the bits from the second of the plurality of carriers a second set of bitstreams in the stream adjacent to the first set of bitstreams; sorting the demapped second set of bitstreams in reverse order.

Optionally, the demapping process is specifically: de-mapping successive sets of bit streams in the bit stream by using sequential and reverse ordering on multiple sets of subcarriers of the multiple carriers.

For the specific implementation process of the processor 61, refer to the processing device and the processing method of the bit stream in the foregoing embodiment, and details are not described herein again.

The processor 61, the memory 62, and the bus 63 of this embodiment And the communication interface 64 can be integrated or solidified in hardware, which can be a chip, such as an FPGA (Field-Programmable Gate) Array, Field Programmable Gate Array), AISC (Application Specific Integrated) Circuit, ASIC, DSP (Digital Signal Process), ARM (Advanced RISC) Machines, advanced simplification command system set computers) and other chips.

Referring to FIG. 15, which is a schematic structural diagram of an embodiment of a communication system according to the present invention. The communication system includes a transmitting device including an encoding module 71, a mapping module 72, and a transmitting module 73. The receiving device includes a receiving module 81, a demapping module 82, and a decoding module 83.

The encoding module 71 is configured to perform FEC encoding on the bit stream to obtain an encoded bit stream.

The mapping module 72 is configured to sequentially map the first group of bit streams in the bit stream from the encoding module 71 onto the first one of the plurality of carriers, And mapping a second group of bitstreams in the bitstream from the encoding module 71 adjacent to the first group of bitstreams to a second one of the plurality of carriers in reverse order, wherein each of the plurality of carriers corresponds to A set of bitstreams in the bitstream of encoding module 71.

The transmitting module 73 is configured to modulate and transmit subcarriers from the mapping module 72.

The receiving module 81 is configured to receive and demodulate a group of subcarriers from the plurality of carriers of the transmitting module 73.

The demapping module 82 is configured to sequentially demap the first group of bitstreams in the bitstream from the first one of the plurality of carriers from the receiving module 81, from the second of the plurality of carriers from the receiving module 81. A second set of bitstreams in the bitstream adjacent to the first set of bitstreams are demapped in reverse order on the subcarriers.

The decoding module 83 is configured to perform FEC decoding on the bit stream from the demapping module 82 to obtain a decoded bit stream.

For the encoding module 71, the mapping module 72, the demapping module 82, and the decoding module 83 of the present embodiment, refer to the processing device and the processing method of the bit stream according to any of the preceding embodiments, which are easily understood by those skilled in the art. I will not repeat them here.

In the above manner, the processing device, the processing method, and the communication system of the bit stream of the present invention, when the FEC-encoded bit stream is mapped to the sub-carriers of the plurality of carriers, sequentially processes the first group of bit streams in the bit stream. Mapping to the first subcarrier, mapping the second group of bitstreams adjacent to the first group of bitstreams to the second subcarrier in reverse order, and demaping the subcarriers before performing FEC decoding, from the first subcarrier Demap the first set of bitstreams in reverse order, and sequentially demap the second set of bitstreams in the bitstream adjacent to the first set of bitstreams from the second subcarriers, since the order and the reverse order are mutually Conversely, the bits of the high bit error rate in the first set of bitstreams and the bits of the high bit error rate in the second set of bitstreams will be adjacent to each other after encoding and before decoding, if the subcarriers are transmitting errors, high errors. The bit of the rate will be concentrated in one of the encoding/decoding units of the FEC encoding/decoding, so that the number of decoding units that need to be error-corrected at the time of decoding is reduced as compared with the encoding/decoding unit that is erroneous in the prior art, thereby enabling Reduced transmission The bit error rate and improve the effective encoding and decoding gain.

In the several embodiments provided by the present invention, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed. Alternatively, the coupling or direct coupling or communication connection to each other may be an indirect coupling or communication connection through some interface, device or unit, and may be in electrical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the technical solution of the present invention may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a computer device (which may be a personal computer, The management server, or network device, etc. or processor, performs all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, and a read only memory (English: read-only Memory, abbreviation: ROM), RAM, disk or optical disc, etc. Various media that can store program code.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation of the present invention and the contents of the drawings may be directly or indirectly applied to other related technologies. The fields are all included in the scope of patent protection of the present invention.

Claims

A processing device for a bit stream, the processing device comprising:

An encoding module, configured to perform forward error correction FEC encoding on the bit stream to obtain an encoded bit stream;

a mapping module, configured to sequentially map the first group of bitstreams in the bitstream from the encoding module to the first one of the plurality of carriers, Mapping a second set of bitstreams in the bitstream from the encoding module adjacent to the first set of bitstreams to a second one of the plurality of carriers in reverse order, wherein the plurality of carriers Each of the subcarriers corresponds to a set of bitstreams in the bitstream from the encoding module.
The processing device according to claim 1, wherein the encoding module performs encoding of the FEC encoding with a first number of bits as a coding unit, wherein the first number is greater than two.
The processing device according to claim 2, wherein the FEC encoding type used by the encoding module to perform the FEC encoding is a Reed Solomon RS code or a BCH code.
The processing device according to any one of claims 1 to 3, wherein the mapping module comprises:

a sorting unit, configured to sort the second group of bitstreams in reverse order;

And a mapping unit, configured to map the first group of bitstreams and the second group of bitstreams that are sorted in reverse order onto the first subcarrier and the second subcarrier, respectively.
The processing device according to any one of claims 1 to 4, wherein the mapping module is specifically configured to alternately use a sequence and a reverse order to continuously contiguous groups of bitstreams in a bitstream from the encoding module. Mapped to the corresponding multiple sets of subcarriers.
The processing device according to claim 5, wherein the processing device further comprises:

a constellation module, configured to perform constellation mapping on the mapped subcarriers to obtain a constellation symbol;

And a sending module, configured to modulate and transmit a constellation symbol from the constellation module.
A processing apparatus according to any one of claims 1 to 6, wherein:

The bit stream from the encoding module is the encoded bit stream;

Alternatively, the bit stream from the encoding module is a bit stream obtained by interleaving the encoded bit stream, wherein the interleaving is performed with a second number of bits as a granularity.
A processing device for a bit stream, the processing device comprising:

a demapping module, configured to sequentially demap a first group of bitstreams in a bitstream from a first one of the plurality of carriers, and demap the packets from the second subcarrier of the plurality of carriers in reverse order a second set of bitstreams in the bitstream adjacent to the first set of bitstreams, wherein the first set of bitstreams are sequentially mapped onto the first subcarrier, the second set of bitstreams Mapping on the second subcarrier in reverse order, each of the plurality of carriers corresponding to a group of bitstreams in the bitstream;

And a decoding module, configured to perform forward error correction FEC decoding on the bit stream from the demapping module to obtain a decoded bit stream.
The processing device according to claim 8, wherein the decoding module performs decoding of the FEC decoding with a first number of bits as a decoding unit, wherein the first number is greater than two.
The processing device according to claim 9, wherein the FEC decoding type used by the decoding module to perform the FEC decoding is a Reed Solomon RS code or a BCH code.
The processing device according to any one of claims 8 to 10, wherein the demapping module comprises:

a demapping unit, configured to demap a first group of bitstreams in the bitstream from a first one of the plurality of carriers, and demap the bitstream from a second one of the plurality of carriers a second set of bitstreams adjacent to the first set of bitstreams;

a sorting unit for ordering the second group of bitstreams from the demapping unit in reverse order.
The processing device according to any one of claims 8 to 11, wherein the demapping module is specifically configured to demap the plurality of subcarriers from a plurality of carriers in an alternate order and a reverse order manner. A contiguous set of bitstreams in a bitstream.
The processing device according to claim 10, wherein the processing device further comprises:

a receiving module, configured to receive and demodulate a constellation symbol;

And a constellation module, configured to perform constellation demapping on constellation symbols from the receiving module, obtain multiple carriers, and output the multiple carriers to the demapping module.
The processing device according to any one of claims 8 to 13, wherein the bit stream from the demapping module is the demapped bit stream;

Or the bit stream from the demapping module is a bit stream obtained after the demapped bit stream is deinterleaved, wherein the deinterleaving is performed by using a second number of bits as a granularity.
A method for processing a bit stream, characterized in that the processing method comprises:

Performing forward error correction FEC encoding on the bit stream to obtain an encoded bit stream;

Mapping the first set of bitstreams in the encoded bitstream to a first one of the plurality of carriers in sequence, and locating the encoded bitstream adjacent to the first set of bitstreams A second set of bitstreams are mapped in reverse order to a second one of the plurality of carriers, wherein each of the plurality of carriers corresponds to a set of bitstreams from the encoded bitstream.
The processing method according to claim 13, wherein the FEC encoding is performed by encoding the first number of bits as a coding unit, wherein the first number is greater than two.
The processing method according to claim 13, wherein the mapping the first group of bitstreams in the encoded bitstream to the first subcarriers of the plurality of carriers in sequence, the encoding The step of mapping the second group of bitstreams adjacent to the first group of bitstreams to the second one of the plurality of carriers in the reverse bitstream includes:

And sorting the second group of bitstreams adjacent to the first group of bitstreams in the encoded bitstream in reverse order;

And mapping the first group of bitstreams and the reverse-ordered second group of bitstreams to first and second subcarriers of the plurality of carriers, respectively.
The processing method according to any one of claims 15 to 17, wherein the first group of bit streams in the encoded bit stream are sequentially mapped onto a first one of a plurality of carriers And the step of mapping the second group of bitstreams in the encoded bitstream adjacent to the first group of bitstreams to the second one of the plurality of carriers in reverse order is specifically:

The successive sets of bitstreams in the encoded bitstream are mapped into corresponding sets of subcarriers of the plurality of carriers alternately using sequential and reverse ordering.
A method for processing a bit stream, characterized in that the processing method comprises:

Dislocating a first group of bitstreams in a bitstream from a first subcarrier of the plurality of carriers, and demaping the bitstreams from a second subcarrier of the plurality of carriers in reverse order a second group of bitstreams adjacent to the first set of bitstreams, wherein the first set of bitstreams are sequentially mapped on the first subcarrier, and the second set of bitstreams are mapped in reverse order And on the second subcarrier, each of the multiple carriers corresponds to a group of bitstreams in the bitstream;

Performing forward error correction FEC decoding on the demapped bit stream to obtain a decoded bit stream.
The processing method according to claim 17, wherein the decoding is performed with the first number of bits as a decoding unit when the FEC decoding is performed, wherein the first number is greater than two.
The processing method according to claim 17, wherein the first group of bitstreams in the bitstream are demapped sequentially from the first one of the plurality of carriers, from the plurality of carriers The step of de-mapping the second group of bitstreams in the bitstream adjacent to the first group of bitstreams in a reverse order on the second subcarrier comprises:

De-mapping a first set of bitstreams in the bitstream from a first one of the plurality of carriers, and de-mapping the first set of bits in the bitstream from a second one of the plurality of carriers Flowing a second set of bitstreams adjacent to each other;

The demapped second set of bitstreams are sorted in reverse order.
The processing method according to any one of claims 19 to 21, wherein the first group of bitstreams in the bitstream are demapped sequentially from the first one of the plurality of carriers, from the The step of de-mapping the second group of bitstreams adjacent to the first group of bitstreams in the bitstream in a reverse order on the second subcarrier of the plurality of carriers is specifically:

A plurality of sets of bitstreams in the bitstream are de-mapped alternately from a plurality of sets of subcarriers of the plurality of carriers in a sequential and reverse order manner.
A communication system, characterized in that the communication system comprises a transmitting device and a receiving device, wherein

The sending device includes:

An encoding module, configured to perform forward error correction FEC encoding on the bit stream to obtain an encoded bit stream;

a mapping module, configured to sequentially map the first group of bitstreams in the bitstream from the encoding module to the first one of the plurality of carriers, Mapping a second set of bitstreams in the bitstream from the encoding module adjacent to the first set of bitstreams to a second one of the plurality of carriers in reverse order, wherein the plurality of carriers Each of the subcarriers corresponds to a set of bitstreams in the bitstream from the encoding module;

a sending module, configured to modulate and transmit a subcarrier from the mapping module;

The receiving device includes:

a receiving module, configured to receive and demodulate a group of subcarriers from the plurality of carriers of the sending module;

a demapping module, configured to sequentially demap a first group of bitstreams in the bitstream from a first one of the plurality of carriers from the receiving module, from among a plurality of carriers from the receiving module Decoding a second set of bitstreams in the bitstream adjacent to the first set of bitstreams in reverse order on the second subcarrier;

And a decoding module, configured to perform FEC decoding on the bit stream from the demapping module to obtain a decoded bit stream.
The communication system according to claim 23, wherein said encoding module performs encoding of said FEC encoding with a first number of bits as a coding unit; said decoding module performs said FEC decoding with said A number of bits are encoded as a decoding unit, wherein the first number is greater than two.
The communication system according to claim 22 or 23, wherein the mapping module is specifically configured to map successive sets of bit streams in the bit stream from the encoding module to corresponding ones in an alternate order and a reverse order manner. Multiple sets of subcarriers;

The demapping module is specifically configured to de-map consecutive groups of bitstreams in the bitstream by using sequential and reverse ordering on multiple sets of subcarriers from the plurality of carriers of the receiving module.