WO2015064562A1 - Dispositif à semi-conducteur bipolaire et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur bipolaire et son procédé de fabrication Download PDF

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WO2015064562A1
WO2015064562A1 PCT/JP2014/078601 JP2014078601W WO2015064562A1 WO 2015064562 A1 WO2015064562 A1 WO 2015064562A1 JP 2014078601 W JP2014078601 W JP 2014078601W WO 2015064562 A1 WO2015064562 A1 WO 2015064562A1
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semiconductor layer
type
impurity concentration
layer
semiconductor
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PCT/JP2014/078601
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English (en)
Japanese (ja)
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哲郎 逸見
中山　浩二
勝則 浅野
秀一 土田
哲哉 宮澤
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一般財団法人電力中央研究所
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Publication of WO2015064562A1 publication Critical patent/WO2015064562A1/fr

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Definitions

  • the present invention relates to a bipolar semiconductor device and a manufacturing method thereof.
  • a SiC semiconductor element is manufactured using a SiC film grown on a SiC substrate by a CVD (chemical vapor deposition) method or the like.
  • CVD chemical vapor deposition
  • a p-type SiC film and an n-type SiC film are alternately grown and laminated.
  • Non-patent Document 1 When carrier recombination is promoted at the pn junction interface, switching loss can be reduced, but steady loss increases.
  • an object of the present invention is to provide a bipolar semiconductor device that can reduce switching loss and suppress increase in steady loss and a method for manufacturing the same.
  • a bipolar semiconductor device of the present invention is A drift layer that is a silicon carbide semiconductor of the first conductivity type; A first semiconductor layer that is a silicon carbide semiconductor of a second conductivity type formed on the drift layer; Of the second semiconductor layer of the first conductivity type formed between the drift layer and the first semiconductor layer or on the side opposite to the first semiconductor layer with respect to the drift layer, Comprising at least the drift layer and the first semiconductor layer; Recombination promotion that promotes carrier recombination in at least one of the first semiconductor layer, the drift layer, the second semiconductor layer, and the interface between the drift layer and the second semiconductor layer.
  • Recombination promotion that promotes carrier recombination in at least one of the first semiconductor layer, the drift layer, the second semiconductor layer, and the interface between the drift layer and the second semiconductor layer.
  • Has a surface A recombination promoting surface is not formed at the interface between the first semiconductor layer and the drift layer or the interface between the first semiconductor layer and the second semiconductor layer.
  • the bipolar semiconductor device of the present invention when the first semiconductor layer and the drift layer are provided, recombination promotion that promotes carrier recombination in the first semiconductor layer excluding the interface between the first semiconductor layer and the drift layer.
  • recombination promotion that promotes carrier recombination in the first semiconductor layer excluding the interface between the first semiconductor layer and the drift layer.
  • the first semiconductor layer, the drift layer, and the second semiconductor layer are provided, the first semiconductor layer, the drift layer, the second semiconductor layer, and the interface between the drift layer and the second semiconductor layer Since at least one of these is a recombination promoting surface, switching loss can be reduced, and carriers at a pn junction interface formed of a drift layer or a second semiconductor layer of a conductivity type different from that of the first semiconductor layer and the semiconductor layer can be reduced. Recombination is suppressed, carrier injection efficiency into the drift layer can be kept high, and an increase in steady loss can be suppressed.
  • the layer that forms the pn junction interface is continuously grown and the pn junction interface is used as the continuous growth interface, so that it is possible to reduce the steady loss while reducing the switching loss. become.
  • the second semiconductor layer is formed between the drift layer and the first semiconductor layer, A recombination promoting surface that promotes carrier recombination is formed at the interface between the drift layer and the second semiconductor layer.
  • the switching loss can be reduced, and the first semiconductor layer and the first semiconductor layer having different conductivity types can be reduced. Recombination of carriers at the pn junction interface formed by two semiconductor layers can be suppressed.
  • the second semiconductor layer includes Formed between the drift layer and the first semiconductor layer; A first semiconductor layer portion formed to be continuous with the drift layer; A second semiconductor layer portion formed so as to be continuous with the first semiconductor layer portion, The drift layer has a first impurity concentration; The first semiconductor layer portion of the second semiconductor layer has a thickness of less than 100 nm, and has reached the second impurity concentration at the end on the second semiconductor layer portion side, and between the lower end and the upper end.
  • the second semiconductor layer portion of the second semiconductor layer has the second impurity concentration and The third impurity concentration is 10 times the second impurity concentration or 1/10 or less of the second impurity concentration;
  • a recombination promoting surface that promotes carrier recombination is formed in the first semiconductor layer portion of the second semiconductor layer.
  • the second impurity concentration is reached from the third impurity concentration which differs from the second impurity concentration by one digit or more.
  • a discontinuous growth surface in which the impurity concentration changes sharply is formed in the first semiconductor layer portion of the second semiconductor layer.
  • This discontinuous growth surface serves as a recombination promoting surface that promotes carrier recombination.
  • the semiconductor layer is A first semiconductor layer portion formed to be continuous with the drift layer, or formed to be continuous with an intermediate layer formed on the drift layer; A second semiconductor layer portion formed so as to be continuous with the first semiconductor layer portion; A third semiconductor layer portion formed so as to be continuous with the second semiconductor layer portion, The first, second, and third semiconductor layer portions have the same conductivity type and different conductivity types from the drift layer, The first semiconductor layer portion of the first semiconductor layer has a first impurity concentration; The second semiconductor layer portion of the first semiconductor layer has a thickness of less than 100 nm, reaches the second impurity concentration at the end on the third semiconductor layer portion side, and has a lower end and an upper end.
  • a third impurity concentration different from the second impurity concentration between, The third semiconductor layer portion of the first semiconductor layer has the second impurity concentration,
  • the third impurity concentration is 10 times or more of the second impurity concentration or 1/10 or less of the second impurity concentration;
  • the recombination promoting surface is provided in the second semiconductor layer portion of the first semiconductor layer.
  • the second impurity concentration is reached from the third impurity concentration different from the second impurity concentration by one digit or more. Yes.
  • a discontinuous growth surface in which the impurity concentration changes sharply is formed in the second semiconductor layer portion.
  • This discontinuous growth surface serves as a recombination promoting surface that promotes carrier recombination.
  • the first semiconductor layer composed of the first, second, and third semiconductor layer portions having the same conductivity type has a discontinuous growth surface in the second semiconductor layer portion, and this discontinuous growth surface.
  • the carrier injection efficiency into the drift layer can be kept high, and the increase in steady loss can be suppressed.
  • the first impurity concentration and the second impurity concentration are different from each other.
  • the interface between the first semiconductor layer portion and the second semiconductor layer portion of the first semiconductor layer is a discontinuous growth surface, so that switching loss can be reduced and increase in steady loss can be suppressed.
  • the first impurity concentration and the second impurity concentration are substantially the same.
  • the second semiconductor layer portion of the first semiconductor layer having the first impurity concentration has a discontinuous growth surface, switching loss can be reduced and increase in steady loss can be suppressed. it can.
  • the first semiconductor layer is After the source gas is supplied to the crystal growth surface to form the first semiconductor layer portion, the supply of the source gas is stopped for one minute or more, and then the source gas is supplied to form the second semiconductor layer portion and The third semiconductor layer portion is formed.
  • the second semiconductor layer portion of the first semiconductor layer formed after the supply of the source gas is stopped for 1 minute or longer, and the first semiconductor layer portion and the second semiconductor layer portion having the same conductivity type are formed.
  • the interface with the semiconductor layer portion can be a discontinuous growth surface. Therefore, according to this embodiment, the switching loss can be reduced and the pn can be reduced as compared with the case where the interface between the first semiconductor layer portion and the second semiconductor layer portion of the first semiconductor layer is a continuous growth surface. Compared with the case where the junction interface is a discontinuous growth surface, the carrier injection efficiency into the drift layer can be kept high, and an increase in steady loss can be suppressed.
  • the first semiconductor layer is After supplying the source gas to the crystal growth surface and forming the first semiconductor layer portion at a predetermined growth rate, the source gas is supplied in advance after the silicon carbide growth rate is reduced to zero for 1 minute or more.
  • the second semiconductor layer portion and the third semiconductor layer portion are formed at a predetermined growth rate.
  • the discontinuous growth surface is formed in the second semiconductor layer portion of the first semiconductor layer formed after the growth rate of silicon carbide is set to zero for 1 minute or more, so that switching loss can be reduced and steady state can be achieved. An increase in loss can be suppressed.
  • the first semiconductor layer is After supplying the source gas to the crystal growth surface and forming the first semiconductor layer portion at an ambient temperature of 1500 ° C. or higher, the ambient temperature is lowered to 1400 ° C. or lower, and then raised again to an ambient temperature of 1500 ° C. or higher.
  • the source gas is supplied by heating to form the second semiconductor layer portion and the third semiconductor layer portion.
  • the atmospheric temperature is lowered by 100 ° C. or higher and then raised again to the atmospheric temperature of 1500 ° C. or higher.
  • the interface between the first semiconductor layer portion and the second semiconductor layer portion can be a discontinuous growth surface.
  • the first semiconductor layer is a diode constituting an anode layer.
  • the first semiconductor layer is a transistor constituting a base layer.
  • the first semiconductor layer is an IGBT constituting an emitter layer.
  • IGBT insulated gate bipolar transistor
  • the first semiconductor layer is a GTO that forms a base layer.
  • GTO gate turn-off thyristor
  • a method for manufacturing the bipolar semiconductor device comprising: Supplying a source gas to the crystal growth surface to form a first semiconductor layer portion of the first semiconductor layer made of a silicon carbide semiconductor and having a first impurity concentration; After forming the first semiconductor layer portion, the supply of the source gas is stopped for 1 minute or more, and then the source gas is supplied. It is formed on the first semiconductor layer portion so as to be continuous with the first semiconductor layer portion, has the same conductivity type as the first semiconductor layer portion, has a thickness of less than 100 nm, and has an upper end.
  • a third semiconductor layer portion of the layer is formed.
  • the second semiconductor layer portion of the first semiconductor layer formed after the supply of the source gas is stopped for 1 minute or more is the same conductivity type.
  • the interface between the first semiconductor layer portion and the second semiconductor layer portion of the semiconductor layer can be a discontinuous growth surface. Therefore, compared with the case where the pn junction interface is a discontinuous growth surface, switching loss can be reduced while suppressing increase in steady loss while maintaining high carrier injection efficiency to the drift layer.
  • a method for manufacturing a bipolar semiconductor device includes: A method for manufacturing the bipolar semiconductor device, comprising: Supplying a source gas to a crystal growth surface at a predetermined supply rate to form a first semiconductor layer portion of the first semiconductor layer made of a silicon carbide semiconductor and having a first impurity concentration; After forming the first semiconductor layer portion, controlling the feed rate of the source gas so that the growth rate of silicon carbide is zero for 1 minute or longer, Supply the source gas at a predetermined supply rate, It is formed on the first semiconductor layer portion so as to be continuous with the first semiconductor layer portion, has the same conductivity type as the first semiconductor layer portion, has a thickness of less than 100 nm, and has an upper end.
  • the first impurity concentration is reached, and the second impurity concentration is 10 times or more of the first impurity concentration or 1/10 or less of the first impurity concentration between the lower end and the upper end.
  • a second semiconductor layer portion of the first semiconductor layer; The first semiconductor is formed on the second semiconductor layer portion so as to be continuous with the second semiconductor layer portion, has the same conductivity type as the second semiconductor layer portion, and has the first impurity concentration.
  • a third semiconductor layer portion of the layer is formed.
  • the discontinuous growth surface is formed in the second semiconductor layer portion of the first semiconductor layer formed after the growth rate of silicon carbide is set to zero for 1 minute or more. Therefore, according to the present invention, the switching loss can be reduced and the pn junction interface can be made to be a discontinuous growth surface as compared with the case where the discontinuous growth surface is not formed in the second semiconductor layer portion of the first semiconductor layer. Compared to the case described above, it is possible to manufacture a bipolar semiconductor device capable of keeping the carrier injection efficiency into the drift layer high and suppressing an increase in steady loss.
  • a method for manufacturing a bipolar semiconductor device includes: A method for manufacturing the bipolar semiconductor device, comprising: A source gas is supplied to the crystal growth surface to form a first semiconductor layer portion of the first semiconductor layer made of a silicon carbide semiconductor and having a first impurity concentration at an ambient temperature of 1500 ° C. or higher. , After forming the first semiconductor layer portion, the ambient temperature is lowered to 1400 ° C. or lower, and then the ambient temperature is raised to 1500 ° C. or higher to supply the source gas, It is formed on the first semiconductor layer portion so as to be continuous with the first semiconductor layer portion, has the same conductivity type as the first semiconductor layer portion, has a thickness of less than 100 nm, and has an upper end.
  • a third semiconductor layer portion of the layer is formed.
  • the atmospheric temperature is lowered from 100 ° C. or more to 1500 ° C. or higher again from the atmospheric temperature of 1500 ° C. or higher forming the first semiconductor layer portion of the first semiconductor layer.
  • the interface between the first semiconductor layer portion and the second semiconductor layer portion having the same conductivity type may be a discontinuous growth surface. it can. Therefore, according to the present invention, the switching loss can be reduced and the pn junction can be reduced as compared with the case where the interface between the first semiconductor layer portion and the second semiconductor layer portion of the first semiconductor layer is a continuous growth surface. Compared with the case where the interface is a discontinuous growth surface, it is possible to manufacture a bipolar semiconductor device that can keep the carrier injection efficiency into the drift layer high and suppress an increase in steady loss.
  • the bipolar semiconductor device of the present invention at least one of the first semiconductor layer, the drift layer, the second semiconductor layer, and the interface between the drift layer and the second semiconductor layer promotes carrier recombination. Therefore, the switching loss can be reduced, the carrier recombination at the pn junction interface can be suppressed, the carrier injection efficiency into the drift layer can be kept high, and the increase in the steady loss can be suppressed. .
  • FIG. 1 is a sectional view of a SiC diode 20 as a first embodiment of a bipolar semiconductor device of the present invention.
  • a semiconductor layer described below is formed on a substrate 21 made of n-type 4H SiC as the first conductivity type.
  • the 4H type “H” represents a hexagonal crystal
  • the 4H type “4” represents a crystal structure in which the atomic stacking has a four-layer period.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • n-type 4H—SiC and the p-type (second conductivity type) 4H—SiC are sequentially grown on the n-type 4H type SiC substrate 21 to produce an epitaxial SiC diode 20 as described later.
  • the n-type 4H SiC substrate 21 shown in FIG. 1 was produced by slicing an ingot grown by the modified Rayleigh method with an off angle ⁇ of 8 degrees and mirror polishing.
  • the n-type 4H SiC substrate 21 obtained by the Hall effect measurement method has a carrier density of 4 ⁇ 10 18 cm ⁇ 3 and a thickness of 350 ⁇ m.
  • a nitrogen-doped n-type SiC layer (n-type growth layer) and an aluminum-doped p-type SiC layer (p-type growth layer) are sequentially formed on the C-plane (carbon surface) of the n-type 4H-type SiC substrate 21 serving as a cathode by a CVD method. It is formed by epitaxial growth.
  • the buffer layer 22 has a donor density of 4 ⁇ 10 18 cm ⁇ 3 and a film thickness of 5.0 ⁇ m.
  • the drift layer 23 has a donor density of 2 ⁇ 10 14 cm ⁇ 3 and a film thickness of 120 ⁇ m.
  • the p-type growth layer which is the aluminum-doped p-type SiC layer, becomes the first p-type junction layer 24, the second p-type junction layer 25, and the p + -type contact layer 26 that become the anode layer.
  • the first p-type junction layer 24 forms a first semiconductor layer portion of the first semiconductor layer, has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 as a first impurity concentration, and has a film thickness of 2. 0 ⁇ m.
  • the second p-type junction layer 25 has a thickness of 0.5 ⁇ m.
  • the second p-type junction layer 25 is a second semiconductor layer portion of a first semiconductor layer formed on the first p-type junction layer 24 so as to be in contact with the first p-type junction layer 24. 25A, and a third semiconductor layer portion 25B of the first semiconductor layer formed on the second semiconductor layer portion 25A so as to be continuous with the second semiconductor layer portion 25A.
  • the first p-type junction layer 24, the second semiconductor layer portion 25A, and the third semiconductor layer portion 25B constitute a first semiconductor layer.
  • the second semiconductor layer portion 25A has a thickness of less than 100 nm (for example, 50 nm), and the second semiconductor layer portion 25A has an acceptor density of 1 ⁇ 102, which is a second impurity concentration, at the upper end 25A-1. It has reached 19 cm -3 . Further, the second semiconductor layer portion 25A has an acceptor density (for example, a third impurity concentration 10 times or more of the acceptor density 1 ⁇ 10 19 cm ⁇ 3 between the lower end 25A-2 and the upper end 25A-1. 1 ⁇ 10 20 cm ⁇ 3 ). A discontinuous growth surface is formed at the interface between the second semiconductor layer portion 25A and the first p-type junction layer 24. Note that the thickness of the second semiconductor layer portion 25A may be 10 nm. Further, the third impurity concentration which is 10 times or more may be 1 ⁇ 10 21 cm ⁇ 3 .
  • the third semiconductor layer portion 25B has an acceptor density of 1 ⁇ 10 19 cm ⁇ 3 as a second impurity concentration.
  • the p + type contact layer 26 has an acceptor density of 1 ⁇ 10 20 cm ⁇ 3 and a film thickness of 0.5 ⁇ m.
  • the SiC diode 20 includes an n-type buffer layer 22, an n-type drift layer 23, a first p-type junction layer 24, and a second p-type on the n-type 4H type SiC substrate 21.
  • the bonding layer 25 and the p + -type contact layer 26 are sequentially formed, and the processing conditions during fabrication will be described in more detail below.
  • the SiC diode 20 of this embodiment uses silane (SiH 4 ) and propane (C 3 H 8 ) as material gases. Nitrogen (N 2 ) and trimethylaluminum (Al (CH 3 ) 3 ) are used as dopant gases. Further, hydrogen (H 2 ) is used as a carrier gas.
  • the flow rate (supply speed) of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in Torr.
  • the numerical value in the parenthesis attached after the name of each gas represents a flow rate.
  • the temperature in the processing chamber is raised from room temperature to 1400 ° C. in 30 minutes in an H 2 atmosphere at 40 Torr.
  • the surface of the n-type 4H SiC substrate 21 serving as the cathode is etched for 30 minutes in the processing chamber at 40 Torr and 1400 ° C. in an H 2 atmosphere.
  • the temperature in the processing chamber is raised from 1400 ° C. to 1550 ° C. in 15 minutes in an H 2 atmosphere at 40 Torr.
  • silane (30 sccm), propane (12 sccm), nitrogen (17 sccm) and hydrogen (50 scrr, 1550 ° C.) 10 slm).
  • the processing time for this step is 20 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (0.008 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 480 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) at 50 Torr and 1550 ° C.
  • hydrogen (10 slm) is supplied to the crystal growth surface.
  • the processing time for this step is 8 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (300 sccm) and hydrogen at 50 Torr and 1550 ° C. (10 slm) is supplied.
  • the processing time for this step is 2 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (3000 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 2 minutes.
  • the temperature is lowered from 1550 ° C. to 1400 ° C. in 15 minutes at 50 Torr in an H 2 atmosphere.
  • the temperature is lowered from 1400 ° C. to 400 ° C. in 30 minutes at 100 Torr in an H 2 atmosphere.
  • the SiC epitaxial wafer for the SiC diode of the first embodiment can be manufactured by the above steps and processes.
  • the temperature lowering step and the temperature raising step the temperature was lowered to 1400 ° C. and then raised again to 1550 ° C. to re-grow the next layer. However, after the temperature was lowered to room temperature (or about the wafer removal temperature), the temperature was lowered again. The temperature may be increased and the next layer may be regrown.
  • the SiC diode 20 according to the first embodiment shown in FIG. 1 can be manufactured by performing the processing described below on the SiC epitaxial wafer according to the first embodiment.
  • both ends of the SiC epitaxial wafer are removed by reactive ion etching (RIE) and processed into a mesa structure.
  • RIE reactive ion etching
  • CF 4 carbon tetrafluoride
  • O 2 oxygen tetrafluoride
  • etching was performed to a depth of about 3.5 ⁇ m by a plasma processing apparatus under conditions of a pressure of 5 Pa and a high frequency power of 260 W.
  • a SiO 2 film (thickness 10 ⁇ m) deposited by CVD was used as a mask material at this time.
  • a p-type JTE (junction termination extension) 27 having a width of 250 ⁇ m and a depth of 0.7 ⁇ m was provided on the mesa bottom.
  • This p-type JTE27 was formed by Al ion implantation. The energy of this Al ion implantation is changed in 6 steps between 30 and 450 keV, and the total dose is 1.2 ⁇ 10 13 cm ⁇ 2 .
  • the JTE 27 injection layer was designed to have a box profile.
  • Ion implantation was all performed at room temperature, and graphite (thickness 5 ⁇ m) was used as a mask for ion implantation.
  • Heat treatment for activating the implanted ions was performed in an argon gas atmosphere at 1700 ° C. for 3 minutes.
  • a thermal oxide film 28 as a protective film was formed by wet oxidation at a temperature of 1200 ° C. for 3 hours.
  • reference numeral 31 denotes an insulating protective film (or oxide film).
  • Ni thinness 350 nm
  • a film of Ti (titanium: thickness 350 nm) and Al (aluminum: thickness 100 nm) is deposited on the p + type contact layer 26 to form the anode electrode 30.
  • the anode electrode 30 is composed of a Ti layer 30a and an Al layer 30b.
  • heat treatment is performed at 1000 ° C. for 20 minutes to make the cathode electrode 29 and the anode electrode 30 ohmic electrodes, respectively.
  • the size of the pn junction is 2.6 mm ⁇ and is almost circular.
  • the p-type JTE 27 is formed by aluminum ion implantation. However, the same effect can be obtained even when boron (B) ion implantation is used.
  • the withstand voltage of the SiC diode 20 of the first embodiment is 20 kV, and the on-voltage is 3.35V.
  • This on-voltage (forward voltage) is a value at a current density of 100 A / cm 2 in a characteristic curve K1 indicated by a solid line as shown in the forward characteristic diagram of FIG. This forward characteristic was obtained by measuring the current-voltage characteristic of the SiC diode 20 with a curve tracer.
  • the comparative example was manufactured without performing the (temperature decreasing process) and (temperature increasing process) before the process of forming the second p-type bonding layer 25.
  • the on-voltage at a current density of 100 A / cm 2 was 3.33 V, as indicated by a characteristic curve K2 indicated by a one-dot chain line in FIG.
  • the forward voltage is slightly increased as compared with the comparative example, but this increase is 0.6% (0.02 V), which is the same as that in the first embodiment. It can be said that the forward characteristics and the forward characteristics of the comparative example are substantially the same.
  • FIG. 3 shows the reverse recovery characteristics.
  • a characteristic curve K11 indicated by a solid line in FIG. 3 is the reverse recovery characteristic of the first embodiment, and a characteristic curve K12 indicated by a dashed line in FIG. 3 is a reverse recovery characteristic of the comparative example.
  • the reverse current density is 200 (A / cm 2 ), which is approximately 25% lower than the reverse current density 268 (A / cm 2 ) of the comparative example. is doing.
  • the reverse recovery time is 0.156 ( ⁇ seconds), which is approximately 20% less than the reverse recovery time 0.192 ( ⁇ seconds) of the comparative example.
  • the reverse recovery capacity is 0.80 ( ⁇ C) in the first embodiment, which is 40% less than the reverse recovery capacity 1.34 ( ⁇ C) of the comparative example. This indicates that according to the present embodiment, the switching loss can be greatly reduced as compared with the comparative example.
  • the acceptor density 1 ⁇ 10 19 cm ⁇ 3 that is the second impurity concentration is different by one digit or more.
  • the third impurity concentration (for example, 1 ⁇ 10 20 cm ⁇ 3 ) has reached the acceptor density of 1 ⁇ 10 19 cm ⁇ 3 , which is the second impurity concentration.
  • the semiconductor layer composed of the first p-type junction layer 24 and the second p-type junction layer 25 having the same conductivity type has a discontinuous growth surface.
  • the continuous growth surface serves as a recombination promoting surface that promotes carrier recombination.
  • the recombination velocity is substantially zero, whereas in the discontinuous growth surface, the recombination velocity has a finite value of, for example, 1 ⁇ 10 4 cm / s or more.
  • the switching loss can be reduced and the pn junction interface can be reduced compared to the case where the semiconductor layer made of the p-type silicon carbide semiconductor does not have a discontinuous growth surface.
  • the carrier injection efficiency into the drift layer 23 can be kept high, and an increase in steady loss can be suppressed.
  • step of manufacturing the epitaxial wafer of the SiC diode 20 of the first embodiment after the step of forming the first p-type junction layer 24 and before the step of forming the second p-type junction layer 25.
  • a step of stopping supply of silane, propane, and trimethylaluminum as source gases for 1 minute or longer may be performed.
  • the thickness is less than 100 nm and the impurity concentration is between the upper end 25A-1 and the lower end 25A-2.
  • the second p-type junction layer 25 having the second semiconductor layer portion 25A changing by one digit or more can be formed.
  • the second impurity concentration (1 ⁇ 10 19 cm ⁇ 3 ) of the third semiconductor layer portion 25B of the second p-type junction layer 25 is set to the first semiconductor layer of the first semiconductor layer.
  • the second impurity concentration of the third semiconductor layer portion 25B is increased.
  • 1 ⁇ 10 18 cm ⁇ 3 may be set, and the first impurity concentration of the first p-type junction layer 24 as the first semiconductor layer portion of the first semiconductor layer may be set to 1 ⁇ 10 19 cm ⁇ 3, for example.
  • the second semiconductor layer portion 25A has the second impurity concentration (for example, 1 ⁇ 10 18 cm ⁇ 3 ) at the upper end 25A-1, and the second semiconductor layer portion 25A has a second impurity concentration between the upper end 25A-1 and the lower end 25A-2.
  • a third impurity concentration eg, 1 ⁇ 10 19 cm ⁇ 3 ) that is 10 times or more the impurity concentration of 2.
  • FIG. 4 is a cross-sectional view of a pn junction diode 40 which is a modification of the first embodiment.
  • this modification only the one p-type junction layer 41 is provided in place of the first p-type junction layer 24 and the second p-type junction layer 25 of the first embodiment described above.
  • the same parts as those in the first embodiment are denoted by the same reference numerals, and the parts different from those in the first embodiment will be mainly described.
  • the p-type bonding layer 41 is an aluminum-doped p-type SiC layer and has a film thickness of 2.5 ⁇ m.
  • the p-type junction layer 41 is produced by the following first to third steps.
  • the growth rate of the p-type SiC film is set to zero for 1 minute or more (for example, 3 minutes).
  • the source gas is stopped, the p-type SiC film grown under the influence of the carrier gas by hydrogen is etched and scraped off at a very low speed.
  • the growth rate of the p-type SiC film is made zero by supplying the raw material gas so as to compensate for the portion cut at the extremely low etching rate.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C. to form a p-type SiC film.
  • This p-type SiC film is composed of a p-type SiC portion 41B as the second semiconductor layer portion of the first semiconductor layer and a p-type SiC portion 41C as the third semiconductor layer portion of the first semiconductor layer.
  • the processing time for this third step is 2 minutes.
  • the p-type junction layer 41 manufactured by the first to third steps has a first semiconductor layer first semiconductor layer with an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 2.0 ⁇ m.
  • a p-type SiC portion 41A is provided as a layer portion.
  • the p-type junction layer 41 is formed on the p-type SiC portion 41A so as to be continuous with the p-type SiC portion 41A, and has a thickness of less than 100 nm (for example, 50 nm) of the first semiconductor layer.
  • 2 has a p-type SiC portion 41B as a semiconductor layer portion.
  • the p-type SiC portion 41B has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 at the upper end 41B-1 and the acceptor density of 1 ⁇ 10 18 cm ⁇ between the upper end 41B-1 and the lower end 41B-2.
  • 3 has an acceptor density (for example, 1 ⁇ 10 17 cm ⁇ 3 ) which is 1/10 or less of 3 .
  • the thickness of the p-type SiC portion 41B may be 10 nm. Further, the acceptor density which is 1/10 or less of the above may be 1 ⁇ 10 14 cm ⁇ 3 .
  • the p-type junction layer 41 is formed on the p-type SiC portion 41B so as to be continuous with the p-type SiC portion 41B, and has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 .
  • a p-type SiC portion 41C is provided as a third semiconductor layer portion.
  • the p-type SiC portion 41B of the p-type junction layer 41 composed of the p-type SiC portion 41A, the p-type SiC portion 41B, and the p-type SiC portion 41C having the same conductivity type is discontinuously grown.
  • the discontinuous growth surface of p-type SiC portion 41B serves as a recombination promoting surface that promotes carrier recombination, and the semiconductor layer made of the p-type silicon carbide semiconductor has a discontinuous growth surface. Switching loss can be reduced as compared with the case where it is not. Further, compared with the case where the pn junction interface is a discontinuous growth surface, the carrier injection efficiency to the drift layer 23 can be kept high, and the increase in steady loss can be suppressed.
  • the anode layer first p-type junction layer 24 (first semiconductor layer) and second p-type junction layer 25 (second and third semiconductor layer portions) are used.
  • the p-type junction layer 41 second and third semiconductor layer portions
  • the present invention is basically applicable to other than the pn junction and the substrate, for example, The n-type buffer layer 22 as the second semiconductor layer, the interface between the n-type buffer layer 22 and the n-type drift layer 23, the interface between the second p-type junction layer 25 and the p + -type contact layer 26, p +
  • the present invention can also be applied to the interface between the p-type contact layer 26 and the p-type contact layer 26 in the p-type contact layer 26.
  • the n-type drift layer 23, the first p-type junction layer 24 (first semiconductor layer portion), the second semiconductor layer portion 25A, and the third semiconductor layer portion 25B are sequentially formed.
  • the n-type drift layer 23, the p-type SiC portion 41A (first semiconductor layer portion), the p-type SiC portion 41B (second semiconductor layer portion), the p-type SiC portion 41C. (Third semiconductor layer portion) is sequentially formed.
  • An n-type intermediate layer as a second semiconductor layer is formed on the n-type drift layer, and the p-type first semiconductor layer is formed on the n-type intermediate layer.
  • the first semiconductor layer portion, the p-type second semiconductor layer portion, and the p-type third semiconductor layer portion may be sequentially formed.
  • FIG. 5 shows a second embodiment of the bipolar semiconductor device of the present invention.
  • FIG. 5 is a cross-sectional view of an npn bipolar transistor 60 as the second embodiment.
  • the second embodiment also employs an n-type 4H SiC substrate.
  • n-type 4H—SiC, p-type 4H—SiC, and n-type 4H—SiC were successively epitaxially grown in this order to produce an npn bipolar transistor 60.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the n-type 4H-type SiC substrate 61 was produced by slicing an ingot grown by the modified Rayleigh method so that the off angle ⁇ was 8 degrees, and mirror polishing.
  • the substrate 61 serving as a collector is n-type, has a carrier density of 4 ⁇ 10 18 cm ⁇ 3 and a thickness of 350 ⁇ m as measured by the Hall effect measurement method.
  • an n-type buffer layer 62 and an n-type drift layer 63 are formed as a second semiconductor layer of nitrogen-doped n-type SiC by a CVD method.
  • n-type drift layer 63 On this n-type drift layer 63, a first p-type growth layer 64 made of aluminum-doped p-type SiC, a second p-type growth layer 65 made of aluminum-doped p-type SiC, and an n-type growth layer made of nitrogen-doped n-type SiC. 66 were sequentially formed by epitaxial growth. The n-type buffer layer 62 and the n-type drift layer 63 become the n-type collector layer.
  • the n-type buffer layer 62 has a donor density of 4 ⁇ 10 17 cm ⁇ 3 and a film thickness of 5 ⁇ m.
  • the n-type drift layer 63 has a donor density of 2 ⁇ 10 14 cm ⁇ 3 and a film thickness of 120 ⁇ m.
  • the first p-type growth layer 64 as the first semiconductor layer portion of the first semiconductor layer constituting the p-type base layer has an acceptor density of 2 ⁇ 10 17 cm ⁇ 3 as the first impurity concentration.
  • the layer thickness is 0.5 ⁇ m.
  • the second p-type growth layer 65 constituting the second and third semiconductor layer parts constituting the p-type base layer has a layer thickness of 0.5 ⁇ m.
  • the second p-type growth layer 65 is formed on the first p-type growth layer 64 so as to be in contact with the first p-type growth layer 64 and has a thickness of less than 100 nm (for example, 50 nm).
  • a p-type growth layer portion 65B as a semiconductor layer portion.
  • the p-type growth layer portion 65A may have a thickness of 10 nm.
  • the first p-type growth layer 64, the p-type growth layer portion 65A, and the p-type growth layer portion 65B constitute a first semiconductor layer.
  • the p-type growth layer portion 65A as the second semiconductor layer portion of the first semiconductor layer reaches the acceptor density 1 ⁇ 10 18 cm ⁇ 3 , which is the second impurity concentration, at the upper end 65A-1. Further, the p-type growth layer portion 65A has an acceptor density (for example, 10 times or more of the acceptor density 1 ⁇ 10 18 cm ⁇ 3 , which is the second impurity concentration) between the upper end 65A-1 and the lower end 65A-2. 1 ⁇ 10 19 cm ⁇ 3 ). Further, the acceptor density 10 times or more may be set to 1 ⁇ 10 21 cm ⁇ 3 .
  • the p-type growth layer portion 65B as the third semiconductor layer portion of the first semiconductor layer has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 as the second impurity concentration.
  • n-type growth layer 66 serving as an n-type emitter is formed on the second p-type growth layer 65.
  • the n-type growth layer 66 has a donor density of 7 ⁇ 10 17 cm ⁇ 3 and a film thickness of 0.75 ⁇ m.
  • Silane (SiH 4 ) and propane (C 3 H 8 ) are used as material gases.
  • Nitrogen (N 2 ) and trimethylaluminum ⁇ Al (CH 3 ) 3 ⁇ are used as dopant gases.
  • hydrogen (H 2 ) is used as a carrier gas.
  • the flow rate (supply speed) of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute).
  • the pressure is represented by Torr.
  • the numerical value in parentheses after the name of each gas represents the flow rate.
  • the temperature in the processing chamber is raised from room temperature to 1400 ° C. in 30 minutes in an H 2 atmosphere at 40 Torr.
  • the surface of the n-type 4H SiC substrate 61 serving as a collector is etched for 30 minutes in the processing chamber at 40 Torr and 1400 ° C. in an H 2 atmosphere.
  • the temperature in the processing chamber is raised from 1400 ° C. to 1550 ° C. in 15 minutes in an H 2 atmosphere at 40 Torr.
  • n-type buffer layer 62 on the C-plane of the n-type 4H-type SiC substrate 61 serving as a collector, silane (30 sccm), propane (12 sccm), nitrogen (17 sccm), and 50 Torr at 1550 ° C. Supply hydrogen (10 slm).
  • the processing time for this step is 20 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (0.008 sccm), and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 480 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (6 sccm) at 50 Torr and 1550 ° C.
  • hydrogen (10 slm) is supplied to the crystal growth surface.
  • the processing time for this step is 2 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen at 50 Torr and 1550 ° C. (10 slm) is supplied.
  • the processing time for this step is 2 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (30 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 3 minutes.
  • the temperature is lowered from 1550 ° C. to 1400 ° C. in 15 minutes at 50 Torr in an H 2 atmosphere.
  • the temperature is lowered from 1400 ° C. to 400 ° C. in 30 minutes at 100 Torr in an H 2 atmosphere.
  • the SiC epitaxial wafer for the npn bipolar transistor of the second embodiment can be manufactured by the above steps and processes.
  • the temperature lowering step and the temperature raising step the temperature was lowered to 1400 ° C. and then raised again to 1550 ° C. to re-grow the next layer. However, the temperature was lowered to room temperature (or about the wafer take-out temperature) and then again. The temperature may be increased and the next layer may be regrown.
  • an npn bipolar transistor according to the second embodiment shown in FIG. 5 can be manufactured by performing the following process on the SiC epitaxial wafer according to the second embodiment.
  • the n-type growth layer 66 is etched by reactive ion etching (RIE) with a width of 10 ⁇ m, a depth of 0.75 ⁇ m, and a pitch of 23 ⁇ m, leaving an n-type growth layer 66 that becomes an n-type emitter.
  • RIE reactive ion etching
  • CF 4 and O 2 were used, and the etching was performed under the conditions of a pressure of 0.05 Torr and a high frequency power of 260 W.
  • a SiO 2 film (thickness 10 ⁇ m) deposited by CVD was used as a mask material at this time.
  • a mesa structure is formed by reactive ion etching (RIE).
  • RIE reactive ion etching
  • CF 4 and O 2 were used as the etching gas for this RIE, and the etching was performed to a depth of about 1 ⁇ m under the conditions of a pressure of 0.05 Torr and high frequency power of 260 W.
  • a SiO 2 film (thickness 10 ⁇ m) deposited by CVD was used as a mask material at this time.
  • the p-type guard ring 56 for relaxing the electric field concentration at the base end portion and the base contact region 68 are formed by Al (aluminum) ion implantation in the same process.
  • the base contact region 68 has a width of 3 ⁇ m, a distance from the emitter of 5 ⁇ m, and the p-type guard ring 56 has a width of 150 ⁇ m.
  • the contact region 68 and the depth of the p-type guard ring 56 are both 0.5 ⁇ m.
  • the energy of Al ion implantation when forming the p-type guard ring 56 and the base contact region 68 is 40 to 560 keV, and the total dose is 1.0 ⁇ 10 13 cm ⁇ 2 .
  • a SiO 2 film (thickness 5 ⁇ m) formed by CVD was used as a mask for this ion implantation. All ion implantations were performed at room temperature, and the heat treatment for activating the implanted ions was performed under conditions of a temperature of 1600 ° C. in an argon gas atmosphere for 5 minutes.
  • a thermal oxide film was formed by wet oxidation at a temperature of 1150 ° C. for 2 hours, and a SiO 2 film was further deposited by CVD to form an oxide film 58 having a total thickness of 2 ⁇ m.
  • a collector electrode 59C is formed on the lower surface of the n-type 4H type SiC substrate 61.
  • a base electrode 59B is formed in the base contact region 68.
  • Ni is vapor-deposited on the n-type growth layer 66 to be the n-type emitter, thereby forming an emitter electrode 69.
  • heat treatment was performed at 1000 ° C. for 20 minutes to form ohmic junctions.
  • the base electrode 59B and the emitter electrode 69 were covered with a Ti / Au electrode 70 to form each electrode terminal.
  • the size of the joint is 3.2 mm ⁇ 3.2 mm.
  • the guard ring 56 is formed by Al ion implantation, but the same effect can be obtained even when B (boron) ion implantation is used.
  • each of the n-type 4H SiC substrate 61, the n-type buffer layer 62, the n-type drift layer 63, the first p-type growth layer 64, and the second p-type growth layer 65 is provided.
  • the joint surfaces (surfaces extending in the horizontal direction in the figure) are all parallel to a surface having an off angle of 8 degrees from the (000-1) carbon surface.
  • the breakdown voltage of the npn bipolar transistor 60 manufactured in this way is 30 kV.
  • the on-resistance was 10.0 m ⁇ cm 2 and the maximum current amplification factor was about 15. This on-resistance is a value in an initial state at a base current of 0.6 A and a collector current density of 100 A / cm 2 .
  • the acceptor density 1 ⁇ which is the second impurity concentration is 1 ⁇ .
  • the third impurity concentration (for example, 1 ⁇ 10 19 cm ⁇ 3 ), which differs from 10 18 cm ⁇ 3 by one digit or more, reaches the acceptor density of 1 ⁇ 10 18 cm ⁇ 3 , which is the second impurity concentration. .
  • a discontinuous growth surface in which the impurity concentration changes sharply is formed in the p-type growth layer portion 65A as the second semiconductor layer portion of the first semiconductor layer.
  • the p-type base layer which is a semiconductor layer composed of the first p-type growth layer 64 and the second p-type growth layer 65 having the same conductivity type, is formed as a discontinuous growth surface.
  • This discontinuous growth surface is a recombination promoting surface that promotes carrier recombination.
  • the recombination velocity is substantially zero, whereas in the discontinuous growth surface, the recombination velocity has a finite value of, for example, 1 ⁇ 10 4 cm / s or more.
  • the switching loss can be reduced as compared with the case where the p base layer, which is a semiconductor layer made of the p-type silicon carbide semiconductor, does not have a discontinuous growth surface, Compared with the case where the pn junction interface is a discontinuous growth surface, the carrier injection efficiency to the n-type drift layer 63 can be kept high, and an increase in steady loss can be suppressed.
  • step of manufacturing the epitaxial wafer of the npn bipolar transistor 60 of the above embodiment after the formation step of the first p-type growth layer 64 and before the formation step of the second p-type growth layer 65.
  • a step of stopping supply of silane, propane, and trimethylaluminum as source gases for 1 minute or longer may be performed.
  • the thickness is less than 100 nm and the impurity concentration is between the upper end 65A-1 and the lower end 65A-2.
  • a second p-type growth layer 65 having a p-type growth layer portion 65A as the second semiconductor layer portion of the first semiconductor layer that has changed by an order of magnitude or more can be formed.
  • the second impurity concentration (1 ⁇ 10 18 cm ⁇ 3 ) of the p-type growth layer portion 65B as the third semiconductor layer portion of the first semiconductor layer of the second p-type growth layer 65 is used. Is higher than the first impurity concentration (2 ⁇ 10 17 cm ⁇ 3 ) of the first p-type growth layer 64 as the first semiconductor layer portion of the first semiconductor layer.
  • the second impurity concentration of the p-type growth layer portion 65B as the third semiconductor layer portion is, for example, 1 ⁇ 10 18 cm ⁇ 3, and the first p-type as the first semiconductor layer portion of the first semiconductor layer
  • the first impurity concentration of the growth layer 64 may be set to 1 ⁇ 10 19 cm ⁇ 3 , for example.
  • the p-type growth layer portion 65A as the second semiconductor layer portion of the first semiconductor layer has the second impurity concentration (for example, 1 ⁇ 10 18 cm ⁇ 3 ) at the upper end 65A-1, and the upper end 65A.
  • ⁇ 3 and the lower end 65A-2 have a third impurity concentration (for example, 1 ⁇ 10 19 cm ⁇ 3 ) that is 10 times or more of the second impurity concentration.
  • FIG. 6 is a cross-sectional view of an npn bipolar transistor 80 which is a modification of the second embodiment.
  • this modification only the first p-type growth layer 85 is provided in place of the first p-type growth layer 64 and the second p-type growth layer 65 of the second embodiment described above.
  • the same parts as those in the second embodiment are denoted by the same reference numerals, and different parts from the second embodiment will be mainly described.
  • the p-type growth layer 85 is an aluminum-doped p-type SiC layer and has a thickness of 1.0 ⁇ m.
  • the p-type growth layer 85 is produced by the following first to third steps.
  • the growth rate of the p-type SiC film is set to zero for 1 minute or more (for example, 3 minutes).
  • the source gas is stopped, the p-type SiC grown under the influence of the carrier gas due to the hydrogen is etched and scraped off at a very low speed.
  • the growth rate of the p-type SiC film is made zero by supplying a very small amount of source gas so as to compensate for the portion cut at the extremely low etching rate.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C. to form a p-type SiC film.
  • This p-type SiC film includes a p-type SiC portion 85B as the second semiconductor layer portion of the first semiconductor layer and a p-type SiC portion 85C as the third semiconductor layer portion of the first semiconductor layer. .
  • the processing time for this third step is 2 minutes.
  • the p-type growth layer 85 manufactured in the first to third steps has a first semiconductor layer first semiconductor layer with an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.5 ⁇ m.
  • a p-type SiC portion 85A is provided as a layer portion.
  • the p-type growth layer 85 is formed on the p-type SiC portion 85A so as to be continuous with the p-type SiC portion 85A, and has a thickness of less than 100 nm (for example, 50 nm) of the first semiconductor layer.
  • 2 has a p-type SiC portion 85B as a semiconductor layer portion.
  • the p-type SiC portion 85B has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 at the upper end 85B-1 and the acceptor density of 1 ⁇ 10 18 cm ⁇ between the upper end 85B-1 and the lower end 85B-2.
  • 3 has an acceptor density (for example, 1 ⁇ 10 17 cm ⁇ 3 ) which is 1/10 or less of 3 .
  • the thickness of the p-type SiC portion 85B may be 10 nm. Further, the acceptor density which is 1/10 or less of the above may be 1 ⁇ 10 14 cm ⁇ 3 .
  • the p-type growth layer 85 is formed on the p-type SiC portion 85B so as to be continuous with the p-type SiC portion 85B, and has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 .
  • a p-type SiC portion 85C is provided as a third semiconductor layer portion.
  • the p-type SiC portion 85B of the p-type growth layer 85 including the p-type SiC portion 85A, the p-type SiC portion 85B, and the p-type SiC portion 85C having the same conductivity type is discontinuously grown.
  • the discontinuous growth surface of p-type SiC portion 85B serves as a recombination promoting surface that promotes carrier recombination, and the semiconductor layer made of the p-type silicon carbide semiconductor has a discontinuous growth surface. Switching loss can be reduced as compared with the case where it is not. Further, compared to the case where the pn junction interface is a discontinuous growth surface, the carrier injection efficiency into the n-type drift layer 63 can be kept high, and the increase in steady loss can be suppressed.
  • the configuration of the present invention is applied to the p-type base layer (the first p-type growth layer 64 and the second p-type growth layer 65 or the p-type growth layer 85).
  • the present invention is basically applicable to other than the pn junction and the substrate.
  • the n-type buffer layer 62 as the second semiconductor layer or the n-type buffer layer 62 and the n-type drift layer 63 It can also be applied to the interface.
  • the n-type drift layer 63, the first p-type growth layer 64 (first semiconductor layer portion), the p-type growth layer portion 65A (second semiconductor layer portion), and the p-type growth are used.
  • the layer portion 65B (third semiconductor layer portion) is sequentially formed, and in the modification of the second embodiment, the n-type drift layer 63, the p-type SiC portion 85A (first semiconductor layer portion), and the p-type SiC portion 85B
  • the (second semiconductor layer portion) and the p-type SiC portion 85C (third semiconductor layer portion) were sequentially formed, and an n-type intermediate layer as a second semiconductor layer was formed on the n-type drift layer, and the A p-type first semiconductor layer portion, a p-type second semiconductor layer portion, and a p-type third semiconductor layer portion of the first semiconductor layer may be sequentially formed on the n-type intermediate layer.
  • FIG. 7 shows a cross section of an IGBT (Insulated Gate Bipolar Transistor) 101 as a third embodiment of the bipolar semiconductor device of the present invention.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • this IGBT 101 three layers are epitaxially grown in the order of a p-type 4H—SiC layer, an n-type 4H—SiC layer, and a p-type 4H—SiC layer on an n-type 4H type SiC substrate 91, as will be described below. It was made.
  • the main bonding surfaces of the p layer and the n layer are ⁇ 0001 ⁇ planes.
  • a p-type 4H—SiC layer an n-type layer is formed on a substrate using n-type 4H-type SiC having a plane orientation of an off-angle ⁇ of 3.5 degrees from the (000-1) carbon plane.
  • a 4H—SiC layer and a p-type 4H—SiC layer were sequentially formed.
  • the n-type 4H SiC substrate 91 was prepared by slicing an ingot grown by the modified Rayleigh method at a surface inclined by 3.5 degrees from the (000-1) carbon surface and mirror polishing.
  • the n-type 4H-type SiC substrate 91 serving as a collector is n-type, has a thickness of 350 ⁇ m, and has a carrier density of 4 ⁇ 10 18 cm ⁇ 3 determined by the Hall effect measurement method.
  • Three layers of an aluminum-doped p-type SiC layer, a nitrogen-doped n-type SiC layer, and an aluminum-doped p-type SiC layer were epitaxially grown in this order on the n-type 4H-type SiC substrate 91 by a CVD method.
  • the p-type SiC layer becomes the p-type buffer layer 92 and the p-type drift layer 93 in FIG.
  • the p-type buffer layer 92 has an acceptor density of 4 ⁇ 10 17 cm ⁇ 3 and a film thickness of 5.0 ⁇ m.
  • the p-type drift layer 93 has an acceptor density of 1 ⁇ 10 14 cm ⁇ 3 and a film thickness of 120 ⁇ m.
  • the n-type growth layer 94 as the first semiconductor layer portion of the first semiconductor layer formed on the p-type drift layer 93 has a donor density of 1 ⁇ 10 17 cm ⁇ 3 and a film thickness of 1.0 ⁇ m. .
  • the n-type growth layer 95 formed on the n-type growth layer 94 has a donor density of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 1.0 ⁇ m.
  • the n-type growth layer 95 includes an n-type SiC portion 95A as a second semiconductor layer portion of the first semiconductor layer having a film thickness of less than 100 nm (for example, 50 nm), and a third portion connected to the n-type SiC portion 95A. And an n-type SiC portion 95B as a semiconductor layer portion.
  • the n-type SiC portion 95A may have a thickness of 10 nm.
  • the n-type growth layer 94, the n-type SiC portion 95A, and the n-type SiC portion 95B constitute a first semiconductor layer.
  • the donor density at the upper end 95A-1 reaches 1 ⁇ 10 18 cm ⁇ 3 , and the donor density at the upper end 95A-1 is between the upper end 95A-1 and the lower end 95A-2. It has a donor density (for example, 1 ⁇ 10 19 cm ⁇ 3 ) that is 10 times or more of 1 ⁇ 10 18 cm ⁇ 3 . Note that the donor density 10 times or more may be 1 ⁇ 10 21 cm ⁇ 3 .
  • the p-type growth layer 96 formed on the n-type growth layer 95 has an acceptor density of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 0.75 ⁇ m.
  • Silane (SiH 4 ) and propane (C 3 H 8 ) are used as material gases.
  • Nitrogen (N 2 ) and trimethylaluminum ⁇ Al (CH 3 ) 3 ⁇ are used as dopant gases.
  • hydrogen (H 2 ) is used as a carrier gas.
  • the flow rate (supply speed) of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute).
  • the pressure is represented by Torr.
  • the numerical value in parentheses after the name of each gas represents the flow rate.
  • the temperature in the processing chamber is raised from room temperature to 1400 ° C. in 30 minutes in an H 2 atmosphere at 40 Torr.
  • the surface of the n-type 4H SiC substrate 91 serving as the collector is etched for 30 minutes in the processing chamber in an H 2 atmosphere at 40 Torr and an atmospheric temperature of 1400 ° C.
  • the temperature in the processing chamber is raised from 1400 ° C. to 1550 ° C. in 15 minutes in an H 2 atmosphere at 40 Torr.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (12 sccm) at 50 Torr and 1550 ° C. And hydrogen (10 slm).
  • the processing time for this step is 20 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (3 sccm), and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 480 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (4.5 sccm) and hydrogen at 50 Torr and 1550 ° C. (10 slm) is supplied to the crystal growth surface.
  • the processing time for this step is 4 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (45 sccm) and hydrogen (10 slm) are applied at 50 Torr and 1550 ° C. Supply.
  • the processing time for this step is 4 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm), and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 3 minutes.
  • the temperature is lowered from 1550 ° C. to 1400 ° C. in 15 minutes at 50 Torr in an H 2 atmosphere.
  • the temperature is lowered from 1400 ° C. to 400 ° C. in 30 minutes at 100 Torr in an H 2 atmosphere.
  • the SiC epitaxial wafer for IGBT of the third embodiment can be manufactured by the above steps and processes.
  • the temperature was lowered to 1400 ° C. and then raised again to 1550 ° C. to re-grow the next layer.
  • the temperature may be increased and the next layer may be regrown.
  • the IGBT 101 shown in FIG. 7 can be manufactured by performing the processing described below on the SiC epitaxial wafer for the third embodiment.
  • the central portion of the p-type growth layer 96 is etched by RIE, a hole 96a is provided, and nitrogen is ion-implanted to form a contact region 97 serving as an emitter.
  • the p-type growth layer 96 and the n-type growth layer 95 are etched by RIE to form holes 90 (two in FIG. 7).
  • an SiO 2 film is deposited by CVD to form an insulating film 98.
  • Ni is deposited on the collector region of the n-type 4H SiC substrate 91 to form the collector electrode 102. Also, Ni is deposited on the contact region 97 to form the emitter electrode 103.
  • heat treatment is performed to form ohmic junctions. Further, a Mo electrode is formed on the insulating film 98 to form a gate electrode 99.
  • the IGBT 101 of this embodiment thus completed has a withstand voltage of 30 kV, an on-resistance of 15.0 m ⁇ cm 2 , and a collector-emitter voltage of ⁇ 15V.
  • This collector-emitter voltage is a value in an initial state where the gate voltage is ⁇ 40 V and the collector current is 1.4 A.
  • the donor density 1 ⁇ 10 that is the second impurity concentration is used in the n-type SiC portion 95A as the second semiconductor layer portion of the first semiconductor layer having a thickness of less than 100 nm (for example, 50 nm).
  • the third impurity concentration (for example, 1 ⁇ 10 19 cm ⁇ 3 ), which differs from 18 cm ⁇ 3 by one digit or more, reaches the acceptor density of 1 ⁇ 10 18 cm ⁇ 3 , which is the second impurity concentration.
  • the n-type emitter layer which is a semiconductor layer composed of the n-type growth layer 94 and the n-type growth layer 95 having the same conductivity type, has a discontinuous growth surface.
  • the continuous growth surface serves as a recombination promoting surface that promotes carrier recombination.
  • the recombination velocity is substantially zero, whereas in the discontinuous growth surface, the recombination velocity has a finite value of, for example, 1 ⁇ 10 4 cm / s or more.
  • the switching loss can be reduced as compared with the case where the n-type emitter layer, which is a semiconductor layer made of the n-type silicon carbide semiconductor, does not have a discontinuous growth surface.
  • the carrier injection efficiency into the p-type drift layer 93 can be kept high, and the increase in steady loss can be suppressed.
  • the step of manufacturing the epitaxial wafer of the IGBT 101 of the above-described embodiment after the step of forming the n-type growth layer 94 and before the step of forming the n-type growth layer 95, In place of performing the step (step), after the step of forming the n-type growth layer 94 and before the step of forming the n-type growth layer 95, supply of silane, propane, and nitrogen as source gases is performed for one minute. The step of stopping may be performed as described above (for example, for 3 minutes).
  • the n-type growth layer 95 after the source gas stopping step the thickness is less than 100 nm and the impurity concentration is one digit or more between the upper end 95A-1 and the lower end 95A-2.
  • An n-type growth layer 95 having an n-type SiC portion 95A as the second semiconductor layer portion of the changing first semiconductor layer can be formed.
  • the second impurity concentration (1 ⁇ 10 18 cm ⁇ 3 ) of the n-type SiC portion 95B as the third semiconductor layer portion of the first semiconductor layer of the n-type growth layer 95 is set to the first level.
  • the concentration is higher than the first impurity concentration (1 ⁇ 10 17 cm ⁇ 3 ) of the n-type growth layer 94 as the first semiconductor layer portion of one semiconductor layer, it may be reversed.
  • the second impurity concentration of the n-type SiC portion 95B as the third semiconductor layer portion of the first semiconductor layer is set to 1 ⁇ 10 17 cm ⁇ 3 , for example, and the first semiconductor layer portion as the first semiconductor layer portion
  • the first impurity concentration of the n-type growth layer 94 may be set to 1 ⁇ 10 18 cm ⁇ 3 , for example.
  • the n-type SiC portion 95A as the second semiconductor layer portion of the first semiconductor layer has the second impurity concentration (for example, 1 ⁇ 10 17 cm ⁇ 3 ) at the upper end 95A-1 and the upper end 95A ⁇ .
  • a third impurity concentration (for example, 1 ⁇ 10 18 cm ⁇ 3 ) is 10 times or more higher than the second impurity concentration between 1 and the lower end 95A-2.
  • FIG. 8 is a cross-sectional view of an IGBT 121 that is a modification of the third embodiment.
  • This modification differs from the above-described third embodiment only in that one n-type growth layer 115 is provided instead of the n-type growth layer 94 and the n-type growth layer 95 of the above-described third embodiment. . Therefore, in this modification, the same parts as those in the third embodiment are denoted by the same reference numerals, and different parts from the third embodiment will be mainly described.
  • the n-type growth layer 115 is produced by the following first to third steps.
  • Silane (30 sccm), propane (12 sccm), nitrogen (45 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C. to form an n-type SiC portion 115A as the first semiconductor layer portion of the first semiconductor layer. Film.
  • the processing time for this first step is 4 minutes.
  • the growth rate of the n-type SiC film is set to zero for 1 minute or more (for example, 3 minutes).
  • the source gas is stopped, the n-type SiC grown under the influence of the carrier gas caused by the hydrogen is etched and scraped off at a very low speed.
  • the growth rate of the n-type SiC film is made zero by supplying a very small amount of source gas so as to compensate for the portion cut at the extremely low etching rate.
  • silane (30 sccm), propane (12 sccm), nitrogen (45 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C. to form a p-type SiC film.
  • This p-type SiC film is composed of an n-type SiC portion 115B as the second semiconductor layer portion of the first semiconductor layer and an n-type SiC portion 115C as the third semiconductor layer portion of the first semiconductor layer. .
  • the processing time for this third step is 4 minutes.
  • the n-type growth layer 115 manufactured by the first to third steps has a donor density of 1 ⁇ 10 18 cm ⁇ 3 and a thickness of 1.0 ⁇ m. It has n-type SiC part 115A as a layer part.
  • the n-type growth layer 115 is formed on the n-type SiC portion 115A so as to continue to the n-type SiC portion 115A, and has a thickness of less than 100 nm (for example, 50 nm) of the first semiconductor layer.
  • 2 has an n-type SiC portion 115B as a semiconductor layer portion.
  • the n-type SiC portion 115B has a donor density of 1 ⁇ 10 18 cm ⁇ 3 at the upper end 115B-1 and the donor density of 1 ⁇ 10 18 cm ⁇ between the upper end 115B-1 and the lower end 115B-2. 1 or less is the donor density of 10 minutes of 3 (eg, 1 ⁇ 10 17 cm -3) have.
  • the n-type SiC portion 115B may have a thickness of 10 nm. Further, the donor density which is 1/10 or less of the above may be 1 ⁇ 10 14 cm ⁇ 3 .
  • the n-type growth layer 115 is formed on the n-type SiC portion 115B so as to be continuous with the n-type SiC portion 115B, and has a donor density of 1 ⁇ 10 18 cm ⁇ 3 . It has an n-type SiC portion 115C as a third semiconductor layer portion.
  • the n-type SiC portion 115B of the n-type growth layer 115 composed of the n-type SiC portion 115A, the n-type SiC portion 115B, and the n-type SiC portion 115C having the same conductivity type is discontinuously grown.
  • the discontinuous growth surface of n-type SiC portion 115B serves as a recombination promoting surface that promotes carrier recombination, and the emitter layer made of the n-type silicon carbide semiconductor has a discontinuous growth surface. Switching loss can be reduced as compared with the case where it is not. Further, compared to the case where the pn junction interface is a discontinuous growth surface, the carrier injection efficiency into the p-type drift layer 93 can be kept high, and an increase in steady loss can be suppressed.
  • the configuration of the present invention is applied to the n-type growth layer 94, the n-type growth layer 95, and the n-type growth layer 115.
  • the present invention basically includes a pn junction.
  • the present invention can be applied to the p-type buffer layer 92 as the second semiconductor layer and the interface between the p-type buffer layer 92 and the p-type drift layer 93.
  • the n-type drift layer 93, the n-type SiC portion 115A (first semiconductor layer portion), and the n-type SiC portion 115B (second semiconductor layer) are formed.
  • Layer portion) and n-type SiC portion 115C (third semiconductor layer portion) are sequentially formed.
  • An n-type intermediate layer as a second semiconductor layer is formed on the n-type drift layer, and the n-type intermediate layer is formed.
  • a p-type first semiconductor layer portion, a p-type second semiconductor layer portion, and a p-type third semiconductor layer portion of the first semiconductor layer may be sequentially formed thereon.
  • FIG. 9 shows a cross section of a GTO (gate turn-off bipolar transistor) 220 as a fourth embodiment of the bipolar semiconductor device of the present invention.
  • the n-type SiC substrate used for the GTO 220 of the fourth embodiment is the same as the n-type 4H type SiC substrate used for the IGBT 101 of the third embodiment.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the GTO 220 of the fourth embodiment includes an n-type 4H SiC substrate 201, a p-type buffer layer 202 sequentially formed on the n-type 4H SiC substrate 201, and a p-type A drift layer 203 and an n-type base layer 204 as a first semiconductor layer portion of the first semiconductor layer are provided.
  • An n-type growth layer 205 is formed on the n-type base layer 204.
  • a mesa p-type anode emitter layer 207 is formed on the n-type growth layer 205.
  • an n-type gate contact region 206 is formed by ion implantation in the portion of the n-type growth layer 205 exposed from the mesa-type p-type anode emitter layer 207.
  • the n-type gate contact region 206 is formed so as to surround the mesa-type p-type anode emitter layer 207.
  • a gate electrode 210 is formed on the n-type gate contact region 206.
  • An anode electrode 208 is formed on the p-type anode emitter layer 207.
  • a cathode electrode 299 is formed on the back surface of the n-type 4H type SiC substrate 201.
  • the n-type 4H SiC substrate 201 is composed of a SiC semiconductor layer having a thickness of 200 ⁇ m and a donor density of 8 ⁇ 10 18 cm ⁇ 3
  • the p-type buffer layer 202 has a thickness of 10 ⁇ m and an acceptor density of 6 It is composed of a SiC semiconductor layer of ⁇ 10 17 cm ⁇ 3
  • the p-type drift layer 203 is composed of a SiC semiconductor layer having a thickness of 200 ⁇ m and an acceptor density of 1 ⁇ 10 14 cm ⁇ 3 .
  • the n-type base layer 204 is composed of a SiC semiconductor layer having a thickness of 10 ⁇ m and a donor density of 1 ⁇ 10 17 cm ⁇ 3 .
  • the n-type base layer 204 serving as the first semiconductor layer portion of the first semiconductor layer has a donor density of 1 ⁇ 10 17 cm ⁇ 3 and a film thickness of 1.0 ⁇ m.
  • the n-type growth layer 205 formed on the n-type base layer 204 has a donor density of 1 ⁇ 10 18 cm ⁇ 3 and a film thickness of 1.0 ⁇ m.
  • the n-type growth layer 205 includes an n-type SiC portion 205A as a second semiconductor layer portion of a first semiconductor layer having a thickness of less than 100 nm (for example, 50 nm), and a first semiconductor connected to the n-type SiC portion 205A.
  • N-type SiC portion 205B as a third semiconductor layer portion of the layer.
  • the n-type SiC portion 205A may have a thickness of 10 nm.
  • the n-type base layer 204, the n-type SiC portion 205A, and the n-type SiC portion 205B constitute a first semiconductor layer.
  • the donor density at the upper end 205A-1 reaches 1 ⁇ 10 18 cm ⁇ 3 , and the donor density at the upper end 205A-1 is between the upper end 205A-1 and the lower end 205A-2. It has a donor density (for example, 1 ⁇ 10 19 cm ⁇ 3 ) that is 10 times or more of 1 ⁇ 10 18 cm ⁇ 3 . Note that the donor density 10 times or more may be 1 ⁇ 10 21 cm ⁇ 3 .
  • the n-type gate contact region 206 is composed of a SiC semiconductor layer having a thickness of 3 ⁇ m and a donor density of 1 ⁇ 10 18 cm ⁇ 3 .
  • the p-type anode emitter layer 207 is composed of a SiC semiconductor layer having a thickness of 10 ⁇ m and an acceptor density of 8 ⁇ 10 18 cm ⁇ 3 .
  • Silane (SiH 4 ) and propane (C 3 H 8 ) are used as material gases.
  • Nitrogen (N 2 ) and trimethylaluminum ⁇ Al (CH 3 ) 3 ⁇ are used as dopant gases.
  • hydrogen (H 2 ) is used as a carrier gas.
  • the flow rate (supply speed) of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute).
  • the pressure is represented by Torr.
  • the numerical value in parentheses after the name of each gas represents the flow rate.
  • the temperature in the processing chamber is raised from room temperature to 1400 ° C. in 30 minutes in an H 2 atmosphere at 40 Torr.
  • the surface of the n-type 4H SiC substrate 201 serving as a collector is etched for 30 minutes in the processing chamber at 40 Torr and an atmospheric temperature of 1400 ° C. in an H 2 atmosphere.
  • the temperature in the processing chamber is raised from 1400 ° C. to 1550 ° C. in 15 minutes in an H 2 atmosphere at 40 Torr.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (12 sccm) at 50 Torr and 1550 ° C.
  • hydrogen (10 slm).
  • the processing time for this step is 20 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (3 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 480 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (4.5 sccm) and hydrogen at 50 Torr and 1550 ° C. (10 slm) is supplied to the crystal growth surface.
  • the processing time for this step is 4 minutes.
  • silane (30 sccm), propane (12 sccm), nitrogen (45 sccm) and hydrogen (10 slm) are applied at 50 Torr and 1550 ° C. Supply.
  • the processing time for this step is 4 minutes.
  • silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C.
  • the processing time for this step is 3 minutes.
  • the temperature is lowered from 1550 ° C. to 1400 ° C. in 15 minutes at 50 Torr in an H 2 atmosphere.
  • the temperature is lowered from 1400 ° C. to 400 ° C. in 30 minutes at 100 Torr in an H 2 atmosphere.
  • the SiC epitaxial wafer for GTO of the third embodiment can be manufactured by the above steps and processes.
  • the temperature lowering step and the temperature raising step the temperature was lowered to 1400 ° C. and then raised again to 1550 ° C. to re-grow the next layer. However, after the temperature was lowered to room temperature (or about the wafer take-out temperature), The temperature may be increased and the next layer may be regrown.
  • the GTO 220 shown in FIG. 9 can be manufactured by subjecting the SiC epitaxial wafer for the fourth embodiment to the processing described below.
  • the p-type anode emitter layer 207 is etched by reactive ion etching (RIE) to form a mesa-type p-type anode emitter layer 207.
  • RIE reactive ion etching
  • an n-type gate contact region 206 is formed in the n-type growth layer 205 by ion implantation.
  • Ni is vapor-deposited on the back surface of the n-type 4H SiC substrate 201 to form the cathode electrode 299. Further, Ni is deposited on the p-type anode emitter layer 207 to form the anode electrode 208. Next, heat treatment is performed to form ohmic junctions. Further, Ni is deposited on the n-type gate contact region 206 to form the gate electrode 210.
  • the donor density 1 ⁇ 10 that is the second impurity concentration is used in the n-type SiC portion 205A as the second semiconductor layer portion of the first semiconductor layer having a thickness of less than 100 nm (for example, 50 nm).
  • the third impurity concentration (for example, 1 ⁇ 10 19 cm ⁇ 3 ), which differs from 18 cm ⁇ 3 by one digit or more, reaches the acceptor density of 1 ⁇ 10 18 cm ⁇ 3 , which is the second impurity concentration.
  • the n-type gate layer which is a semiconductor layer composed of the n-type base layer 204 and the n-type growth layer 205 having the same conductivity type, has a discontinuous growth surface.
  • the continuous growth surface serves as a recombination promoting surface that promotes carrier recombination.
  • the recombination velocity is substantially zero, whereas in the discontinuous growth surface, the recombination velocity has a finite value of, for example, 1 ⁇ 10 4 cm / s or more.
  • the switching loss can be reduced and the pn junction interface can be reduced.
  • the carrier injection efficiency into the p-type drift layer 203 can be kept high, and an increase in steady loss can be suppressed.
  • the step of manufacturing the epitaxial wafer of GTO 220 of the above embodiment after the step of forming the n-type base layer 204 and before the step of forming the n-type growth layer 205, In place of performing the step (step), after the step of forming the n-type base layer 204 and before the step of forming the n-type growth layer 205, supply of silane, propane, and nitrogen as source gases is performed for one minute. The step of stopping may be performed as described above (for example, for 3 minutes).
  • the thickness is less than 100 nm and the impurity concentration is one digit or more between the upper end 205A-1 and the lower end 205A-2.
  • An n-type growth layer 205 having an n-type SiC portion 205A as the second semiconductor layer portion of the changing first semiconductor layer can be formed.
  • the second impurity concentration (1 ⁇ 10 18 cm ⁇ 3 ) of the n-type SiC portion 205B as the third semiconductor layer portion of the first semiconductor layer of the n-type growth layer 205 is set to the first level.
  • the concentration is higher than the first impurity concentration (1 ⁇ 10 17 cm ⁇ 3 ) of the n-type base layer 204 as the first semiconductor layer portion of one semiconductor layer, the reverse may be possible.
  • the second impurity concentration of the n-type SiC portion 205B as the third semiconductor layer portion of the first semiconductor layer is set to 1 ⁇ 10 17 cm ⁇ 3 , for example, and the first semiconductor layer portion as the first semiconductor layer portion is The first impurity concentration of the n-type base layer 204 may be set to 1 ⁇ 10 18 cm ⁇ 3 , for example.
  • the n-type SiC portion 205A as the second semiconductor layer portion of the first semiconductor layer has the second impurity concentration (for example, 1 ⁇ 10 17 cm ⁇ 3 ) at the upper end 205A-1, and the upper end 205A ⁇ .
  • a third impurity concentration (for example, 1 ⁇ 10 18 cm ⁇ 3 ) is 10 times or more the second impurity concentration between 1 and the lower end 205A-2.
  • FIG. 10 is a cross-sectional view of a GTO 221 that is a modification of the fourth embodiment.
  • This modification differs from the above-described fourth embodiment only in that one n-type growth layer 215 is provided instead of the n-type base layer 204 and the n-type growth layer 205 of the above-described fourth embodiment. . Therefore, in this modification, the same parts as those in the above-described fourth embodiment are denoted by the same reference numerals, and different parts from the above-described fourth embodiment will be mainly described.
  • the n-type growth layer 215 is produced by the following first to third steps.
  • Silane (30 sccm), propane (12 sccm), nitrogen (45 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C. to form the n-type SiC portion 215A as the first semiconductor layer portion of the first semiconductor layer. Film.
  • the processing time for this first step is 4 minutes.
  • the growth rate of the n-type SiC film is set to zero for 1 minute or more (for example, 3 minutes).
  • the source gas is stopped, the n-type SiC grown under the influence of the carrier gas caused by the hydrogen is etched and scraped off at a very low speed.
  • the growth rate of the n-type SiC film is made zero by supplying a very small amount of source gas so as to compensate for the portion cut at the extremely low etching rate.
  • silane (30 sccm), propane (12 sccm), nitrogen (45 sccm) and hydrogen (10 slm) are supplied at 50 Torr and 1550 ° C. to form a p-type SiC film.
  • This p-type SiC film is composed of an n-type SiC portion 215B as the second semiconductor layer portion of the first semiconductor layer and an n-type SiC portion 215C as the third semiconductor layer portion of the first semiconductor layer. .
  • the processing time for this third step is 4 minutes.
  • the n-type growth layer 215 manufactured by the first to third steps has a donor density of 1 ⁇ 10 18 cm ⁇ 3 and a thickness of 1.0 ⁇ m. It has n-type SiC part 215A as a layer part.
  • the n-type growth layer 215 is formed on the n-type SiC portion 215A so as to be continuous with the n-type SiC portion 215A, and has a thickness of less than 100 nm (for example, 50 nm) of the first semiconductor layer.
  • 2 has an n-type SiC portion 215B as a semiconductor layer portion.
  • the n-type SiC portion 215B has a donor density of 1 ⁇ 10 18 cm ⁇ 3 at the upper end 215B-1 and a donor density of 1 ⁇ 10 18 cm ⁇ between the upper end 215B-1 and the lower end 215B-2. 1 or less is the donor density of 10 minutes of 3 (eg, 1 ⁇ 10 17 cm -3) have.
  • the n-type SiC portion 215B may have a thickness of 10 nm. Further, the donor density which is 1/10 or less of the above may be 1 ⁇ 10 14 cm ⁇ 3 .
  • the n-type growth layer 215 is formed on the n-type SiC portion 215B so as to be continuous with the n-type SiC portion 215B, and has a donor density of 1 ⁇ 10 18 cm ⁇ 3 . It has an n-type SiC portion 215C as a third semiconductor layer portion.
  • the n-type SiC portion 215B of the n-type growth layer 215 composed of the n-type SiC portion 215A, the n-type SiC portion 215B, and the n-type SiC portion 215C having the same conductivity type is discontinuously grown.
  • the discontinuous growth surface of n-type SiC portion 215B serves as a recombination promoting surface that promotes carrier recombination, and the emitter layer made of the n-type silicon carbide semiconductor has a discontinuous growth surface. Switching loss can be reduced as compared with the case where it is not. Further, compared to the case where the pn junction interface is a discontinuous growth surface, the carrier injection efficiency into the p-type drift layer 203 can be kept high, and the increase in steady loss can be suppressed.
  • the configuration of the present invention is applied to the n-type base layer 204, the n-type growth layer 205, and the n-type growth layer 215.
  • the present invention basically includes a pn junction.
  • the present invention can be applied to the p-type buffer layer 202 as the second semiconductor layer and the interface between the p-type buffer layer 202 and the p-type drift layer 203.
  • Layer portion) and n-type SiC portion 215C (third semiconductor layer portion) are sequentially formed.
  • a p-type intermediate layer as a second semiconductor layer is formed on the p-type drift layer, and the p-type intermediate layer is formed.
  • An n-type first semiconductor layer portion, an n-type second semiconductor layer portion, and an n-type third semiconductor layer portion of the first semiconductor layer may be sequentially formed thereon.
  • the first conductivity type second semiconductor layer is formed between the first conductivity type drift layer and the second conductivity type first semiconductor layer, and the drift layer and the second semiconductor are formed.
  • a recombination promoting surface that promotes carrier recombination may be formed at the interface with the layer. Thereby, switching loss can be reduced, and recombination of carriers at the pn junction interface formed by the first and second semiconductor layers having different conductivity types can be suppressed.
  • the bipolar semiconductor device of the present invention includes a first semiconductor layer portion formed between the first conductivity type drift layer and the second conductivity type first semiconductor layer so as to be continuous with the drift layer, A second semiconductor layer of a first conductivity type having a second semiconductor layer portion formed so as to be connected to the first semiconductor layer portion, the drift layer having a first impurity concentration, and a second semiconductor layer
  • the first semiconductor layer portion has a thickness of less than 100 nm, reaches the second impurity concentration at the end on the second semiconductor layer portion side, and has a second impurity concentration between the lower end and the upper end.
  • the second semiconductor layer portion of the second semiconductor layer has the second impurity concentration, and the third impurity concentration is 10 times the second impurity concentration or the second impurity concentration.
  • the second impurity concentration is reached from the third impurity concentration that differs from the second impurity concentration by an order of magnitude or more.
  • a discontinuous growth surface (recombination promoting surface that promotes carrier recombination) can be formed in the second semiconductor layer portion of the two semiconductor layers where the impurity concentration changes sharply.
  • the SiC diode, npn bipolar transistor, IGBT, and GTO have been described as embodiments of the SiC bipolar semiconductor device of the present invention.
  • the present invention is not limited to the above-described embodiments.
  • Can be applied to various 4H-SiC bipolar semiconductor devices such as SIJFET, Thyristor, GTO, MCT (Mos Controlled Thyristor), SiCGT (SiC Commutated Gate Thyristor), EST (Emitter Switched Thyristor), BRT (Base Resistance Controlled Thyristor) is there.
  • the present invention can be applied to various 4H-SiC bipolar elements such as elements having opposite polarities (for example, pnp transistors for npn transistors), and can be applied to SiC bipolar elements using other crystal structures such as 6H-SiC. Is.
  • the SiC / bipolar semiconductor device of the present invention can suppress switching loss and steady loss, it can suppress energization loss and can be used with a large current.
  • a vehicle such as a home appliance field, an industrial field, or an electric vehicle.
  • power loss can be reduced, and it can be used with a large current and is compact. Can be realized.
  • SiC diode 21 n-type 4H-type SiC substrate 22 n-type buffer layer 23 n-type drift layer 24 first p-type junction layer 25 second p-type junction layer 25A second semiconductor layer portion 25A-1 upper end 25A- 2 Lower end 25B Third semiconductor layer portion 26 p + type contact layer 27 p type JTE 28 Thermal oxide film 29 Cathode electrode 30 Anode electrode 30a Ti layer 30b Al layer 31 Insulating protective film 40 pn junction diode 41 p-type junction layer 41A p-type SiC part 41B p-type SiC part 41B-1 upper end 41B-2 lower end 41C p-type SiC portion 56 p-type guard ring 58 oxide film 59B base electrode 59C collector electrode 60 npn bipolar transistor 61 n-type 4H-type SiC substrate 62 n-type buffer layer 63 n-type drift layer 64 first p-type growth layer 65 second p-type growth layer 65A p-type growth layer portion 65A-1 upper end 65A

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Abstract

La présente invention concerne, dans une diode (20) SiC, la concentration des impuretés d'une seconde partie (25A) de couche à semi-conducteur ayant une épaisseur inférieure à 100 nm (par exemple, 50 nm) passe d'une troisième concentration des impuretés (par exemple, 1 × 1020 cm-3) à une densité d'accepteur de 1 × 1019 cm-3, ladite troisième concentration des impuretés étant différente par une ou plusieurs ordres de grandeur à partir d'une densité d'accepteur de 1 × 1019 cm-3 qui est une deuxième concentration des impuretés. Une surface de croissance discontinue, où la concentration des impuretés change brusquement, est formée dans la deuxième partie (25A) de couche à semi-conducteur. Ladite surface de croissance discontinue sert de surface favorisant la recombinaison destinée à favoriser la recombinaison de porteuses, permettant de réduire une perte de commutation. De plus, l'efficacité d'injection de porteuse dans une couche (23) de dérive est maintenue élevée par comparaison avec le cas dans lequel une interface de jonction pn est utilisée comme la surface de croissance discontinue, permettant ainsi d'empêcher une perte constante d'augmenter. Cela fournit un dispositif à semi-conducteur bipolaire dont la perte de commutation peut être réduite et dont la perte constante peut être empêchée d'augmenter.
PCT/JP2014/078601 2013-11-01 2014-10-28 Dispositif à semi-conducteur bipolaire et son procédé de fabrication WO2015064562A1 (fr)

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WO2018160785A1 (fr) * 2017-03-02 2018-09-07 University Of South Carolina Ancrage du point de conversion en dessous de l'interface de couche épitaxiale pour un dispositif de puissance sic

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JP6988175B2 (ja) * 2017-06-09 2022-01-05 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法

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JPH04291765A (ja) * 1991-03-20 1992-10-15 Fuji Electric Co Ltd 横型絶縁ゲートサイリスタ
JPH1074959A (ja) * 1996-07-03 1998-03-17 Toshiba Corp 電力用半導体素子
JP2012033618A (ja) * 2010-07-29 2012-02-16 Kansai Electric Power Co Inc:The バイポーラ半導体素子
JP2012204541A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 電力用半導体装置

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Publication number Priority date Publication date Assignee Title
WO2018160785A1 (fr) * 2017-03-02 2018-09-07 University Of South Carolina Ancrage du point de conversion en dessous de l'interface de couche épitaxiale pour un dispositif de puissance sic

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