WO2015063220A1 - Capteur d'image a base de silicium a dynamique de lecture amelioree - Google Patents
Capteur d'image a base de silicium a dynamique de lecture amelioree Download PDFInfo
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- WO2015063220A1 WO2015063220A1 PCT/EP2014/073354 EP2014073354W WO2015063220A1 WO 2015063220 A1 WO2015063220 A1 WO 2015063220A1 EP 2014073354 W EP2014073354 W EP 2014073354W WO 2015063220 A1 WO2015063220 A1 WO 2015063220A1
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- storage node
- voltage
- pixel
- image sensor
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- 229910052710 silicon Inorganic materials 0.000 title description 4
- 239000010703 silicon Substances 0.000 title description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 3
- 238000003860 storage Methods 0.000 claims abstract description 77
- 238000005286 illumination Methods 0.000 claims description 56
- 239000004020 conductor Substances 0.000 claims description 30
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- 239000011159 matrix material Substances 0.000 description 5
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- 101100140580 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) REF2 gene Proteins 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/76—Circuitry for compensating brightness variation in the scene by influencing the image signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Definitions
- the field of the invention is that of silicon-based image sensors, both matrix sensors and linear sensors, whose dynamics are sought to improve.
- the dynamics of a sensor is expressed in decibels (dB) and is defined by the ratio of the largest signal, corresponding to a high illumination, to the floor noise level of the sensor which fixes the lowest signal, corresponding to a low illuminance, observable at the exit.
- This floor noise level depends on the sensor technology and the characteristics of the electronic pixel reading system.
- a sensor with a large dynamic scene is generally understood to mean sensors whose dynamic range is greater than 80 dB.
- the dynamics of the sensor depends on specific characteristics of the pixel and its structure, in particular its ability to convert photons into electrons, it is the quantum efficiency, and its ability to convert the collected electrons into voltage, it is the gain of conversion of charges / voltage, and characteristics specific to the read circuit downstream of the pixel: gain of the read circuit and voltage excursion allowed by the analog / digital converter of the reading circuit.
- This dynamic is also constrained by technological factors: in the photosensitive zone where the pixels are made, it is notably the filling factor of the pixel, that is to say the ratio of the photosensitive zone of the pixel on the complete surface the pixel; in the peripheral zone around the photosensitive zone, it is the silicon surface available for the reading circuits. Conversion speed and power consumption must also be taken into account.
- the object of the invention is to provide a solution for adjusting the charge-voltage conversion gain of the pixel so as to obtain a gain that can be adapted to the illumination received to avoid saturation in the event of strong illumination and to maintain a gain charge-voltage conversion sufficiently high in case of low illumination.
- a basic structure of a silicon-based active pixel sensor pixel comprises:
- a capacitive storage node which stores the charges (the electrons) collected by the photosensitive element of the pixel, which can be formed by the intrinsic capacitance of the photosensitive element; or, in an intermediate storage node active pixel structure (four or more transistors pixel), by a separate capacitance, connected to the photosensitive member by a charge transfer transistor and;
- a follower transistor connected to this storage node, which outputs a voltage level representative of the quantity of charges on the storage node.
- the technical solution on which the invention is based mainly consists in modifying the effective capacity of the storage node of the pixel, by virtue of a feedback loop which acts on the supply of the follower transistor connected to the storage node. in such a way that the apparent capacity of the storage node depends on the gain of the loop.
- the gain By modifying the gain, the capacity of the storage node is modified and therefore the load-voltage conversion factor which is inversely proportional to the capacity of the storage node.
- the invention proposes an image sensor comprising pixels and read circuits, each pixel having at least one photosensitive element, a charge storage node generated by the photosensitive element, a follower transistor whose gate is connected to the storage node, whose source is connected to a column conductor itself connected to a read circuit, and whose drain receives a supply voltage, characterized in that a counter loop is provided.
- this loop having an input connected to the column conductor and an output connected to the drain of the follower transistor to supply the supply voltage of the latter, and in that means are provided for modifying the behavior of the counter-loop. -action according to the illumination received.
- the behavior of the feedback loop can be changed by commissioning or decommissioning the loop according to the illumination received. Alternatively, it can be modified by modifying the loop gain according to the illumination received.
- the illumination received may be the overall illumination received by the sensor or it may be the illumination received by the pixel itself.
- the illumination is the overall illumination of the sensor
- an automatic detection of the global illumination and an action on the behavior of the loop according to this detection can be provided, or a manual action of the user can be provided. decides whether it wants to go into high illumination mode or low light mode and that changes the gain or the commissioning or out of order of the loop accordingly.
- the behavior of the loop will preferably be modified as a function of the voltage present on the column conductor at the time of the reading of the charges.
- storage node because this voltage represents the illumination received by the pixel: for example, a different loop gain will be adopted depending on the voltage level present on the column.
- the loop gain can be positive or negative. If it is negative, it increases the effective capacity of the storage node and consequently decreases the load-voltage conversion factor. If it is positive, it decreases the effective capacity of the storage node and significantly increases the load-to-voltage conversion factor. It can therefore be preferably provided that the loop gain is made positive or negative depending on the illumination received.
- the feedback loop is preferably disabled during a re-initialization phase of the storage node before a charge transfer from the photosensitive member to the storage node.
- the feedback loop comprises a first negative gain amplifier whose input is connected to the column conductor, a second negative gain amplifier whose input is connected to the output of the first amplifier, a comparator having two inputs respectively connected to the outputs of the two amplifiers, and a switching means controlled by the comparator for directing to the drain of the follower transistor is the output of the first amplifier or the output of the second amplifier.
- the first amplifier comprises a first input connected to a first reference voltage, a second input connected to an input capacitance, a feedback capability, and a switch for short-circuiting the feedback capability during an initialization phase of the storage node; and the second amplifier comprises a first input coupled to a second reference voltage, a second input connected to an input capacitance, a feedback capability, and a switch for short-circuiting the feedback capability during a phase. initialization of the storage node.
- the proposed solution does not affect the fill factor of the pixel, which is an added advantage.
- FIGS. 1a and 1b respectively illustrate a basic structure of a CMOS sensor pixel, with four transistors and the associated sequencing signals making it possible to read such a pixel, according to the state of the art;
- FIG. 2 illustrates a feedback loop between the conductor of a column of pixels, and the drain of the follower transistor of these pixels according to the invention
- FIG. 3 illustrates a first embodiment of a feedback loop to a negative gain amplifier according to the invention.
- FIG. 4 is a timing diagram highlighting the effect of the feedback loop during the charge transfer phase
- FIG. 5 illustrates a second embodiment of a feedback loop according to the invention with two negative gain amplifiers each and a comparator, making it possible to set the loop gain to a positive value or a negative value according to the voltage supplied by the column driver during the reading of the loads stored in the storage node;
- FIGS. 6 and 7 are timing diagrams of the different signals in sequence of reading a pixel with such a feedback loop with two amplifiers, in the case of a corresponding column voltage (FIG. low level of illumination of the pixel, and the second ( Figure 7) at a high level of illumination of the pixel.
- the invention will be described in an example of application to a four-transistor CMOS sensor pixel structure.
- the field of application of the invention applies more widely to the different charge storage node pixel structures coupled to a follower transistor: to more complex structure pixels, using more transistors; or at three transistor transistor structure pixels, wherein it is the capacitance of the photosensitive element which directly constitutes the capacitive storage node.
- Figures 1a and 1b illustrate the structure and sequencing of the read signals of a PIX pixel to four transistors of a CMOS sensor array.
- the matrix is organized in rows and columns of pixels of identical structure.
- Each pixel PIX is connected to a column conductor connecting all the pixels of the same column of pixels.
- Each column conductor is connected to a current source CC, generally common to all the columns of the matrix, which provides the current necessary for the reading of a pixel of the column selected for reading; and an ADC reading circuit of the pixels of the column, which digitally converts the voltage level Vcol applied to the column conductor by the PIX pixel selected for reading.
- This voltage level Vcol is representative of the illumination received by the pixel.
- the photosensitive element of the pixel is a photodiode Dph.
- Other photosensitive elements may be used, for example a MOS capability.
- This photodiode is connected to a capacitive storage node NS, by a transistor T1, during a phase transfer of the charges collected by the photodiode, to the capacitor Cs of the storage node NS.
- a follower transistor T3 supplies on its source s, fed by a constant current supplied by a DC current source, an output voltage which is representative of the quantity of charges transferred on the capacitive storage node: its gate g is connected to the node NS storage; its drain d receives a supply voltage V RE FP sufficient to bias the transistor T3 in follower mode (polarization in saturated mode), when the pixel is selected for reading, allowing the copying of the voltage of the storage node, on the conductor column.
- a selection transistor T4 is connected between the source s of the follower transistor T3 and a column conductor COL which connects the pixels of the same column. Its gate is connected to a line conductor L1 through which a pixel selection signal (SEL) is applied.
- SEL pixel selection signal
- a reset transistor T2 is provided to reset the storage node NS. In the example, it is connected between the supply voltage V RE FP and the storage node NS, carrying this node at the voltage V RE FP ⁇
- the initialization phase of the storage node NS is driven by the signal RSNS, during which the voltage at the node is established and stabilizes at the reset level V RE FP; and a charge transfer phase collected by the photosensitive element Dph, to the storage node NS, is driven by the signal TRA, during which the voltage at the storage node will be established at a useful level representative of the amount of loads stored by the node NS, and function of the charge-voltage conversion factor of the pixel.
- the voltage Vcol on the column COL which is the copy of the voltage at the storage node, the threshold voltage of the follower transistor, is thus established at a corresponding reset level and a corresponding useful level.
- Reading the pixel by the read circuit ADC generally consists of a first digital analog conversion of the voltage Vcol, conducted between the initialization phase (RS N s) and the transfer phase (TRA), to obtain a first digital value representative of the reset level, in a second conversion of the voltage Vcol, conducted after the transfer phase, to obtain a second digital value representative of the useful level, and a subtraction between the two numerical values obtained.
- a numerical result is obtained which is a measurement representative of the illumination received by the pixel and free of the correlated noise associated with the capacitive storage node.
- the charge / voltage conversion factor of the pixel defines, for the pixel, the voltage level that will be obtained at the input of the read circuit ADC, for an electron collected by the element photosensitive pixel.
- FIG. 2 details the elements or parameters of the pixel that fall within the definition of the conversion factor: the capacitance C N s of the storage node NS of the pixel, and the gain and the intrinsic capacities of the follower transistor.
- the gain of the follower transistor denoted G f , is close to 1, generally of the order of 0.8 or 0.9.
- the intrinsic capacitances of the follower transistor are the capacitance C gs , between gate and source of the transistor T3; and the capacity C gd between gate and drain of the follower transistor T3. This follower transistor has a gain of its own.
- the total capacity seen from the storage node NS therefore comprises the contribution of the capacitances C N s and C gd , and that of the capacitance C gSi, but this latter in a proportion reduced by the Miller effect to (1 -G f ) C gs .
- the voltage V RE FP is supplied during the reading of the pixel by a feedback loop 100 having a loop gain GL inserted between the column conductor and the transistor drain. follower of the pixels of the column.
- the feedback loop 1 00 has its input
- the drain voltage applied during the reading of a pixel of the column then depends on the voltage Vcol supplied by the column conductor during the reading of this pixel.
- Vcol supplied by the column conductor during the reading of this pixel.
- the contribution of the gate-drain capacitance C g d of the transistor to the conversion factor CVF also becomes proportionate, by a Miller effect provided by the feedback loop according to the invention. And this proportion depends on the gain of the follower transistor and the gain of the loop. More precisely, the charge-voltage conversion factor is then written for this G L gain feedback loop pixel structure, as follows:
- the feedback loop 100 thus makes it possible to use the gate drain capacitance of the follower transistor to modify the value of the load / voltage conversion factor.
- Gi_ negative loop gain
- the contribution of this gate-drain capacitance is increased to the effective capacity of the storage node.
- the CVF factor of charge-voltage conversion is decreased.
- the dynamics of the sensor towards the high levels of illumination is improved.
- the contribution of this grid-drain capacitance is made more "negative", which makes it possible to increase the FVC factor, which is favorable for low levels of illumination.
- the feedback loop 100 thus makes it possible to improve the exploitable dynamics of a pixel, for a given pixel structure and a given electronic reading chain. It can be implemented in practice to improve the dynamics for high levels of illumination and / or low levels of illumination.
- FIG. 3 A first exemplary embodiment of a feedback loop, having a predetermined negative loop gain GL, is illustrated in FIG. 3.
- Y are represented two consecutive pixels PIX ,, and ⁇ , + ⁇ of the same column COL. pixels. These two pixels are connected to the column conductor COL by their respective selection transistor controlled for the pixel PIXi by a selection signal SEL, a row of rank i of the matrix, and for the pixel ⁇ , + ⁇ by a signal of SEL i + i selection of the next row, rank i + 1.
- the selection signals are sequenced so that only one pixel of the column at a time is selected for reading.
- the transistor T3 of the pixel has its source connected to the DC current source and operates as a follower.
- the gain feedback loop G L is formed by a gain AMP1 amplifier G1 negative.
- G L G1.
- the amplifier has an input e1 connected to the column conductor COL.
- the other input e2 receives a reference voltage V REF .
- This reference voltage V RE F is common to all the pixels of the matrix.
- the output of the amplifier forms the output 102 of the loop. It is connected to the drain supply conductor of the follower transistors T3 of all the pixels of the column.
- the input e1 is connected to the column conductor COL by an input capacitor C1 1 and a feedback capacitance C12 is connected between this input and the output of the amplifier.
- a switch controlled by an initialization signal RSAMPI is placed in parallel on this capacitor C12.
- the switch controlled by the signal RSAMPI and the two capacities make it possible to initialize the amplifier according to a mounting in follower mode, making it possible to copy, at the output, the input reference voltage (the output S1 of the amplifier moves to cancel the voltage difference between the two inputs e1 and e2). This imposes the reference voltage level V RE F on the output S1 of the amplifier.
- this initialization of the loop amplifier is carried out in the re-initialization phase of the storage node: the voltage V RE F is used to reset the storage node NS, and there is a corresponding level of voltage Vcol on the column driver COL.
- the feedback loop is out of order: no gain effect.
- the variations in the voltage level of the column have no effect on the voltage level applied to the drain of the follower transistor; the latter is constant and equal to Vref.
- FIG. 4 shows the evolution of the voltage V REF P applied to the drain of the pixel by the feedback loop. It occurs during and after the charge transfer phase (electrons) to the storage node (TRA). In this phase (TRA), the charges of the photodiode transferred to the storage node NS, change (lower) the voltage of this node, and therefore the voltage Vcol on the column, according to the load-voltage conversion factor.
- the loop gain G L being in the negative example, it reduces the load-voltage conversion factor at the storage node of the pixel: the voltage level at the storage node, and therefore the level of the voltage Vcol on the column. , falls less quickly and reaches the end of the transfer a level that is higher than that which would have been obtained for the same amount of transferred charges, without the feedback loop.
- the evolution of the voltage Vcol with and without the loop is respectively represented by the curve in solid line and in dotted lines in FIG. 4. This configuration is favorable to the high levels of illumination, making it possible to avoid the saturation of the chain. electronic reading.
- a specific action can be performed to put the feedback loop out of service during the load reading phase of the storage node if the overall illumination of the sensor is lower, for example by short-circuiting the capacitor C12 even outside phases reset.
- This action can be decided by the user or according to an automatic detection of global illumination of the sensor.
- An action decided by the user or by an automatic detection may alternatively be provided to change the gain of the amplifier; this can be done for example by selecting another capacity C1 1 or C12, of different value, depending on the illumination.
- a feedback loop with a positive G L loop gain is implemented by using two amplifiers each having a structure comparable to the structure of the amplifier of FIG. following each other, in series.
- the positive loop gain G L increases the charge-voltage conversion factor at the storage node of the pixel: for the same quantity of transferred charges, the voltage level at the storage node drops faster and reaches the end of the transfer. a level which is lower than that which would have been obtained for the same quantity of transferred charges, without the feedback loop.
- This configuration is favorable to low levels of illumination.
- a specific action can be performed to turn off the feedback loop during the storage node load reading phase if the overall illumination of the sensor is stronger, for example by short-circuiting the capacitor C12 even outside the reset phases.
- This action can be decided by the user or according to an automatic detection of global illumination of the sensor.
- An action decided by the user or by an automatic detection may alternatively be provided to change the gain of one of the amplifiers; this can be done for example by selecting other capacitance values associated with each of the amplifiers, depending on the illumination.
- This deactivation or in service or this change of gain is for example obtained by means of external configuration of the sensor (programming, control button ...), or alternatively from a measurement of the average brightness of the scene , obtained in the sensor.
- the feedback loop can be put into operation with a positive loop gain or a negative G loop gain, depending on the illumination.
- This selection of positive or negative gain can be obtained by means of external configuration of the sensor (programming, control button, selector ...) or from a measurement of average brightness of the scene, made by the sensor.
- FIG. 5 illustrates an improved implementation of a feedback loop according to the invention, by which the loop gain G L is established at a value which is a function of the voltage level supplied by the column conductor during the load transfer phase stored in the storage node.
- the loop gain G L is slaved to the illumination received by the pixel. This improves the exploitable dynamics of the pixel towards the two extremes.
- the modification of the behavior of the feedback loop consists in a selection between a positive loop gain and a negative loop gain, but the servocontrol as a function of the column voltage could also consist in a selection between two positive gains or two negative gains of different values, or a selection between a commissioning or a decommissioning of the loop.
- the feedback loop 100 comprises two negative gain amplifiers in series, of the same structure:
- the column conductor COL is connected at the input e1 of the first amplifier by its input capacitance C1 1; the output S1 of the first amplifier is connected at the input of the second amplifier by its input capacitance C21.
- the outputs S1 and S2 of the amplifiers are applied as inputs to a comparator COMP whose output controls a switching circuit SW of either output S1 or S2 on the output 102 of the feedback loop. .
- the output voltage S1 or S2 is thus found as the drain voltage V RE FP of the follower transistor T3 of the pixel. In reality, this voltage is applied to the drain of the follower transistors of all the pixels of the column, the pixel selected for reading and the pixels not selected for reading.
- the reference voltage V RE F2 of the amplifier AMP2 is chosen higher than the voltage V RE FI of the amplifier AMP1.
- REF2 is set to 3.3 volts and the voltage V RE FI to 3 volts.
- the comparator COMP is configured to impose the voltage V RE F2 at the output 102 of the feedback loop, via the switching means SW, during the initialization phase of the storage node.
- Output S2 is required during the initialization phase and continues to apply for low levels of illumination.
- the output S1 is required if the voltage Vcol reaches a threshold voltage such that the outputs S1 and S2 intersect, for a value V B.
- This comparator switching value V B is set by the reference voltages and the gains respective amplifiers AMP1 and AMP2. It is in practice equal to (V REF 2 V REF i) / (G 1 + G 1 x G 2).
- G1 and G2 are close to -1; and that G f x G 1 x G 2 is greater than 1 and preferably less than 3. It is ideally of the order of 2 to 2.5.
- the gain G f of follower transistor is generally of the order of 0.8 or 0.9 with the technologies of MOS transistors usually used.
- the two amplifiers AMP1 and AMP2 are each initialized as described above with reference to FIG. 3, so that we find the reference voltage V RE FI output S1 and the reference voltage REF2 output S2.
- the respective duration of the initialization signals RS Ns , RSAMP-I, RSAMP2 is defined to obtain the stabilization of the voltage at the storage node, then that of the output S1, then that of the output S2 .
- the output S2 is switched on the output 102 of the loop: the re-initialization level of the storage node is therefore set at the voltage VREF2.
- the voltage Vcol is the recopy. on the column conductor is established substantially at this same level (at the threshold voltage V th of the follower transistor).
- a reset voltage Vref2 could be applied to the storage node during the reset phase without going through the amplifiers. It will also be noted that the reset transistor T2 could be diode-mounted without control of its gate by a reset signal, the reset being done because of the application of the voltage Vref2 to the drain of this diode-mounted transistor.
- the (negative) charges lower the voltage on the storage node and therefore the voltage Vcol.
- the output voltage S2 and therefore the drain voltage VREFP, decreases faster than the voltage on the storage node NS and therefore the voltage Vcol on the column conductor; the conversion factor is increased.
- FIG. 7 illustrates what happens on the contrary, when the quantity of charges collected is high: as explained in connection with FIGS. 3 and 4, the column voltage will drop less rapidly than if there were no feedback. but since the quantity of charges transferred is high, the outputs S1 and S2 will cross here and switch the comparator: the voltage V RE FP which was fixed first by the output S2, at the beginning of the transfer phase, then follows the exit S1, and goes back up. The conversion factor is decreased, preventing the Vcol voltage from reaching a voltage level that is too high.
- the reading of the pixel generally comprises two analog-to-digital conversions followed by a subtraction of the two numerical values obtained.
- the first conversion being that of the initialization level, before the charge transfer phase: there is no loop gain: the voltage Vcol corresponds to the voltage of reference V RE F2. Since the second conversion is that of the useful level, after charge transfer, the loop gain varies as a function of the illumination: the voltage Vcol obtained will depend on the actual conversion factor at the storage node, at the end of the transfer phase. and therefore function of G1 and G2, or of G1 alone.
- the reading circuit therefore, means are provided for rendering the two conversions homogeneous.
- it will be provided to transmit a signal from the comparator to the read circuit.
- the sensor operates with an automatic switching between two values of the charge-voltage conversion factor, one for the strongest illuminations, the other for the weakest illuminations. , this failover resulting from the use of two different loop gains.
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Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2016550999A JP2016536949A (ja) | 2013-11-04 | 2014-10-30 | 改善された読み取りダイナミックレンジを有するシリコンベースの画像センサ |
EP14793835.1A EP3066826A1 (fr) | 2013-11-04 | 2014-10-30 | Capteur d'image a base de silicium a dynamique de lecture amelioree |
CN201480065554.8A CN105794200A (zh) | 2013-11-04 | 2014-10-30 | 具有改进的读取动态的硅基图像传感器 |
US15/033,964 US9924118B2 (en) | 2013-11-04 | 2014-10-30 | Silicon-based image sensor with improved reading dynamic range |
KR1020167013151A KR20160078999A (ko) | 2013-11-04 | 2014-10-30 | 개선된 판독 동적특성을 갖는 실리콘 기반의 이미지 센서 |
IL245428A IL245428A0 (en) | 2013-11-04 | 2016-05-01 | Silicon-based image sensor with improved reading dynamics |
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FR1360769 | 2013-11-04 | ||
FR1360769A FR3012912B1 (fr) | 2013-11-04 | 2013-11-04 | Capteur d'image a base de silicium a dynamique de lecture amelioree |
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WO2015063220A1 true WO2015063220A1 (fr) | 2015-05-07 |
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US (1) | US9924118B2 (fr) |
EP (1) | EP3066826A1 (fr) |
JP (1) | JP2016536949A (fr) |
KR (1) | KR20160078999A (fr) |
CN (1) | CN105794200A (fr) |
FR (1) | FR3012912B1 (fr) |
IL (1) | IL245428A0 (fr) |
TW (1) | TW201532442A (fr) |
WO (1) | WO2015063220A1 (fr) |
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US10910072B1 (en) * | 2019-12-17 | 2021-02-02 | Sandisk Technologies Llc | Accurate self-calibrated negative to positive voltage conversion circuit and method |
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US5192920A (en) * | 1992-03-18 | 1993-03-09 | Eastman Kodak Company | High-sensitivity, low-noise transistor amplifier |
WO2001061756A2 (fr) * | 2000-02-14 | 2001-08-23 | Foveon, Inc. | Detecteur de pixels actifs possedant une amplification d'amorçage et une limitation de fuite pendant l'affichage |
US6831486B1 (en) * | 2003-09-30 | 2004-12-14 | Texas Instruments Incorporated | Charge detection node with variable conversion gain and kTC noise suppression |
US20060157640A1 (en) * | 2005-01-18 | 2006-07-20 | Perlman Stephen G | Apparatus and method for capturing still images and video using coded aperture techniques |
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JP2795314B2 (ja) * | 1996-05-13 | 1998-09-10 | 日本電気株式会社 | 半導体装置 |
KR100296451B1 (ko) * | 1998-09-21 | 2001-10-26 | 윤종용 | 개선된이득을가지는소오스팔로워회로및그것을이용한고체촬상장치의출력회로 |
EP1351490B1 (fr) * | 2002-04-02 | 2009-12-23 | STMicroelectronics Limited | Capteur d'image utilisant un circuit de lecture amélioré |
JP4666383B2 (ja) * | 2006-08-10 | 2011-04-06 | シャープ株式会社 | 増幅型固体撮像装置および電子情報機器 |
US7732748B2 (en) | 2006-08-31 | 2010-06-08 | Aptina Imaging Corporation | Active pixel image sensor with reduced readout delay |
JP5188221B2 (ja) * | 2008-03-14 | 2013-04-24 | キヤノン株式会社 | 固体撮像装置 |
JP5383465B2 (ja) * | 2009-12-16 | 2014-01-08 | キヤノン株式会社 | 光電変換装置、焦点検出装置及び撮像システム |
CN104041010B (zh) * | 2011-12-27 | 2017-12-15 | 索尼半导体解决方案公司 | 成像元件、成像装置、电子装置和成像方法 |
-
2013
- 2013-11-04 FR FR1360769A patent/FR3012912B1/fr active Active
-
2014
- 2014-10-30 JP JP2016550999A patent/JP2016536949A/ja active Pending
- 2014-10-30 CN CN201480065554.8A patent/CN105794200A/zh active Pending
- 2014-10-30 KR KR1020167013151A patent/KR20160078999A/ko not_active Application Discontinuation
- 2014-10-30 EP EP14793835.1A patent/EP3066826A1/fr not_active Withdrawn
- 2014-10-30 WO PCT/EP2014/073354 patent/WO2015063220A1/fr active Application Filing
- 2014-10-30 US US15/033,964 patent/US9924118B2/en not_active Expired - Fee Related
- 2014-10-31 TW TW103137810A patent/TW201532442A/zh unknown
-
2016
- 2016-05-01 IL IL245428A patent/IL245428A0/en unknown
Patent Citations (4)
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US5192920A (en) * | 1992-03-18 | 1993-03-09 | Eastman Kodak Company | High-sensitivity, low-noise transistor amplifier |
WO2001061756A2 (fr) * | 2000-02-14 | 2001-08-23 | Foveon, Inc. | Detecteur de pixels actifs possedant une amplification d'amorçage et une limitation de fuite pendant l'affichage |
US6831486B1 (en) * | 2003-09-30 | 2004-12-14 | Texas Instruments Incorporated | Charge detection node with variable conversion gain and kTC noise suppression |
US20060157640A1 (en) * | 2005-01-18 | 2006-07-20 | Perlman Stephen G | Apparatus and method for capturing still images and video using coded aperture techniques |
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Title |
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See also references of EP3066826A1 * |
Also Published As
Publication number | Publication date |
---|---|
US9924118B2 (en) | 2018-03-20 |
IL245428A0 (en) | 2016-06-30 |
KR20160078999A (ko) | 2016-07-05 |
FR3012912B1 (fr) | 2017-04-14 |
EP3066826A1 (fr) | 2016-09-14 |
CN105794200A (zh) | 2016-07-20 |
TW201532442A (zh) | 2015-08-16 |
JP2016536949A (ja) | 2016-11-24 |
FR3012912A1 (fr) | 2015-05-08 |
US20160277689A1 (en) | 2016-09-22 |
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