WO2015056342A1 - 尤度生成回路および尤度生成方法 - Google Patents
尤度生成回路および尤度生成方法 Download PDFInfo
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- WO2015056342A1 WO2015056342A1 PCT/JP2013/078321 JP2013078321W WO2015056342A1 WO 2015056342 A1 WO2015056342 A1 WO 2015056342A1 JP 2013078321 W JP2013078321 W JP 2013078321W WO 2015056342 A1 WO2015056342 A1 WO 2015056342A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
Definitions
- the present invention relates to a likelihood generation circuit and the like necessary for soft decision error correction decoding.
- Likelihoods used in soft decision error correction decoding are the minimum value of errors (Euclidean distance) with respect to the received symbols and all symbol candidate points of the pattern in which the transmission bit is 1, and the pattern in which the transmission bit is 0.
- the minimum values of errors with all of the symbol candidate points are obtained, and the difference is taken as the log likelihood ratio LLR (Log Likelihood Ratio).
- Patent Document 1 a circuit scale is reduced by eliminating a calculation part of the Euclidean distance from a symbol that does not need to be calculated in advance from the relationship between the received signal and the mapping from the relationship of symbol mapping.
- a decision value generation circuit is proposed.
- the circuit is reduced by deleting the unnecessary part of the calculation, which is clarified from the expression expansion.
- it is necessary to support a plurality of modulation schemes.
- the present invention has been made to solve the above-described problem, and is a soft decision value generation circuit that supports a plurality of modulation schemes, particularly 8QAM (Quadrature Amplitude Modulation) and QPSK (Quadrature Phase Shift Keying). Therefore, an object of the present invention is to provide a likelihood generation circuit and the like that reduce the circuit scale by sharing a part of the likelihood generation unit.
- 8QAM Quadrature Amplitude Modulation
- QPSK Quadrature Phase Shift Keying
- the present invention is a likelihood generation circuit for generating likelihood from received data of modulation schemes QPSK and 8QAM, and includes 1 bit for selecting an inner circle or an outer circle on a constellation mapping diagram, and 2 indicating each quadrant A phase rotation adjustment unit for phase-rotating symbols in the inner circle or outer circle of a symbol set of received data of modulation scheme 8QAM to which bits are allocated and bit mapped, and reception of received data of modulation scheme QPSK by QPSK likelihood generation A first likelihood generation unit that generates a 2-bit likelihood indicating a quadrant of a symbol set of the modulation scheme 8QAM processed by the phase rotation adjustment unit together with the symbol likelihood, and the phase rotation adjustment unit A phase rotation unit for rotating the phase of the modulated modulation mode 8QAM symbol set to the first quadrant on the constellation mapping diagram;
- the likelihood generation of the modulation scheme QPSK is applied from the modulation scheme 8QAM symbol set processed by the phase rotation unit or the likelihood is directly calculated by threshold determination to indicate whether the modulation scheme 8QAM symbol set is an inner circle
- the circuit scale can be reduced by sharing a part of the likelihood generation unit.
- FIG. 1 It is a figure which shows an example of the constellation mapping figure (mapping) of the modulation system 8QAM corresponding by this invention. It is a figure which shows schematic structure of the likelihood generation circuit by Embodiment 1 of this invention. It is a figure for demonstrating the likelihood production
- the circuit scale is reduced by sharing a part of the likelihood generating section.
- a phase rotation part that adjusts the phase rotation according to the modulation method, a likelihood generation unit, and a modulation method selection part are provided.
- the circuit scale can be reduced while the 8QAM circuit and the QPSK circuit can be shared.
- a delay unit 1 delays a received signal.
- the phase rotation unit 2 rotates the phase of the received signal.
- the delayed signal r0 is used as a reference signal for differential decoding, and the signal r0 is input to two inputs of the signal r1 that is not delayed.
- the phase rotation of the same amount as the amount of phase rotation is added, and signals r0 ′ and r1 ′ are output, respectively.
- the addition units 3a and 3b are signals of the output signals r0 ′ and r1 ′ of the phase rotation unit 2. Compute the possible Euclidean distance for.
- the minimum value selection units 4a and 4b select the minimum value of the Euclidean distance from the possible symbol.
- the sign reflecting units 5a and 5b add signs according to the sign of the input value.
- the soft decision value correction units 6a and 6b select an LLR value from the selected minimum Euclidean distance.
- the phase rotation unit 2 applies 90 degree unit rotation to each symbol.
- the rotation process in units of 90 degrees can be realized by sign inversion and replacement of I-ch (real part) / Q-ch (imaginary part), and the circuit scale can be reduced.
- the adders 3a and 3b are circuits for performing addition, and are small-scale circuits as compared with the multiplication circuit.
- the minimum value selectors 4a and 4b are circuits that select the minimum value from the three values, and can be realized using two comparators and are small-scale circuits.
- the code reflecting units 5a and 5b only reflect the code according to the code of the signal r1 ', and are small-scale circuits.
- the soft decision value correction units 6a and 6b perform fixed value multiplication, but there are a method of realizing the fixed value multiplication by a bit shift and an adder, a method of table lookup using a reference table, and the like. Does not affect much.
- the prior art clarifies from the formula expansion that the minimum value selection units 4a and 4b can select from three candidate values and that the soft decision value correction units 6a and 6b can perform fixed value multiplication. This reduces the circuit scale.
- FIG. 1 shows an example of a constellation mapping diagram of a modulation scheme 8QAM corresponding to the present invention.
- S represents each symbol point (received symbol candidate point) of the symbol set in 8QAM mapping, and 4 symbols are mapped on the inner circle and the outer circle according to the length of the symbol amplitude.
- the mapping is called a star type, and even if the same star type mapping is used as shown in FIGS. 8QAM case2) is also conceivable.
- one symbol is composed of 3 bits, and can be divided into 1 bit indicating an inner circle and an outer circle and 2 bits indicating a phase of 4 symbols mapped on the inner and outer circles.
- the determination of the inner and outer circles and the position of the phase may be assigned to any bit.
- the determination bit of the inner and outer circles is assigned to the most significant bit and the phase is assigned to the lower two bits.
- the present invention by changing the direction of the rotation processing in the phase rotation portion, it is possible to cope with either of the mappings (a) and (b) in FIG. In FIG. 1A, this can be dealt with by rotating the outer circle symbol set by ⁇ 45 degrees, and in FIG. 1B, this can be dealt with by rotating the inner circle symbol set by ⁇ 45 degrees. In both (a) and (b) of FIG.
- the rotation direction is such that the lower 2 bits of the outer circle and the lower 2 bits of the inner circle are in the same quadrant.
- both (a) and (b) of FIG. 1 can be configured with the same flow. Therefore, as an outline description of the present invention, FIG. Focusing on the case of mapping and the rotation direction of the inner circle is ⁇ 45 degrees, the description will be made.
- FIG. 2 is a diagram showing a schematic configuration of the likelihood generation circuit according to the first embodiment of the present invention.
- a path 12 indicates a path when a QPSK likelihood generation method for the modulation method QPSK is selected.
- the other paths indicate paths when the 8QAM likelihood generation method is selected.
- Received symbols of received data whose modulation method is QPSK are input to the path 12, and received symbols of received data whose modulation method is 8QAM are input to the received symbol phase rotation unit 13.
- the received symbol phase rotation unit 13 rotates the input symbol to the first quadrant for the following processing.
- the phase rotation adjustment unit 14 determines the symbols of the inner circle and the outer circle.
- the threshold determination unit 14a performs symbol amplitude determination based on the threshold.
- the phase rotation processing unit 14b applies ⁇ 45 degrees rotation to the symbol determined to be the inner circle.
- the data giving -45 degree rotation is an input symbol, and is data before being processed by the received symbol phase rotation unit 13 and the threshold value determination unit 14a.
- the first likelihood generation unit (first QPSK likelihood generation unit 15a) 15 performs QPSK likelihood generation and is a circuit sharing part of the QPSK and 8QAM likelihood generation units.
- the first likelihood generator 15 generates and outputs a 2-bit likelihood.
- the QPSK likelihood generation unit 15a may have any configuration as long as the circuit configuration generates QPSK likelihood. That is, as described above, with respect to the input symbol, the minimum value (Euclidean distance) of errors from all symbol candidate points (see (b) in FIG. 1) of the pattern in which the transmission bit is 1, and the transmission bit is 0. The minimum value of errors with all symbol candidate points in the pattern to be obtained may be obtained, and a 2-bit likelihood may be generated based on the log likelihood ratio LLR of the difference. Good.
- the 2-bit likelihood output from the QPSK likelihood generation unit 15a is the likelihood in the case of a QPSK received symbol or the likelihood of the lower 2 bits of the 3 bits in the case of an 8QAM received symbol.
- the phase rotation unit 16 rotates the data (symbol) after applying the phase rotation of ⁇ 45 degrees to the first quadrant.
- the second likelihood generation unit 17 generates the highest 1-bit likelihood of 3 bits in the case of 8QAM received symbols.
- the second likelihood generation unit 17 includes an offset processing unit 17a, a constant multiplication processing unit 17b, and a QPSK likelihood generation unit (second QPSK likelihood generation unit) 17c. From the first likelihood generation unit 17, the first likelihood generation unit 15 outputs the likelihood of 1 bit out of the 2-bit likelihood output from the QPSK likelihood generation unit 17c.
- a circuit that outputs the likelihood of 3 bits for 8QAM is combined with the output of the lower 2 bits of likelihood for 8QAM.
- An input or output switching unit (indicated by a broken line) is provided for switching whether to generate a QPSK likelihood or an 8QAM likelihood.
- the received symbol phase rotation unit 13, the phase rotation adjustment unit 14, and the phase rotation unit 16 constitute a phase rotation part, and the first and second likelihood generation units 15 and 17 constitute a likelihood generation part.
- FIG. 3 and 4 are diagrams for explaining 8QAM likelihood generation processing in the processing of the likelihood generation circuit of FIG.
- FIG. 3 shows an example of bit mapping for the symbol mapping of the symbol set of FIG.
- the most significant bit is a bit indicating whether it is an inner circle or an outer circle, and the outer circle is “0” and the inner circle is “1”.
- the lower 2 bits are assigned “00” to the first quadrant symbol of the outer circle, “10” to the second quadrant symbol, “11” to the third quadrant symbol, and “01” to the fourth quadrant symbol.
- the inner circle applies the same bit mapping to the symbol at the position obtained by rotating the outer circle by 45 degrees (counterclockwise direction).
- the likelihood generation method of the lower 2 bits will be described by taking 8QAM by the bit mapping of FIG. 3 as an example.
- the data is phase-rotated to the first quadrant by the reception symbol phase rotation unit 13 of FIG.
- the threshold value determination unit 14a determines whether it is an inner circle or an outer circle based on the threshold value.
- the determination axis may be determined by either amplitude or I / Q position information.
- the received symbol phase rotation unit 13 is a process for determining only in the first quadrant, and a circuit for determining the amplitude of the inner circle and the outer circle without rotating the phase in the first quadrant according to the circuit scale. It is also possible. That is, the reception symbol phase rotation unit 13 can be omitted.
- the phase rotation processing unit 14b rotates the symbol by -45 degrees (clockwise 45 around the origin where the I axis and the Q axis intersect in the constellation mapping diagram). A process of rotating a symbol mapped on the I / Q axis into a quadrant.
- the first likelihood generation unit 15 which is a QPSK likelihood generation circuit is passed through, thereby generating the first likelihood generation.
- the unit 15 can output the 2-bit likelihood of the lower 2 bits of 8QAM. Also, since only the lower 2 bits are assigned in the quadrant direction, it is possible to apply differential encoding and decoding similar to QPSK.
- This example is bit mapping necessary for implementing the circuit of the present invention, but the bit allocation rule itself may be different.
- the policy assigns 1 bit (eg, most significant bit) of 3 bits of 8QAM depending on whether it is an inner circle or an outer circle.
- the remaining 2 bits (for example, the lower 2 bits) are assigned to one of adjacent symbols obtained by rotating the bit mapping assigned to the outer circle by ⁇ 45 degrees.
- the outer circle symbol and the symbol rotated by ⁇ 45 degrees are set to the same bit mapping in the lower 2 bits, the same configuration is obtained by rotating the symbol by 45 degrees by the phase rotation processing unit 14b. It is possible.
- the bit mapping rule is the same, and the mapping shown in FIG. 1A can be handled by making the symbol to be rotated an outer circle symbol.
- FIG. 4 shows processing from the output of the phase rotation adjustment unit 14 of FIG. 4A is a symbol mapping of the output of the phase rotation adjusting unit 14 (phase rotation processing unit 14b), and FIG. 4B is a phase mapping of the symbol mapping of FIG. 2A to the first quadrant by the phase rotating unit 16 of FIG. The symbol mapping when it is made to show is shown.
- the lower 2 bits are generated by the first likelihood generation unit 15 of FIG. 2, only the upper 1 bits are described.
- FIG. 4C shows a likelihood calculation method in the second likelihood generation unit 17.
- the offset processing in the offset processing unit 17a of the second likelihood generation unit 17 processing for moving the midpoint of the two symbols mapped in the first quadrant to the origin is performed.
- the constant multiplication processing unit 17b constant multiplication is given to the two symbols moved from the intermediate point to the origin.
- This process is a process for applying the QPSK likelihood generation process. In this way, by applying the offset and constant multiplication processing, the QPSK likelihood generation unit is shared by adjusting the symbol mapping to a range in which the likelihood can be generated by the QPSK likelihood generation unit 17c. It becomes possible to generate degrees.
- the 2-bit likelihood is output from the QPSK likelihood generation unit 17c, but in the mapping of FIG. 3, the same result is obtained regardless of which likelihood of the I / Q component is output. Either may be output. It is also possible to improve the accuracy of likelihood by likelihood addition.
- FIG. FIG. 5 is a diagram showing a schematic configuration of a likelihood generating circuit according to the second embodiment of the present invention.
- FIG. 5 shows an 8QAM likelihood generation circuit that executes another bit mapping generation method for the upper 1 bits shown in FIGS.
- the processing up to the lower 2 bits is the same as in FIG. 2, and the QPSK and 8QAM likelihood generation circuits can be shared in the same manner.
- the second likelihood generator 18 generates a remaining 1-bit likelihood.
- the second likelihood generation unit 18 outputs a calculation result of the (second) threshold determination unit 18a, the likelihood calculation unit 18b, and the likelihood calculation unit 18b different from the (first) threshold determination unit 14a.
- a soft decision table output unit 18c for providing a soft decision value.
- a modulation method selection part for example, input to at least one of the input side of the left received symbol and the output side of the right likelihood in FIG.
- an output switching unit (shown by a broken line) is provided.
- the received symbol phase rotation unit 13 and the phase rotation adjustment unit 14 constitute a phase rotation part
- the first and second likelihood generation parts 15 and 18 constitute a likelihood generation part.
- the second likelihood generation unit 18 is a 1-bit likelihood generation unit, and, as described above, the lower-order 2-bit likelihood generation method is the same as that described above. The generation process will be described.
- the (second) threshold determination unit 18a determines the area of FIG.
- the likelihood is calculated by calculating the likelihood that the bit whose likelihood is to be calculated is “1” and the symbol having the shortest Euclidean distance among the Euclidean distances of the received data and the symbol whose bit that is the target of calculation is “0”.
- the likelihood is a value obtained by multiplying the difference of the Euclidean distance of the received data having the smallest Euclidean distance by a constant.
- the Euclidean distance in which the symbol (0: s1) 201, the symbol (0: s2) 202, and the symbol (0: s3) 203 shown in FIG. 6 is “1” or “0” is set.
- Minimize Since the input of the second likelihood generation unit 18 is the output of the reception symbol phase rotation unit 13, reception data exists only in the first quadrant.
- r represents received data
- ⁇ 2 represents the variance of Gaussian noise
- the likelihood calculation unit 18b receives the result of the threshold determination, calculates the Euclidean distance between the symbol (0: s1) 201, the symbol (0: s2) 202, and the symbol (0: s3) 203 for the received data, The likelihood is calculated by calculation.
- 8QAM it is necessary to calculate the Euclidean distance between the eight symbol candidate points and the received data, select the minimum Euclidean distance, and calculate the likelihood.
- the two Euclidean distances are calculated. Likelihood can be calculated simply by calculating, and circuit reduction is possible.
- the Euclidean distance is calculated with respect to the received data by expanding the above equation. It can be expressed only by bit shift and addition, and it is not necessary to apply a multiplication circuit, and a circuit can be created.
- the soft decision table output unit 18c is a table reflecting the constant multiplication process at the time of likelihood calculation (in order to convert the likelihood value obtained by the likelihood calculation unit 18b into a likelihood value resulting from the constant multiplication process. The final likelihood value is output.
- the most significant 1 bit of the likelihood of the 8QAM received symbol is obtained by sharing the circuit for calculating the likelihood of the lower 2 bits of the likelihood of the 8QAM received symbol with the likelihood generating circuit of the QPSK. It is possible to simplify the calculation and to obtain a circuit reduction effect.
- the likelihood generating circuit according to the present invention is constituted by, for example, a microprocessor / FPGA / ASIC.
- the likelihood generating circuit and method according to the present invention can be widely applied to receiving devices in various fields.
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Abstract
Description
最初に、この発明で対応する変調方式8QAMのコンスタレーションマッピング図の一例を図1に示す。図1において、Sは8QAMマッピングにおけるシンボルセットの各シンボル点(受信シンボルの候補点)を示しており、シンボルの振幅の長さに応じて、内円と外円上に各4シンボルずつマッピングされている。8QAMのシンボルマッピング方式において、スター型と呼ばれるマッピングであり、図1の(a)、(b)のように同じスター型マッピングであっても、互いが45度回転した関係にあるマッピング(8QAM case1、8QAM case2)も考えられる。8QAMのマッピングは1シンボルが3ビットで構成されており、内円と外円を示す1ビットおよび内外円上にマッピングされている4シンボルの位相を示す2ビットに分けて考えることができる。ここで、1シンボルに割り当てられる3ビットのうち、どのビットに内外円の判定および位相の位置を割り当てても良い。本明細書では、一般性が失われることがないことより、最上位ビットに内外円の判定ビットを割り当て、下位2ビットに位相を割り当てることとして説明する。また、この発明では、位相回転部分において回転処理の方向を変えることで、図1の(a)、(b)のどちらのマッピングでも対応可能である。図1の(a)では、外円のシンボルセットを±45度回転させることで対応でき、図1の(b)では、内円のシンボルセットを±45度回転させることで対応できる。図1の(a)、(b)ともに、回転方向は、外円の下位2ビットと内円の下位2ビットが同じ象限にくる方向に回転させる。以上のように、回転させる内外円と回転方向を変えるだけで、図1の(a)、(b)ともに、同じ流れで構成できるため、この発明の概要説明としては、図1の(b)のマッピングかつ内円の回転方向が-45度の場合に着目して説明する。
図5はこの発明の実施の形態2による尤度生成回路の概略構成を示す図である。図5は、8QAMの尤度生成回路として、図3、4の上位1ビット分のビットマッピングの別の生成方法を実行するものを示す。ここで、下位2ビットまでの処理は図2と同じであり、QPSKと8QAMの尤度生成回路の共有化は同様に可能である。第2の尤度生成部18は、残り1ビットの尤度を生成する。第2の尤度生成部18は、(第1の)閾値判定部14aとは異なる(第2の)閾値判定部18a、尤度計算部18b、尤度計算部18bの演算結果を出力するサイズにする軟判定値を与える軟判定テーブル出力部18cを備える。
LLR=[1/(2σ2)](|r-s3|2-|r-s1|2) エリア#2
以上より、閾値判定部18aにおいて閾値によりエリアを判定した場合には、計算するシンボルの候補が決定する。
Claims (8)
- 変調方式QPSKおよび8QAMの受信データの受信シンボルの尤度を生成する尤度生成回路であって、
コンスタレーションマッピング図上の内円か外円かを選択するビットと、各象限を示す2ビットが割り当てられてビットマッピングされた変調方式8QAMの受信データのシンボルセットの内円または外円のシンボルを位相回転させる位相回転調整部と、
QPSK尤度生成により、変調方式QPSKの受信データの受信シンボルの尤度と共に、前記位相回転調整部で処理された変調方式8QAMのシンボルセットの象限を示す2ビットの尤度、を生成する第1の尤度生成部と、
前記位相回転調整部で処理された変調方式8QAMのシンボルセットを前記コンスタレーションマッピング図上の第1象限に位相回転させる位相回転部と、
前記位相回転部で処理された変調方式8QAMのシンボルセットを変調方式QPSKのシンボルマッピング位置に移動させて、QPSK尤度生成により変調方式8QAMのシンボルセットの内円か外円かを示すビットの尤度を生成する第2の尤度生成部と、
を備えたことを特徴とする尤度生成回路。 - 前記位相回転調整部が、
内円のシンボルか外円のシンボルかを閾値との比較により判定する閾値判定部と、
内円にあるシンボルを-45度分位相回転させる位相回転処理部と、
を含むことを特徴とする請求項1に記載の尤度生成回路。 - 前記第2の尤度生成部において、前記第1象限に位相回転されたシンボルセットにオフセットおよび定数倍の処理行って、QPSK尤度生成により変調方式8QAMのシンボルセットの内円か外円かを示すビットの尤度を生成することを特徴とする請求項1または2に記載の尤度生成回路。
- 変調方式8QAMの受信データのシンボルセットを前記コンスタレーションマッピング図上の第1象限に位相回転させる受信シンボル用位相回転部をさらに備え、前記位相回転調整部が前記受信シンボル用位相回転部で処理されたシンボルセットを位相回転させることを特徴とする請求項1から3までのいずれか1項に記載の尤度生成回路。
- 変調方式QPSKおよび8QAMの受信データの受信シンボルの尤度を生成する尤度生成回路であって、
コンスタレーションマッピング図上の内円か外円かを選択するビットと、各象限を示す2ビットが割り当てられてビットマッピングされた変調方式8QAMの受信データのシンボルセットの内円または外円のシンボルを位相回転させる位相回転調整部と、
QPSK尤度生成により、変調方式QPSKの受信データの受信シンボルの尤度と共に、前記位相回転調整部で処理された変調方式8QAMのシンボルセットの象限を示す2ビットの尤度、を生成する第1の尤度生成部と、
変調方式8QAMの受信データのシンボルセットを前記コンスタレーションマッピング図上の第1象限に位相回転させる受信シンボル用位相回転部と、
前記受信シンボル用位相回転部で処理された変調方式8QAMのシンボルセットの中から各シンボルの位置に基づいて尤度計算を行うシンボルの候補を決定し、候補のシンボルのみに基づき、変調方式8QAMのデータのシンボルセットの内円か外円かを示すビットの尤度を生成する第2の尤度生成部と、
を備えたことを特徴とする尤度生成回路。 - 前記第2の尤度生成部において、I=Qの軸を基準とするエリアとシンボルとの関係からシンボルの位置を判定することを特徴とする請求項5に記載の尤度生成回路。
- 前記位相回転調整部が、前記受信シンボル用位相回転部において前記コンスタレーションマッピング図上の第1象限に位相回転した変調方式8QAMの受信データのシンボルセットに対して位相回転を行うことを特徴とする請求項5または6に記載の尤度生成回路。
- 変調方式QPSKおよび8QAMの受信データの受信シンボルの尤度を生成する尤度生成方法であって、コンスタレーションマッピング図上の内円かまたは外円かにより変調方式8QAMの3ビット中の1ビットを割り当て、残りの2ビットは外円に割り当てたビットマッピングを±45度回転させた隣接シンボルのどちらかに割り当て、
QPSK尤度生成により、変調方式QPSKの受信データの受信シンボルの尤度と共に、位相回転処理された変調方式8QAMの受信データのシンボルセットの外円に割り当てた2ビットの尤度、を生成し、前記位相回転処理された変調方式8QAMのシンボルセットを変調方式QPSKのシンボルマッピング位置に移動させて、QPSK尤度生成により変調方式8QAMのシンボルセットの内円か外円かを示すビットの尤度を生成することを特徴とする尤度生成方法。
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