WO2015054913A1 - Structure de fet à ailette et son procédé de fabrication - Google Patents

Structure de fet à ailette et son procédé de fabrication Download PDF

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Publication number
WO2015054913A1
WO2015054913A1 PCT/CN2013/085533 CN2013085533W WO2015054913A1 WO 2015054913 A1 WO2015054913 A1 WO 2015054913A1 CN 2013085533 W CN2013085533 W CN 2013085533W WO 2015054913 A1 WO2015054913 A1 WO 2015054913A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel
gate stack
fin
width
source
Prior art date
Application number
PCT/CN2013/085533
Other languages
English (en)
Chinese (zh)
Inventor
尹海洲
刘云飞
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2015054913A1 publication Critical patent/WO2015054913A1/fr

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention provides a FinFET structure including:
  • the etch stop layer 106 is removed.
  • the etch stop layer 106 can be removed by wet etching and/or dry etching.
  • the wet etching process includes the use of a hydrogen-oxygen containing solution such as ammonium hydroxide, deionized water, or other suitable etchant solution; the dry etching process includes, for example, plasma etching or the like.
  • the semiconductor structure after the etch stop layer 106 is removed is as shown in FIG. 8.
  • FIGS. 9 and 10 respectively schematically show the semiconductor structure along the corresponding FIG. A cross-sectional view perpendicular to the channel and a top view of the semiconductor structure. It can be seen that after thinning, the thickness of the channel portion is significantly smaller than the initial thickness.
  • a village bottom 101 is provided; a fin 102 is formed on the bottom of the village, the width of the fin 102 is larger than the expected channel width; Etching stop layer 106; performing shallow trench isolation; forming a dummy gate stack over the trench to form source and drain regions; depositing an interlayer dielectric layer to planarize, exposing the dummy gate stack; removing the dummy gate stack Exposing the channel portion; thinning the channel along the sides of the channel perpendicular to the channel side surface until the desired width is obtained; removing the etch stop layer 106; sequentially depositing the gate dielectric material, the work function adjusting material And gate metal material.
  • a FinFET device having a thick source/drain region and a thin channel region can be obtained without epitaxial growth of the source and drain regions, compared with the prior art. Compared, the device performance is effectively improved, and the shape and structure of the source and drain regions are standardized, which facilitates the process of the later ILD and the process complexity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention porte sur un FET à ailette et un procédé de fabrication de ce dernier. Le procédé comprend : la fourniture d'un substrat (101) ; la formation d'une ailette (102) sur le substrat (101), la largeur de l'ailette (102) étant supérieure à une largeur prédéterminée d'un canal ; la réalisation d'une isolation de tranchée peu profonde ; la formation d'une pile de pseudo-grille (200) au-dessus du canal, et la formation d'une région de source/drain ; le dépôt d'une couche de diélectrique intercouche (105), la réalisation d'une planarisation, et la présentation de la pile de pseudo-grille (200) ; le retrait de la pile de pseudo-grille (200) pour présenter une partie de canal ; la formation d'une couche d'arrêt de gravure (106) sur le dessus du canal ; l'amincissement du canal le long de deux côtés du canal dans une direction perpendiculaire à une surface sur un côté du canal jusqu'à une épaisseur souhaitée ; et le retrait de la couche d'arrêt de gravure (106). Le procédé inhibe efficacement un effet de canal court d'un dispositif, réduit une capacité parasite de source/drain du dispositif, améliore les performances du dispositif et réduit la complexité de traitement.
PCT/CN2013/085533 2013-10-14 2013-10-21 Structure de fet à ailette et son procédé de fabrication WO2015054913A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310478725.7 2013-10-14
CN201310478725.7A CN104576385A (zh) 2013-10-14 2013-10-14 一种FinFET结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2015054913A1 true WO2015054913A1 (fr) 2015-04-23

Family

ID=52827602

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/085533 WO2015054913A1 (fr) 2013-10-14 2013-10-21 Structure de fet à ailette et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN104576385A (fr)
WO (1) WO2015054913A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180018947A (ko) * 2016-08-11 2018-02-22 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자
US9953881B2 (en) 2015-07-20 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device
CN112635481A (zh) * 2020-12-22 2021-04-09 长江存储科技有限责任公司 三维nand存储器及其制备方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109698198A (zh) * 2017-10-23 2019-04-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法
CN108470769A (zh) * 2018-03-14 2018-08-31 上海华力集成电路制造有限公司 鳍式晶体管及其制造方法
CN108470766A (zh) * 2018-03-14 2018-08-31 上海华力集成电路制造有限公司 全包覆栅极晶体管及其制造方法
WO2022016463A1 (fr) * 2020-07-23 2022-01-27 华为技术有限公司 Transistor à effet de champ à ailette et procédé de préparation
CN114068396B (zh) * 2020-07-31 2024-03-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112864251A (zh) * 2021-02-04 2021-05-28 上海华力集成电路制造有限公司 鳍式晶体管及其制造方法
WO2023035508A1 (fr) * 2021-09-07 2023-03-16 上海集成电路装备材料产业创新中心有限公司 Dispositif à semi-conducteurs de type à ailette et son procédé de préparation

Citations (6)

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US20050208715A1 (en) * 2004-03-17 2005-09-22 Hyeoung-Won Seo Method of fabricating fin field effect transistor using isotropic etching technique
CN1771589A (zh) * 2003-04-03 2006-05-10 先进微装置公司 形成FinFET装置中的栅极以及薄化该FinFET装置的沟道区中的鳍的方法
CN1961413A (zh) * 2004-06-28 2007-05-09 英特尔公司 形成半导体布线和最终器件的方法
US20100044784A1 (en) * 2004-02-24 2010-02-25 Samsung Electronics Co., Ltd. Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same
CN101853882A (zh) * 2009-04-01 2010-10-06 台湾积体电路制造股份有限公司 具有改进的开关电流比的高迁移率多面栅晶体管
CN103165447A (zh) * 2011-12-08 2013-06-19 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其制作方法

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CN107039281B (zh) * 2011-12-22 2021-06-18 英特尔公司 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1771589A (zh) * 2003-04-03 2006-05-10 先进微装置公司 形成FinFET装置中的栅极以及薄化该FinFET装置的沟道区中的鳍的方法
US20100044784A1 (en) * 2004-02-24 2010-02-25 Samsung Electronics Co., Ltd. Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same
US20050208715A1 (en) * 2004-03-17 2005-09-22 Hyeoung-Won Seo Method of fabricating fin field effect transistor using isotropic etching technique
CN1961413A (zh) * 2004-06-28 2007-05-09 英特尔公司 形成半导体布线和最终器件的方法
CN101853882A (zh) * 2009-04-01 2010-10-06 台湾积体电路制造股份有限公司 具有改进的开关电流比的高迁移率多面栅晶体管
CN103165447A (zh) * 2011-12-08 2013-06-19 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其制作方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9953881B2 (en) 2015-07-20 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device
US10522416B2 (en) 2015-07-20 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having oxide region between vertical fin structures
US11410887B2 (en) 2015-07-20 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having oxide region between vertical fin structures
US11894275B2 (en) 2015-07-20 2024-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having oxide region between vertical fin structures
KR20180018947A (ko) * 2016-08-11 2018-02-22 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자
KR102524806B1 (ko) 2016-08-11 2023-04-25 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자
US11798850B2 (en) 2016-08-11 2023-10-24 Samsung Electronics Co., Ltd. Semiconductor device including contact structure
CN112635481A (zh) * 2020-12-22 2021-04-09 长江存储科技有限责任公司 三维nand存储器及其制备方法

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