WO2015054925A1 - Structure finfet et son procédé de fabrication - Google Patents

Structure finfet et son procédé de fabrication Download PDF

Info

Publication number
WO2015054925A1
WO2015054925A1 PCT/CN2013/085620 CN2013085620W WO2015054925A1 WO 2015054925 A1 WO2015054925 A1 WO 2015054925A1 CN 2013085620 W CN2013085620 W CN 2013085620W WO 2015054925 A1 WO2015054925 A1 WO 2015054925A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
region
diffusion barrier
drain
drain extension
Prior art date
Application number
PCT/CN2013/085620
Other languages
English (en)
Chinese (zh)
Inventor
尹海洲
刘云飞
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2015054925A1 publication Critical patent/WO2015054925A1/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Definitions

  • the impurity forming the source/drain extension region is boron
  • the impurity forming the diffusion barrier is carbon, and the implantation dose is 1.5el5cm" 2 ⁇ 7.5el5ecm" 2 o
  • the present invention contemplates fabrication of a semiconductor fin 200 located above a village floor 100.
  • both the village bottom 100 and the fins 200 are composed of silicon.
  • the fin 200 is formed by epitaxially growing a semiconductor layer on the surface of the substrate 100 and etching the semiconductor layer.
  • the epitaxial growth method may be molecular beam epitaxy (MBE) or other methods, and the etching method may be dry etching. Etch or dry/wet etching.
  • the fin 200 has a height of 100 to 150 nm.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un FinFET, qui comprend les étapes suivantes : a. fournir un substrat (100), une ailette (200) et un empilement (500) de pseudo-grille; b. réaliser une injection d'ions sur la structure semi-conductrice, puis former une région (202) d'extension de source/drain; c. réaliser une injection d'ions sur la structure semi-conductrice, puis former une région (203) de blocage de diffusion, dans laquelle une position d'une valeur de concentration de pic dans la région (203) de blocage de diffusion est cohérente avec la région (202) d'extension de source/drain, c'est-à-dire qu'une erreur dans une direction de la profondeur d'une source/drain ne dépasse pas 5 nm; d. former des parois latérales (505) sur les deux côtés de l'empilement (500) de pseudo-grille; e. former une région de source/drain dans le substrat sur les deux côtés de la paroi latérale et réaliser un recuit, puis former une couche (450) diélectrique intermédiaire; et f. retirer l'empilement (500) de pseudo-grille afin de former une vacance de pseudo-grille, puis déposer une couche (600) d'empilement de grille dans la vacance de pseudo-grille. Le procédé visant à empêcher une diffusion non uniforme dans une région dopée de source/drain selon la présente invention améliore efficacement les performances du dispositif sans augmenter la complexité de traitement.
PCT/CN2013/085620 2013-10-14 2013-10-22 Structure finfet et son procédé de fabrication WO2015054925A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310478709.8A CN104576384A (zh) 2013-10-14 2013-10-14 一种finfet结构及其制造方法
CN201310478709.8 2013-10-14

Publications (1)

Publication Number Publication Date
WO2015054925A1 true WO2015054925A1 (fr) 2015-04-23

Family

ID=52827606

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/085620 WO2015054925A1 (fr) 2013-10-14 2013-10-22 Structure finfet et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN104576384A (fr)
WO (1) WO2015054925A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102552949B1 (ko) * 2016-09-02 2023-07-06 삼성전자주식회사 반도체 장치
EP3748689A1 (fr) * 2019-06-06 2020-12-09 Infineon Technologies Dresden GmbH & Co . KG Dispositif à semi-conducteur et son procédé de production

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057118A (ja) * 2000-08-09 2002-02-22 Toshiba Corp 半導体装置とその製造方法
CN1527368A (zh) * 2003-03-04 2004-09-08 松下电器产业株式会社 半导体装置及其制造方法
CN101202305A (zh) * 2006-12-13 2008-06-18 恩益禧电子股份有限公司 具有改进的源极和漏极的半导体器件及其制造方法
WO2009040707A2 (fr) * 2007-09-27 2009-04-02 Nxp B.V. Procédé de fabrication d'un transistor à effet de champ à ailettes
US20110147812A1 (en) * 2009-12-23 2011-06-23 Steigerwald Joseph M Polish to remove topography in sacrificial gate layer prior to gate patterning

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441000B2 (en) * 2006-02-01 2013-05-14 International Business Machines Corporation Heterojunction tunneling field effect transistors, and methods for fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057118A (ja) * 2000-08-09 2002-02-22 Toshiba Corp 半導体装置とその製造方法
CN1527368A (zh) * 2003-03-04 2004-09-08 松下电器产业株式会社 半导体装置及其制造方法
CN101202305A (zh) * 2006-12-13 2008-06-18 恩益禧电子股份有限公司 具有改进的源极和漏极的半导体器件及其制造方法
WO2009040707A2 (fr) * 2007-09-27 2009-04-02 Nxp B.V. Procédé de fabrication d'un transistor à effet de champ à ailettes
US20110147812A1 (en) * 2009-12-23 2011-06-23 Steigerwald Joseph M Polish to remove topography in sacrificial gate layer prior to gate patterning

Also Published As

Publication number Publication date
CN104576384A (zh) 2015-04-29

Similar Documents

Publication Publication Date Title
CN104576383B (zh) 一种FinFET结构及其制造方法
US9558946B2 (en) FinFETs and methods of forming FinFETs
US20240014294A1 (en) Semiconductor device
US7838887B2 (en) Source/drain carbon implant and RTA anneal, pre-SiGe deposition
US9337102B2 (en) Method for manufacturing semiconductor device including doping epitaxial source drain extension regions
WO2015054913A1 (fr) Structure de fet à ailette et son procédé de fabrication
US10790392B2 (en) Semiconductor structure and fabricating method thereof
WO2013078882A1 (fr) Dispositif à semi-conducteurs et procédé de fabrication associé
CN104576382B (zh) 一种非对称FinFET结构及其制造方法
WO2014026305A1 (fr) Dispositif à semi-conducteurs et son procédé de fabrication
WO2014071650A1 (fr) Dispositif à semiconducteur et son procédé de fabrication
US11837660B2 (en) Semiconductor device and method
WO2015169052A1 (fr) Procédé de fabrication de finfet
WO2013067725A1 (fr) Procédé de fabrication de structure de semi-conducteur
WO2015051560A1 (fr) Procédé pour fabriquer un finfet
WO2014071652A1 (fr) Dispositif à semiconducteur et son procédé de fabrication
WO2015054928A1 (fr) Transistor à effet de champ à ailettes et son procédé de fabrication
WO2015196639A1 (fr) Procédé de fabrication de finfet
WO2015018130A1 (fr) Structure de mosfet et son procédé de fabrication
WO2015054925A1 (fr) Structure finfet et son procédé de fabrication
WO2013159455A1 (fr) Structure de semi-conducteur et son procédé de fabrication
CN105336617B (zh) 一种FinFET制造方法
WO2015051563A1 (fr) Structure mosfet et son procédé de fabrication
WO2015051562A1 (fr) Structure de mosfet et son procédé de fabrication
CN105632929A (zh) 一种FinFET器件及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13895558

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13895558

Country of ref document: EP

Kind code of ref document: A1